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SFP+ pinSFP+ pin Schematic NameB2BNote
Transmit Data + (pin 18)MGT_TX3_PJB2-26-
Transmit Data - (pin 19)MGT_TX3_NJB2-28-
Receive Data + (pin 13)MGT_RX3_PJB2-25-
Receive Data - (pin 12)MGT_RX3_NJB2-27-
Receive Fault (pin 2)MIO10JB1-96-
Receive disable (pin 3)not connected---connected to GND
MOD-DEF2 (pin 4)MIO13JB1-983.3V pull-up, (usable I²C SDA/SCL-line)
MOD-DEF1 (pin 5)MIO12JB1-1003.3V pull-up, (usable I²C SDA/SCL-line)
MOD-DEF0 (pin 6)MIO11JB1-94-
RS0 (pin 7)not connected--
LOS (pin 8)MIO0JB1-88-
RS1 (pin 9)not connected--

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The TEBA0841 carrier board is mainly designed for the 4 x 5 SoMs TE0841 and TE0741. This SoMs have GTX-Transceiver units on their FPGA-modules with up to 8 available MGT-lanes. To test this MGT-lanes, 5 RX/TX differential pairs are bridged on-board, hence the transmitted data on this MGT-lanes flows back to their sources in a loop-back circuit without intentional processing or modification. 

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Note
Note: The mounted TE 4 x 5 SoMs have different schematic net-names of the differential signaling pairs of the MGT-lanes. See Schematic of the particular SoM.

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JX1 pinJX1 pin Schematic NameB2B J3 pinJ3 pin Schematic NameB2B
C (pin 4)TCKJB3-100 4TCKJB3-100
D (pin 8)TDOJB3-98 8TDOJB3-98
F (pin 10)TDIJB3-96 10TDIJB3-96
H (pin 12)TMSJB3-94 12TMSJB3-94
A (pin 3)MIO15JB1-86 (usable as UART RX- / TX-line) 3MIO15JB1-86 (usable as UART RX- / TX-line)
B (pin 7)MIO14JB1-91 (usable as UART RX- / TX-line) 7MIO14JB1-91 (usable as UART RX- / TX-line)
E (pin 9)BOOTMODEJB1-90 (JTAGSELECT) 9BOOTMODEJB1-90 (JTAGSELECT)
G (pin 11)RESINJB3-17 11RESINJB3-17
--- 15CLK0_NJB2-32 (MGT_CLK0_N, decoupling capacitator 100 nF)
--- 16CLK0_PJB2-34 (MGT_CLK0_P, decoupling capacitator 100 nF)

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 The dimensions are given in mm and mil (milli inch).

Image Modified

Figure 4: Physical Dimensions of the TEBA0841-01 carrier board

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DateRevisionAuthorsDescription
2017-06-0827
Ali Nasericurrent TRM for TEBA0841-01
2017-01-300.1

Ali Naseri

Initial document

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