Page History
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| Connector Designator | Pin-header Layout | Count of IO's | Count of LVDS-pairs | Available VCCIO's | Interfaces |
|---|---|---|---|---|---|
| J4 | 2-row 10-pin | 6 | 0 | 3.3V, | SDIO (6 IO's), if available on mounted 4 x 5 SoM. Voltage-translation via SDIO port expander (e.g. Texas Instruments TXS02612) necessary |
| J17 | 2-row 50-pin | 42 | 21 | 3.3V, | - |
| J20 | 2-row 50-pin | 42 | 21 | 3.3V; VCCIOA | - |
| J3 | 2-row 16-pin | 12 | 1 | 3.3V | JTAG (4 IO's). UART (2 IO's). Reference clock input MGT-CLK0 (1 LVDS-pair). |
Table 5: Summary of optional pin-headers
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Following table describes how to configure the base-board supply-voltages by jumpers:
Base-board Supply Voltages | VCCIOA | VCCIOD |
|---|---|---|
| 1.8V | J26:1-2 | J27:1-2 |
| 2.5V | J26:3-4 | J27:3-4 |
| 3.3V | J26:5-6 | J27:5-6 |
Table 6: Configuration of base-board supply-voltages via jumpers. Jumper-Notification: 'Jx: 1-2' means pins 1 and 2 are connected, 'Jx: 3-4' means pins 3 and 4 are connected, and so on.
| Note |
|---|
Take care of the VCCO voltage ranges of the particular PL IO-banks (HR, HP) of the mounted SoM, otherwise damages may occur to the FPGA. Therefore, refer to the TRM of the mounted SoM to get the specific information of the voltage ranges. It is recommended to set and measure the PL IO-bank supply-voltages before mounting of TE 4 x 5 module to avoid failures and damages to the functionality of the mounted SoM. |
Technical Specifications
Absolute Maximum Ratings
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