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Signals, Interfaces and Pins
I/O Banks
| Bank | VCCIO | B2B I/O | Notes |
|---|---|---|---|
| 0 | 3.3V | 0 | JTAG |
| 14 | 3.3V | 0 (3) | 3 I/O in XMOD-JTAG - for use as UART |
| 15 | 1.8V | 0 | used for optional hyper RAM |
| 16 | 2.5V | 0 | used for optional optical fiber transceiver |
| 34 | User select | 42 | 0R resistor option to select 3.3V |
| 35 | User select | 42 | 0R resistor option to select 3.3V |
JTAG Interface
JTAG access to the Xilinx Artix-7 device is provided through connector JB1.
| Signal | Pin Number |
|---|---|
| TCK | JB1-4 |
| TDO | JB1-8 |
| TDI | JB1-10 |
| TMS | JB1-12 |
Connector JB1 (2 x 6 pin header) is compatible with XMOD JTAG adapter TE0790. This adapter can be inserted from top onto the TE0725LP, if JB1 is fitted with male pin header. Optionally JB1 can be fitted with pin header from bottom, in that case the JTAG cable connector must be on the base board.
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When using XMOD-JTAG please check the switch settings on XMOD to be sure the power and I/O reference are supplied correctly. TE0790 can be in some cases used to power up TE0725LP, however this is not recommended. TE0790-01 can not supply enough power for TE0725LP (LED may blink but the module is not operating properly, especially in case of larger and more sophisticated designs).
On-board LED's
| LED | Color | FPGA | Notes |
|---|---|---|---|
| D2 | Green | M16 | |
| D3 | Red | DONE | Active low |
Connectors
All connectors are are for 100mil headers, all connector locations are in 100 mil grid.
| LED | Color | FPGA | Notes |
|---|---|---|---|
| D2 | Green | M16 | |
| D3 | Red | DONE | Active low |
Power and Power-On Sequence
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TE0725LP needs one single power supply with nominal of 3.3V.
Power Consumption
| FPGA | Design | Typical Power, 25C ambient |
|---|---|---|
| A100T | Not configured | TBD* |
*TBD - To Be Determined.
Actual power consumption depends on the FPGA design and ambient temperature.
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Variants Currently In Production
| Module Variant | FPGA Chip Model | PL Clock [MHz] | VIN Supply Voltage |
|---|---|---|---|
| TE0725LP-01-100-2C | XC7A100T-2CSG324C | 3.3 V | |
| TE0725LP-01-100-2D | XC7A100T-2CSG324C | 1.8 V | |
| TE0725LP-01-100-2L | XC7A100T-2CSG324C | 1.8 V |
Technical Specifications
Absolute Maximum Ratings
Parameter | Min | Max | Units | Reference document |
|---|---|---|---|---|
3.3V supply voltage | -0.1 | 3.6 | V | |
| HR I/O banks supply voltage (VCCO) | -0.5 | 3.6 | V | Xilinx datasheet DS181 |
| HR I/O banks input voltage | -0.4 | VCCO + 0.55 | V | Xilinx datasheet DS181 |
Storage Temperature | -40 | +85 | °C |
Recommended Operating Conditions
| Parameter | Min | Max | Units | Reference document |
|---|---|---|---|---|
| VIN supply voltage | 3.135 | 3.45 | V | |
| HR I/O banks supply voltage (VCCO) | 1.14 | 3.465 | V | Xilinx datasheet DS181 |
| HR I/O banks input voltage | -0.20 | VCCO + 0.20 | V | Xilinx datasheet DS181 |
| Operating Temperature | 0 | +85 | °C |
| Note |
|---|
| Please check Xilinx datasheet DS181 for complete list of absolute maximum and recommended operating ratings for the Artix-7 device. |
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Hardware Revision History
| Date | Revision | Notes | PCN | Documentation Link |
|---|---|---|---|---|
| 2016-07-21 | 01 | Prototypes |
Hardware revision number is printed on the PCB board together with the module model number separated by the dash.
Document Change History
| Date | Revision | Contributors | Description |
|---|---|---|---|
| 2017-08-17 | Jan Kumann | Initial version. |
Disclaimer
| Include Page | ||||
|---|---|---|---|---|
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