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Power Rail Name	B2B J1 Pins	B2B J2 Pins	B2B J3 Pins	B2B J4 Pins	Directions	Note
PL_DCIN	151, 153, 155, 157, 159	-	-	-	Input	-
DCDCIN	-	154, 156, 158, 160, 153, 155, 157, 159	-	-	Input	-
LP_DCDC	-	138, 140, 142, 144	-	-	Input	-
PS_BATT	-	125	-	-	Input	-
GT_DCDC	-	-	157, 158, 159, 160	-	Input	-
PLL_3V3	-	-	152	-	Input	U5 (programmable PLL) 3.3V nominal input
SI_PLL_1V8	-	-	151	-	Output	Internal voltage level 1.8V nominal output
PS_1V8	-	99	147, 148	-	Output	Internal voltage level 1.8V nominal output
PL_1V8	91, 121	-	-	-	Output	Internal voltage level 1.8V nominal output
DDR_1V2	-	135	-	-	Output	Internal voltage level 1.2V nominal output
VCCO47	-	-	43, 44	-	Input	-
VCCO48	-	-	15, 16	-	Input	-
VCCO64	-	-	-	58, 106	Input	-
VCCO65	-	-	-	69, 105	Input	-
VCCO66	90, 120	-	-	-	Input	-

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Parameter	Min	Max	Unit	Notes / Reference Document
PL_DCIN	-0.3	74	V	TPS82085SIL / EN63A0QI data sheet/ Limit is LP_DCDC over EN/PG
DCDCIN	-0.3	74	V	TPS82085SIL / TPS51206 data sheet/ Limit is LP_DCDC over EN/PG
LP_DCDC	-0.3	4	V	TPS3106K33DBVR data sheet
GT_DCDC	-0.3	74	V	TPS82085SIL data sheet/ Limit is LP_DCDC over EN/PG
PS_BATT	-0.5	2	V	Xilinx DS925 data sheet
PLL_3V3	-0.5	3.8	V	Si5345/44/42 data sheet
VCCO for HD I/O banks	-0.5	3.4	V	Xilinx DS925 data sheet
VCCO for HP I/O banks	-0.5	2	V	Xilinx DS925 data sheet
I/O input voltage for HD I/O banks	-0.55	VCCO + 0.55	V	Xilinx DS925 data sheet
I/O input voltage for HP I/O banks	-0.55	VCCO + 0.55	V	Xilinx DS925 data sheet
PS I/O input voltage (MIO pins)	-0.5	VCCO_PSIO + 0.55	V	Xilinx DS925 data sheet, VCCO_PSIO 1.8V nominally
PS GTR reference clocks absolute input voltage	-0.5	1.1	V	Xilinx document DS925
PS GTR absolute input voltage	-0.5	1.1	V	Xilinx document DS925
MGT clock absolute input voltage	-0.5	1.3	V	Xilinx document DS925
MGT Receiver (RXP/RXN) and transmitter (TXP/TXN) absolute input voltage	-0.5	1.2	V	Xilinx DS925 data sheet
Voltage on input pins of NC7S08P5X 2-Input AND Gate	-0.5	VCC + 0.5	V	NC7S08P5X data sheet, see schematic for VCC
Voltage on input pins (nMR) of TPS3106K33DBVR Voltage Monitor, U41	-0.3	VDD + 0.3	V	TPS3106 data sheet, VDD = LP_DCDC
"Enable"-signals on TPS82085SIL (EN_PLL_PWR, EN_LPD)	-0.3	7	V	TPS82085SIL data sheet
Storage temperature (ambient)	-40	100	°C	ROHM Semiconductor SML-P11 Series data sheet

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Parameter	Min	Max	Unit	Notes / Reference Document
PL_DCIN	3.3	3.6	V	EN63A0QI / TPS82085SIL data sheet/ Limit is LP_DCDC over EN/PG
DCDCIN	3.3	3.6	V	TPS82085SIL / TPS51206PSQ data sheet/ Limit is LP_DCDC over EN/PG
LP_DCDC	3.3	3.6	V	TPS82085SIL / TPS3106 data sheet
GT_DCDC	3.3	3.6	V	TPS82085SIL data sheet/ Limit is LP_DCDC over EN/PG
PS_BATT	1.2	1.5	V	Xilinx DS925 data sheet
PLL_3V3	3.3	3.47	V	Si5345/44/42 data sheet 3.3V typical
VCCO for HD I/O banks	1.14	3.4	V	Xilinx DS925 data sheet
VCCO for HP I/O banks	0.95	1.9	V	Xilinx DS925 data sheet
I/O input voltage for HD I/O banks.	-0.2	VCCO + 0.2	V	Xilinx DS925 data sheet
I/O input voltage for HP I/O banks	-0.2	VCCO + 0.2	V	Xilinx DS925 data sheet
PS I/O input voltage (MIO pins)	-0.2	VCCO_PSIO + 0.2	V	Xilinx DS925 data sheet, VCCO_PSIO 1.8V nominally
PL bank reference voltage VREF pin	-0.5	2	V	Xilinx DS925 data sheet
Voltage on input pins of NC7S08P5X 2-Input AND Gate	0	VCC	V	NC7S08P5X data sheet, see schematic for VCC
Voltage on input pin 'MR' of TPS3106K33DBVR Voltage Monitor, U41	0	VDD	V	TPS3106 data sheet, VDD = LP_DCDC

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Date

Revision

Contributors

Description

Page info

Page info

Page info

2021-06-10

v.27

John Hartfiel

2021-05-17

v.26

John Hartfiel

2021-05-03

v.25

Martin Rohrmüller

2021-03-11

v.24

Antti Lukats

2019-06-14

v.22

John Hartfiel

2018-08-07

v.20

Ali Naseri

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