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Online version of this manual and other related documents can be found at https://wiki.trenz-electronic.de/display/PD/Trenz+Electronic+Documentation

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Table of contents

Table of Contents
outlinetrue

Overview

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Key Features

  • PetaLinux
  • SD
  • ETH
  • USB
  • U2C
  • RTC

Revision History

...

Release Notes and Know Issues

...

Requirements

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Software

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Hardware

Basic description of TE Board Part Files is available on TE Board Part Files.

Complete List is available on <design name>/board_files/*_board_files.csv

Design supports following modules:

...

Design supports following modules:

...

Additional HW Requirements

...

Content

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For general structure and of the reference design, see Project Delivery

Design Sources

...

Additional Sources

...

Download

Reference Design is only usable with the specified Vivado/SDK/PetaLinux/SDx version. Do never use different Versions of Xilinx Software for the same Project.

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Reference Design is available on:

Design Flow

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Note

Reference Design is also available with prebuilt files. It's recommended to use TE prebuilt files for first lunch.

 

Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow. See: Vivado/SDK/SDSoC#XilinxSoftware-BasicUserGuides and Project Delivery

The most Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.

TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/SDK GUI.  For currently limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality

 

...

  1. Select correct device on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
    Note: Select correct one, see TE Board Part Files

...

  1. Run on Vivado TCL: TE::hw_build_design -export_prebuilt
    Note: Script generate design and export files into \prebuilt\hardware\<short dir>. Use GUI is the same, except file export to prebuilt folder

...

  1. HDF is exported to "prebuilt\hardware\<short name>"
    Note: HW Export from Vivado GUI used default another path.
  2. Create Linux images on VM, see PetaLinux KICKstart
    1. Use TE Template from /os/petalinux

...

  1. "prebuilt\os\petalinux\default" or "prebuilt\os\petalinux\<short name>"
    Notes: Scrips select "prebuilt\os\petalinux\<short name>", if exist, otherwise "prebuilt\os\petalinux\default"

...

Launch

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Note

Check Module and Carrier TRMs for proper HW configuration before you try any design.

Reference Design is also available with prebuilt files. It's recommended to use TE prebuilt files for first lunch.

Programming

Xilinx documentation for programming and debugging: Vivado/SDK/SDSoC-Xilinx Software Programming and Debugging

QSPI

Not used on this Example.

SD

  1. Copy image.ub and Boot.bin on SD-Card.
    • For correct prebuilt file location, see <design_name>/prebuilt readme_file_location.txt
  2. Set Boot Mode to SD-Boot.
    • Depends on Carrier, see carrier TRM.
  3. Insert SD-Card in SD-Slot.

JTAG

Not used on this Example.

Usage

...

  1. Speed: 115200
  2. COM Port: Win OS, see device manager, Linux OS see  dmesg |grep tty  (UART is *USB1)

...

  1. User Name: root
  2. Password: root

...

  1. Set radix from VIO signals to unsigned integer.
  2. MGT CLK is configured to 125MHz by default, FCLK is not configured by default.

...

System Design - Vivado

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Description currently not available.

Design

 

Block Design

Constrains

Software Design - SDK/HSI

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Description currently not available.

Application

FSBL

Software Design -  PetaLinux

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Description currently not available.

Config

U-Boot

Device Tree

Kernel

Rootfs

Appx. A: Change History and Legal Notices

Document Change History

To get content of older revision  got to "Change History"  of this page and select older document revision number.

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Design Name is always "TE Series Name" + Design name, for example "TE0720 Test Board"


Date

Version

Changes

Author

2022-01-253.1.10
  • removed u-boot.dtb from QSPI-Boot mode and SD-Boot mode. Is implemented in BOOT.bin
  • corrected Boot Source File in Boot Script-File
ma
2022-01-143.1.9
  • extended notes for microblaze boot process with linux
  • add u.boot.dtb to petalinux notes
  • add dtb to prebuilt content
  • replace 20.2 with 21.2
jh
2021-06-283.1.8
  • added boot process for Microblaze
  • minor typos, formatting
ma
2021-06-013.1.7
  • carrier reference note
jh
2021-05-043.1.6
  • removed zynq_ from zynq_fsbl
ma
2021-04-283.1.5
  • added macro "Scroll ignore" for suppression of horizontal dividing lines during .pdf-export
  • minor typos, formatting
ma
2021-04-27

3.1.4

  • Version History

    • changed from list to table

  • Design flow

    • removed step 5 from Design flow

    • changed link from TE Board Part Files to Vivado Board Part Flow

    • changed cmd shell from picture to codeblock

    • added hidden template for "Copy PetaLinux build image files", depending from hardware

    • added hidden template for "Power on PCB", depending from hardware

  • Usage update of boot process

  • Requirements - Hardware

    • added "*used as reference" for hardware requirements

  • all

    • placed a horizontal separation line under each chapter heading

    • changed title-alignment for tables from left to center

  • all tables

    • added "<project folder>\board_files" in Vivado design sources

ma


3.1.3

  • Design Flow

    • formatting

  • Launch

    • formatting

ma


3.1.2

  • minor typing corrections

  • replaced SDK by Vitis

  • changed from / to \ for windows paths

  • replaced <design name> by <project folder>

  • added "" for path names

  • added boot.src description

  • added USB for programming

ma


3.1.1

  • swapped order from prebuilt files

  • minor typing corrections

  • removed Win OS path length from Design flow, added as caution in Design flow

ma


3.1

  • Fix problem with pdf export and side scroll bar

  • update 19.2 to 20.2

  • add prebuilt content option



3.0

  • add fix table of content

  • add table size as macro

  • removed page initial creator



Custom_table_size_100

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Important General Note:

  • Export PDF to download, if vivado revision is changed!

  • Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro

    • Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)

      • Figure template (note: inner scroll ignore/only only with drawIO object):

        Scroll Title
        anchorFigure_xyz
        titleText


        Scroll Ignore

        Create DrawIO object here: Attention if you copy from other page, use


        Scroll Only

        image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed



      • Table template:

        • Layout macro can be use for landscape of large tables

        • Set column width manually (can be used for small tables to fit over whole page) or leave empty (automatically)


      • Scroll Title
        anchorTable_xyz
        titleText

        Scroll Table Layout
        orientationportrait
        sortDirectionASC
        repeatTableHeadersdefault
        style
        widths
        sortByColumn1
        sortEnabledfalse
        cellHighlightingtrue

        Example

        Comment

        1

        2



  • ...

Overview

Scroll Ignore
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scroll-officetrue
scroll-chmtrue
scroll-docbooktrue
scroll-eclipsehelptrue
scroll-epubtrue
scroll-htmltrue


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Notes :

Zynq Design PS with Linux and simple frequency counter to measure MGT Reference CLK with Vivado HW-Manager.

Refer to http://trenz.org/te0715-info for the current online version of this manual and other available documentation.

Key Features

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Notes :

  • Add basic key features, which can be tested with the design


Excerpt
  • Vitis/Vivado 2021.2
  • PetaLinux
  • SD
  • ETH
  • MAC from EEPROM
  • USB
  • I2C
  • RTC
  • FMeter
  • Modified FSBL (some additional outputs and SI5338 reconfiguration)
  • Special FSBL for QSPI Programming

Revision History

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Notes :

  • add every update file on the download
  • add design changes on description


Scroll Title
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DateVivadoProject BuiltAuthorsDescription
2022-02-092021.2TE0715-test_board-vivado_2021.2-build_11_20220208131345.zip
TE0715-test_board_noprebuilt-vivado_2021.2-build_11_20220208131345.zip
Manuela Strücker
  • 2021.2 update
2021-12-162020.2TE0715-test_board-vivado_2020.2-build_9_20211216124925.zip
TE0715-test_board_noprebuilt-vivado_2020.2-build_9_20211216124901.zip
Manuela Strücker
  • new Assembly variants
2021-06-162020.2TE0715-test_board-vivado_2020.2-build_5_20210611100936.zip
TE0715-test_board_noprebuilt-vivado_2020.2-build_5_20210611100742.zip
Manuela Strücker
  • update mount function (from busybox to util-linux 2.34)
2021-05-312020.2TE0715-test_board-vivado_2020.2-build_5_20210531083131.zip
TE0715-test_board_noprebuilt-vivado_2020.2-build_5_20210531083148.zip

John Hartfiel/

Manuela Strücker

  • bugfix TE0715_board_files.csv for  TE0715-04-71I33-L ID
2021-04-272020.2

TE0715-test_board-vivado_2020.2-build_5_20210428094945.zip
TE0715-test_board_noprebuilt-vivado_2020.2-build_5_20210428095209.zip

John Hartfiel/
Manuela Strücker

  • update to vivado version 2020.2
  • implemented boot.scr file for distro_boot
2020-06-102019.2TE0715-test_board-vivado_2019.2-build_12_20200610070857.zip
TE0715-test_board_noprebuilt-vivado_2019.2-build_12_20200610071014.zip
John Hartfiel
  • bugfix usb reset
  • changes device tree for eeprom mac
  • new variants
2019-05-092018.3TE0715-test_board-vivado_2018.3-build_05_20190509094447.zip
TE0715-test_board_noprebuilt-vivado_2018.3-build_05_20190509094505.zip
John Hartfiel
  • TE Script update
  • rework of the FSBLs
  • some additional Linux features
  • MAC from EEPROM
2018-10-012018.2TE0715-test_board-vivado_2018.2-build_03_20181001131411.zip
TE0715-test_board_noprebuilt-vivado_2018.2-build_03_20181001131421.zip
John Hartfiel
  • Rework Board Part Files (PS)
  • small design changes
  • SI5338 reconfiguration default activated on FSBL
  • update linux startup app
2018-04-262017.4TE0715-test_board-vivado_2017.4-build_07_20180426171530.zip
TE0715-test_board_noprebuilt-vivado_2017.4-build_07_20180426171546.zip
John Hartfiel
  • new assembly variant
2018-03-272017.4te0715-test_board-vivado_2017.4-build_07_20180327223552.zip
te0715-test_board_noprebuilt-vivado_2017.4-build_07_20180327223606.zip
John Hartfiel
  • Board Part Bug fix with UART 1
2018-01-052017.4te0715-test_board-vivado_2017.4-build_01_20180105195436.zip
te0715-test_board_noprebuilt-vivado_2017.4-build_01_20180105195452.zip
John Hartfiel
  • No Design changes
  • Add FSBL for Flash Programming
2017-11-102017.2te0715-test_board-vivado_2017.2-build_05_20171110134232.zip
te0715-test_board_noprebuilt-vivado_2017.2-build_05_20171110134247.zip
John Hartfiel
  • New Web Link on Board Part Files
  • Add optional FSBL Code to reprogram  SI5338
2017-10-192017.2te0715-test_board-vivado_2017.2-build_04_20171019141808.zip
te0715-test_board_noprebuilt-vivado_2017.2-build_04_20171019141825.zip
John Hartfiel
  • changed Flash typ on TE0715_board_files.csv
    (older one is not supported on Vivado 2017.2)
2017-09-222017.2te0715-test_board-vivado_2017.2-build_02_20170927143412.zip
te0715-test_board_noprebuilt-vivado_2017.2-build_02_20170927143427.zip
John Hartfiel
  • initial release


Release Notes and Know Issues

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Notes :
  • add known Design issues and general notes for the current revision
  • do not delete known issue, add fixed version time stamp if issue fixed


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titleKnown Issues

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IssuesDescriptionWorkaroundTo be fixed version
QSPI FlashProgramming QSPI fails with Vivado 2021.2use Vivado 2020.2 or 2019.2 for programming
Timing problems with Frequency countercan be ignored---with 2018-10-01 update


Requirements

Software

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Notes :

  • list of software which was used to generate the design


Scroll Title
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titleSoftware

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SoftwareVersionNote
Vitis2021.2needed, Vivado is included into Vitis installation
PetaLinux2021.2needed
SI ClockBuilder Pro---optional



Hardware

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Notes :

  • list of hardware which was used to generate the design
  • mark the module and carrier board, which was used tested with an *
Basic description of TE Board Part Files is available on TE Board Part Files.

Complete List is available on "<project folder>\board_files\*_board_files.csv"


Design supports following modules:

Scroll Title
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Module ModelBoard Part Short NamePCB Revision SupportDDRQSPI FlashEMMCOthersNotes
TE0715-02-15-1C03_15_1c_1gbREV02|REV011GB32MBNANANA
TE0715-02-15-1I03_15_1i_1gbREV02|REV011GB32MBNANANA
TE0715-02-15-1I103_15_1i_1gbREV02|REV011GB32MBNANANA
TE0715-02-30-1C03_30_1c_1gbREV02|REV011GB32MBNANANA
TE0715-02-30-1I03_30_1i_1gbREV02|REV011GB32MBNANANA
TE0715-03-15-1I03_15_1i_1gbREV031GB32MBNANANA
TE0715-03-15-1I303_15_1i_1gbREV031GB32MBNANANA
TE0715-03-15-2I03_15_2i_1gbREV031GB32MBNANANA
TE0715-03-30-1C03_30_1c_1gbREV031GB32MBNANANA
TE0715-03-30-1I03_30_1i_1gbREV031GB32MBNANANA
TE0715-03-30-1I303_30_1i_1gbREV031GB32MBNANANA
TE0715-03-30-3E03_30_3e_1gbREV03|REV02|REV011GB32MBNANANA
TE0715-04-12S-1C04_12s_1c_1gbREV041GB32MBNANALow Power DDR
TE0715-04-15-1I04_15_1i_1gbREV041GB32MBNANALow Power DDR
TE0715-04-15-1I304_15_1i_1gbREV041GB32MBNANALow Power DDR 2.5mm connector
TE0715-04-15-1IC04_15_1i_1gbREV041GB32MBNANALow Power DDR. 3M NOVEC coating
TE0715-04-15-2I*04_15_2i_1gbREV041GB32MBNANALow Power DDR
TE0715-04-21C33-A04_12s_1c_1gbREV041GB32MBNANALow Power DDR
TE0715-04-30-1C04_30_1c_1gbREV041GB32MBNANALow Power DDR
TE0715-04-30-1I04_30_1i_1gbREV041GB32MBNANALow Power DDR
TE0715-04-30-1I304_30_1i_1gbREV041GB32MBNANALow Power DDR. 2.5mm connector
TE0715-04-30-1IA04_30_1i_1gbREV041GB32MBNANALow Power DDR. Micron Flash
TE0715-04-30-3E04_30_3e_1gbREV041GB32MBNANALow Power DDR
TE0715-04-51I33-A04_15_1i_1gbREV041GB32MBNANALow Power DDR
TE0715-04-51I33-AN04_15_1i_1gbREV041GB32MBNANALow Power DDR. 3M NOVEC coating
TE0715-04-51I33-L04_15_1i_1gbREV041GB32MBNANALow Power DDR 2.5mm connector
TE0715-04-52I33-A04_15_2i_1gbREV041GB32MBNANALow Power DDR
TE0715-04-71C33-A04_30_1c_1gbREV041GB32MBNANALow Power DDR
TE0715-04-71I33-A04_30_1i_1gbREV041GB32MBNANALow Power DDR
TE0715-04-71I33-L04_30_1i_1gbREV041GB32MBNANALow Power DDR. 2.5mm connector
TE0715-04-73E33-A04_30_3e_1gbREV041GB32MBNANALow Power DDR
TE0715-04-30-1IY04_30_1i_1gbREV041GB32MBNANALow Power DDR, without RTC
TE0715-04-51I33-AY04_15_1i_1gbREV041GB32MBNANALow Power DDR, without RTC
TE0715-04-52I33-AY04_15_2i_1gbREV041GB32MBNANALow Power DDR, without RTC
TE0715-04-71C33-AY04_30_1c_1gbREV041GB32MBNANALow Power DDR, without RTC
TE0715-04-71I33-AY04_30_1i_1gbREV041GB32MBNANALow Power DDR, without RTC
TE0715-04-71I33-LY04_30_1i_1gbREV041GB32MBNANALow Power DDR. 2.5mm connector, without RTC
TE0715-04-S00304_30_1i_1gbREV041GB32MBNANACAO: Low Power DDR

*used as reference



Design supports following carriers:

Scroll Title
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Carrier ModelNotes
TE0701
TE0703
TE0705
TE0706*
TEBA0841-02

*used as reference

Additional HW Requirements:

Scroll Title
anchorTable_AHW
title-alignmentcenter
titleAdditional Hardware

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Additional HardwareNotes
USB Cable for JTAG/UARTCheck Carrier Board and Programmer for correct type
XMOD ProgrammerCarrier Board dependent, only if carrier has no own FTDI


Content

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Notes :

  • content of the zip file

For general structure and usage of the reference design, see Project Delivery - Xilinx devices

Design Sources

Scroll Title
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titleDesign sources

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TypeLocationNotes
Vivado

<project folder>\block_design
<project folder>\constraints
<project folder>\ip_lib
<project folder>\board_files

Vivado Project will be generated by TE Scripts
Vitis<project folder>\sw_libAdditional Software Template for Vitis and apps_list.csv with settings automatically for Vitis app generation
PetaLinux<project folder>\os\petalinuxPetaLinux template with current configuration




Additional Sources

Scroll Title
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titleAdditional design sources

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TypeLocationNotes
SI5338<project folder>\misc\Si5338SI5338 Project with current PLL Configuration
init.sh<project folder>\misc\sd\Additional Initialization Script for Linux (working from sd card only)



Prebuilt

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Notes :

  • prebuilt files
  • Template Table:

    • Scroll Title
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      titlePrebuilt files

      Scroll Table Layout
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      File

      File-Extension

      Description

      BIF-File*.bifFile with description to generate Bin-File
      BIN-File*.binFlash Configuration File with Boot-Image (Zynq-FPGAs)
      BIT-File*.bitFPGA (PL Part) Configuration File
      Boot Script-File*.scr

      Distro Boot Script file

      DebugProbes-File*.ltxDefinition File for Vivado/Vivado Labtools Debugging Interface

      Debian SD-Image

      *.img

      Debian Image for SD-Card

      Diverse Reports---Report files in different formats
      Device Tree*.dtsDevice tree (2 possible, one for u-boot and one for linux)
      Hardware-Platform-Description-File*.xsaExported Vivado hardware description file for Vitis and PetaLinux
      LabTools Project-File*.lprVivado Labtools Project File

      MCS-File

      *.mcs

      Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)

      MMI-File

      *.mmi

      File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)

      OS-Image*.ubImage with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)
      Software-Application-File*.elfSoftware Application for Zynq or MicroBlaze Processor Systems

      SREC-File

      *.srec

      Converted Software Application for MicroBlaze Processor Systems




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File

File-Extension

Description

BIF-File*.bifFile with description to generate Bin-File
BIN-File*.binFlash Configuration File with Boot-Image (Zynq-FPGAs)
BIT-File*.bitFPGA (PL Part) Configuration File
Boot Script-File*.scr

Distro Boot Script file

DebugProbes-File*.ltxDefinition File for Vivado/Vivado Labtools Debugging Interface
Diverse Reports---Report files in different formats
Device Tree*.dtsDevice tree (2 possible, one for u-boot and one for linux)
Hardware-Platform-Description-File*.xsaExported Vivado hardware description file for Vitis and PetaLinux
LabTools Project-File*.lprVivado Labtools Project File
OS-Image*.ubImage with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)
Software-Application-File*.elfSoftware Application for Zynq or MicroBlaze Processor Systems



Download

Reference Design is only usable with the specified Vivado/Vitis/PetaLinux version. Do never use different Versions of Xilinx Software for the same Project.

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Reference Design is available on:

Design Flow

Scroll Ignore
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scroll-eclipsehelptrue
scroll-epubtrue
scroll-htmltrue


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Notes :
  • Basic Design Steps

  • Add/ Remove project specific description


Note

Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first launch.

Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.

See also:

The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.

TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/Vitis GUI.  For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality

Note

Caution! Win OS has a 260 character limit for path lengths which can affect the Vivado tools. To avoid this issue, use Virtual Drive or the shortest possible names and directory locations for the reference design (for example "x:\<project folder>")

  1. Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:

    Code Block
    languagebash
    themeMidnight
    title_create_win_setup.cmd/_create_linux_setup.sh
    ------------------------Set design paths----------------------------
    -- Run Design with: _create_win_setup
    -- Use Design Path: <absolute project path>
    --------------------------------------------------------------------
    -------------------------TE Reference Design---------------------------
    --------------------------------------------------------------------
    -- (0)  Module selection guide, project creation...prebuilt export...
    -- (1)  Create minimum setup of CMD-Files and exit Batch
    -- (2)  Create maximum setup of CMD-Files and exit Batch
    -- (3)  (internal only) Dev
    -- (4)  (internal only) Prod
    -- (c)  Go to CMD-File Generation (Manual setup)
    -- (d)  Go to Documentation (Web Documentation)
    -- (g)  Install Board Files from Xilinx Board Store (beta)
    -- (a)  Start  design with unsupported Vivado Version (beta)
    -- (x)  Exit Batch (nothing is done!)
    ----
    Select (ex.:'0' for module selection guide):


  2. Press 0 and enter to start "Module Selection Guide"
  3. Createproject and follow instructions of the product selection guide, settings file will be configured automatically during this process.
    • optional for manual changes: Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"

      Note

      Note: Select correct one, see also Vivado Board Part Flow


  4. Create hardware description file (.xsa file) for PetaLinux project and export to prebuilt folder

    Code Block
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    titlerun on Vivado TCL (Script generates design and export files into "<project folder>\prebuilt\hardware\<short name>")
    TE::hw_build_design -export_prebuilt


    Info

    Using Vivado GUI is the same, except file export to prebuilt folder.


  5. Create and configure your PetaLinux project with exported .xsa-file, see PetaLinux KICKstart
    • use TE Template from "<project folder>\os\petalinux"
    • use exported .xsa file from "<project folder>\prebuilt\hardware\<short name>" . Note: HW Export from Vivado GUI creates another path as default workspace.

    • The build images are located in the "<plnx-proj-root>/images/linux" directory

  6. Configure the boot.scr file as needed, see Distro Boot with Boot.scr

  7. Copy PetaLinux build image files to prebuilt folder
    • copy u-boot.elf, u-boot.dtb, system.dtb, image.ub and boot.scr from "<plnx-proj-root>/images/linux" to prebuilt folder

      Info

      "<project folder>\prebuilt\os\petalinux\<ddr size>" or "<project folder>\prebuilt\os\petalinux\<short name>"


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      This step depends on Xilinx Device/Hardware

      for Zynq-7000 series

      • copy u-boot.elf, u-boot.dtb, system.dtb, image.ub and boot.scr from "<plnx-proj-root>/images/linux" to prebuilt folder

      for ZynqMP

      • copy u-boot.elf, u-boot.dtb, system.dtb, bl31.elf, image.ub and boot.scr from "<plnx-proj-root>/images/linux" to prebuilt folder

      for Microblaze

      • ...


  8. Generate Programming Files with Vitis

    Code Block
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    titlerun on Vivado TCL (Script generates applications and bootable files, which are defined in "test_board\sw_lib\apps_list.csv")
    TE::sw_run_vitis -all
    TE::sw_run_vitis (optional; Start Vitis from Vivado GUI or start with TE Scripts on Vivado TCL)


    Note

    TCL scripts generate also platform project, this must be done manually in case GUI is used. See Vitis


Launch

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Programming

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Note:
  • Programming and Startup procedure


Note

Check Module and Carrier TRMs for proper HW configuration before you try any design.

Reference Design is also available with prebuilt files. It's recommended to use TE prebuilt files for first launch.


Warning

TE0715-0x-30-xx  only: HP IO Banks max power supply voltage is 1.8V.

Xilinx documentation for programming and debugging: Vivado/Vitis/SDSoC-Xilinx Software Programming and Debugging

Get prebuilt boot binaries

  1. Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell
  2. Press 0 and enter to start "Module Selection Guide"
    1. Select assembly version
    2. Validate selection
    3. Select Create and open delivery binary folder

      Info

      Note: Folder "<project folder>\_binaries_<Article Name>" with subfolder "boot_<app name>" for different applications will be generated


QSPI-Boot mode

Optional for Boot.bin on QSPI Flash and image.ub and boot.scr on SD or USB.

  1. Connect JTAG and power on carrier with module
  2. Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"

    Code Block
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    titlerun on Vivado TCL (Script programs BOOT.bin on QSPI flash)
    TE::pr_program_flash -swapp u-boot
    TE::pr_program_flash -swapp hello_te0715 (optional)


    Note

    To program with Vitis/Vivado GUI, use special FSBL (fsbl_flash) on setup


  3. Copy image.ub and boot.scr on SD or USB
    • use files from "<project folder>\_binaries_<Article Name>\boot_linux" from generated binary folder,see: Get prebuilt boot binaries
    • or use prebuilt file location, see "<project folder>\prebuilt\file_location.txt"
  4. Set Boot Mode to QSPI-Boot and insert SD or USB.
    • Depends on Carrier, see carrier TRM.

SD-Boot mode

  1. Copy image.ub, boot.scr and Boot.bin on SD
    • use files from "<project folder>\_binaries_<Article Name>\boot_linux" from generated binary folder,see: Get prebuilt boot binaries
    • or use prebuilt file location, see "<project folder>\prebuilt\file_location.txt"
    • optional: use startup script init.sh for SD
  2. Set Boot Mode to SD-Boot.
    • Depends on Carrier, see carrier TRM.
  3. Insert SD-Card in SD-Slot.

JTAG

Not used on this Example.

Usage

  1. Prepare HW like described on section Programming
  2. Connect UART USB (most cases same as JTAG)
  3. Select SD Card as Boot Mode (or QSPI - depending on step 1)

    Info

    Note: See TRM of the Carrier, which is used.


    Tip

    Starting with Petalinux version 2020.1, the industry standard "Distro-Boot" boot flow for U-Boot was introduced, which significantly expands the possibilities of the boot process and has the primary goal of making booting much more standardised and predictable.
    The boot options described above describe the common boot processes for this hardware; other boot options are possible.
    For more information see Distro Boot with Boot.scr


  4. Power On PCB

    Expand
    titleboot process

    1. Zynq Boot ROM loads FSBL from SD/QSPI into OCM,

    2. FSBL init PS, programs PL using the bitstream and loads U-boot from SD into DDR,

    3. U-boot loads Linux (image.ub) from SD/QSPI/... into DDR


    Page properties
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    This step depends on Xilinx Device/Hardware

    for Zynq-7000 series

    1. Zynq Boot ROM loads FSBL from SD/QSPI into OCM,

    2. FSBL init the PS, programs the PL using the bitstream and loads U-boot from SD/QSPI into DDR,

    3. U-boot loads Linux (image.ub) from SD/QSPI/... into DDR


    for ZynqMP???

    1. ZynqMP Boot ROM loads FSBL from SD/QSPI into OCM,

    2. FSBL init the PS, programs the PL using the bitstream and loads PMU, ATF and U-boot from SD/QSPI into DDR,

    3. U-boot loads Linux (image.ub) from SD/QSPI/... into DDR


    for Microblaze with Linux

    1. FPGA Loads Bitfile from Flash,

    2. MCS Firmware configure SI5338 and starts Microblaze, (only if mcs is available)

    3. SREC Bootloader from Bitfile Firmware loads U-Boot into DDR (This takes a while),

    4. U-boot loads Linux from QSPI Flash into DDR


    for native FPGA

    ...


Linux

  1. Open Serial Console (e.g. putty)
    • Speed: 115200
    • select COM Port

      Info

      Win OS, see device manager, Linux OS see dmesg | grep tty  (UART is *USB1)


  2. Linux Console:

    Info

    Note: Wait until Linux boot finished


  3. You can use Linux shell now.

    Code Block
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    i2cdetect -y -r 0	(check I2C 1 Bus)
    dmesg | grep rtc	(RTC check)
    udhcpc				(ETH0 check)
    lsusb				(USB check)


  4. Option Features
    • Webserver to get access to Zynq
      • insert IP on web browser to start web interface
    • init.sh scripts
      • add init.sh script on SD, content will be load automatically on startup (template included in "<project folder>\misc\SD")

Vivado HW Manager 

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Note:

  • Add picture of HW Manager

  • add notes for the signal either groups or topics, for example:

    Control:

    • add controllable IOs with short notes..

    Monitoring:

    • add short notes for signals which will be monitored only
    • SI5338 CLKs:
      • Set radix from VIO signals to unsigned integer. Note: Frequency Counter is inaccurate and displayed unit is Hz
      • expected CLK Frequency...
Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder).
  • Monitoring:
    • Si5338 CLKs:
      • Set radix from VIO signals to unsigned integer. Note: Frequency Counter is inaccurate and displayed unit is Hz
      • MGT CLK is configured to 125MHz by default, FCLK is not configured by default (optional possible over FSBL → 50MHz on delivered configuration, see FSBL description).
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System Design - Vivado

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Note:

  • Description of Block Design, Constrains... BD Pictures from Export...


Block Design

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PS Interfaces

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Note:

  • optional for Zynq / ZynqMP only

  • add basic PS configuration

Activated interfaces:

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titlePS Interfaces

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TypeNote
DDR---
QSPIMIO
I2C1MIO
UART0MIO
GPIOMIO
ETH, USB RstMIO
SD0MIO
USB0MIO
ETH0MIO
TTC0..1EMIO
SWDTEMIO


Constrains

Basic module constrains

Code Block
languageruby
title_i_bitgen_common.xdc
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property CFGBVS VCCO [current_design]

set_property BITSTREAM.CONFIG.USR_ACCESS TIMESTAMP [current_design]


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title_i_unused_io.xdc
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLNONE [current_design]

Design specific constrain

Code Block
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title_i_io.xdc
set_property PACKAGE_PIN K2 [get_ports {fclk[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports {fclk[0]}]
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets fclk_IBUF[0]]


Code Block
languageruby
title_i_timing.xdc
# for fmeter only
set_false_path -from [get_clocks clk_fpga_0] -to [get_clocks mgt_clk1_clk_p]
set_false_path -from [get_clocks mgt_clk1_clk_p] -to [get_clocks clk_fpga_0]

Software Design - Vitis

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Note:
  • optional chapter separate

  • sections for different apps

For Vitis project creation, follow instructions from:

Vitis

Application

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----------------------------------------------------------

FPGA Example

scu

MCS Firmware to configure SI5338 and Reset System.

srec_spi_bootloader

TE modified 2021.2 SREC

Bootloader to load app or second bootloader from flash into DDR

Descriptions:

  • Modified Files: blconfig.h, bootloader.c
  • Changes:
    • Add some console outputs and changed bootloader read address.
    • Add bugfix for 2018.2 qspi flash

xilisf_v5_11

TE modified 2021.2 xilisf_v5_11

  • Changed default Flash type to 5.


----------------------------------------------------------

Zynq Example:

fsbl

TE modified 2021.2 FSBL

General:

  • Modified Files: main.c, fsbl_hooks.h/.c (search for 'TE Mod' on source code)
  • Add Files: te_fsbl_hooks.h/.c (for hooks and board)

  • General Changes: 
    • Display FSBL Banner and Device ID

Module Specific:

  • Add Files: all TE Files start with te_*
    • READ MAC from EEPROM and make Address accessible by UBOOT (need copy defines on uboot platform-top.h)
    • CPLD access
    • Read CPLD Firmware and SoC Type
    • Configure Marvell PHY

fsbl_flash

TE modified 2021.2 FSBL

General:

  • Modified Files: main.c
  • General Changes:
    • Display FSBL Banner
    • Set FSBL Boot Mode to JTAG
    • Disable Memory initialisation


----------------------------------------------------------

ZynqMP Example:

zynqmp_fsbl

TE modified 2021.2 FSBL

General:

  • Modified Files: xfsbl_main.c, xfsbl_hooks.h/.c, xfsbl_board.h/.c (search for 'TE Mod' on source code)
  • Add Files: te_xfsbl_hooks.h/.c (for hooks and board)
  • General Changes: 
    • Display FSBL Banner and Device Name

Module Specific:

  • Add Files: all TE Files start with te_*
    • Si5338 Configuration
    • ETH+OTG Reset over MIO

zynqmp_fsbl_flash

TE modified 2021.2 FSBL

General:

  • Modified Files: xfsbl_initialisation.c, xfsbl_hw.h, xfsbl_handoff.c, xfsbl_main.c
  • General Changes:
    • Display FSBL Banner
    • Set FSBL Boot Mode to JTAG
    • Disable Memory initialisation


zynqmp_pmufw

Xilinx default PMU firmware.


----------------------------------------------------------

General Example:

hello_te0820

Hello TE0820 is a Xilinx Hello World example as endless loop instead of one console output.

u-boot

U-Boot.elf is generated with PetaLinux. Vitis is used to generate Boot.bin.

Template location: "<project folder>\sw_lib\sw_apps\"

fsbl

TE modified 2021.2 FSBL

General:

  • Modified Files: main.c, fsbl_hooks.h/.c (search for 'TE Mod' on source code)
  • Add Files: te_fsbl_hooks.h/.c (for hooks and board)

  • General Changes: 
    • Display FSBL Banner and Device ID

Module Specific:

  • Add Files: all TE Files start with te_*
    • SI5338 Configuration

fsbl_flash

TE modified 2021.2 FSBL

General:

  • Modified Files: main.c
  • General Changes:
    • Display FSBL Banner
    • Set FSBL Boot Mode to JTAG
    • Disable Memory initialisation

hello_te0715

Hello TE0715 is a Xilinx Hello World example as endless loop instead of one console output.

u-boot

U-Boot.elf is generated with PetaLinux. Vitis is used to generate Boot.bin.

Software Design -  PetaLinux

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Note:
  • optional chapter separate

  • sections for linux

  • Add "No changes." or "Activate: and add List"

For PetaLinux installation and project creation, follow instructions from:

Config

Start with petalinux-config or petalinux-config --get-hw-description

Changes:

  • CONFIG_SUBSYSTEM_ETHERNET_PS7_ETHERNET_0_MAC=""

U-Boot

Start with petalinux-config -c u-boot

Changes:

  • CONFIG_QSPI_BOOT=y
  • CONFIG_SD_BOOT=y
  • CONFIG_ENV_IS_NOWHERE=y
  • CONFIG_ENV_OVERWRITE=y                       (used to overwrite environment parameter)
  • CONFIG_ENV_IS_IN_FAT=y                           (needed to boot from SD card)
  • CONFIG_ENV_IS_IN_SPI_FLASH=y                  (needed to boot from QSPI flash)
  • # CONFIG_ENV_IS_IN_NAND is not set
  • CONFIG_BOOT_SCRIPT_OFFSET=0x1920000   (Calculate the start address of partition 3 "bootscr" in the QSPI flash. To do this, add the sizes of partitions 0, 1 and 2 together)
  • CONFIG_ZYNQ_MAC_IN_EEPROM=y
  • CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET=0xFA
  • CONFIG_SYS_I2C_EEPROM_ADDR=0x50

Device Tree (system-user.dtsi in device-tree and uboot-device-tree)

Code Block
languagejs
/include/ "system-conf.dtsi"
/ {
  chosen {
    xlnx,eeprom = &eeprom;
  };
};
 
/*------------------- default --------------------*/
 
/*------------------ QSPI PHY --------------------*/
&qspi {
    #address-cells = <1>;
    #size-cells = <0>;
    status = "okay";
    flash0: flash@0 {
        compatible = "jedec,spi-nor";
        reg = <0x0>;
        #address-cells = <1>;
        #size-cells = <1>;
    };
};
 
 
 
/*--------------------- ETH PHY ------------------*/
&gem0 {
 
    status = "okay";
        ethernet_phy0: ethernet-phy@0 {
        compatible = "marvell,88e1510";
        device_type = "ethernet-phy";
                reg = <0>;
    };
};
 
 
/*---------------------- USB PHY -----------------*/ 
/{
    usb_phy0: usb_phy@0 {
        compatible = "ulpi-phy";
        //compatible = "usb-nop-xceiv";
        #phy-cells = <0>;
        reg = <0xe0002000 0x1000>;
        view-port = <0x0170>;
        drv-vbus;
    };
};
 
&usb0 {
    dr_mode = "host";
    //dr_mode = "peripheral";
    usb-phy = <&usb_phy0>;
};
 
/*---------------------- I2C ---------------------*/
// i2c PLL: 0x70, i2c eeprom: 0x50
 
&i2c1 {
  rtc@6F {                      // Real Time Clock
       compatible = "isl12022";
       reg = <0x6F>;
   };
  
  eeprom: eeprom@50 {           //MAC EEPROM
    compatible = "atmel,24c08";
    reg = <0x50>;
  };
};

FSBL patch

Must be add manually --> work in progress

Kernel

Start with petalinux-config -c kernel

Changes:

  • CONFIG_RTC_DRV_ISL12022=y

Rootfs

Start with petalinux-config -c rootfs

Changes:

  • CONFIG_i2c-tools=y
  • CONFIG_busybox-httpd=y         (for web server app)
  • CONFIG_usbutils=y
  • CONFIG_util-linux-umount=y      (uses mount/umount function from util-linux instead of busybox)
  • CONFIG_util-linux-mount=y

Applications

See "<project folder>\os\petalinux\project-spec\meta-user\recipes-apps\"

startup

Script App to load init.sh from SD Card if available.

webfwu

Webserver application suitable for Zynq access. Need busybox-httpd


Additional Software

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Note:
  • Add description for other Software, for example SI CLK Builder ...
  • SI5338 and SI5345 also Link to:

SI5338

File location "<project folder>\misc\Si5338\Si5338-*.slabtimeproj"

General documentation how you work with this project will be available on Si5338

Appx. A: Change History and Legal Notices

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Document Change History

To get content of older revision  got to "Change History" of this page and select older document revision number.

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  • Note this list must be only updated, if the document is online on public doc!
  • It's semi automatically, so do following
    • Add new row below first

    • Copy "Page Information Macro (date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf export template

    • Metadata is only used of compatibility of older exports


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DateDocument Revision

Authors

Description

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infoTypeModified date
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infoTypeCurrent version
dateFormatyyyy-MM-dd
prefixv.
typeFlat

Page info
infoTypeModified by
dateFormatyyyy-MM-dd
typeFlat

  • Release 2021.2
2021-12-16v.39Manuela Strücker
  • new Assembly variants
2021-06-16v.38Manuela Strücker
  • changed mount/umount function in PetaLinux
2021-05-31v.37John Hartfiel
  • Design update (bugfix csv file)

2021-05-04

v.36Manuela Strücker
  • Release 2020.2
  • added boot.scr for distro boot
2020-06-10v.33John Hartfiel
  • Release 2019.2
2019-05-09v.32John Hartfiel
  • Release 2018.3
  • FSBL Rework
  • Script rework
  • some optional features
2018-10-01v.31John Hartfiel
  • Release 2018.2
  • Redesign Board Part Files
  • New activate SI5338 example over FSBL
  • small Design changes
  • Update Documentation Style

2019-04-06

v.30John Hartfiel
  • New assembly variant

2018-03-27

v.29John Hartfiel
  • Bugfix Board Part Files
2018-02-13v.28John Hartfiel
  • Release 2017.4
2017-11-10v.22John Hartfiel
  • Design Update with new options
  • Add Si5338 section
  • Update FSBL section
2017-10-19

v.21

John Hartfiel
  • Download Update
2017-10-19v.20John Hartfiel
  • Document style update
2017-10-06v.18John Hartfiel
  • Text correction
  • Update Launch section
  • Supported PCBs
2017-10-02v.14John Hartfiel
  • Document update on Prebuilt section
2017-09-28
v.13
John Hartfiel
  • Initial Release 2017.2
--all

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--


Legal Notices

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