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Online version of this manual and other related documents can be found at https://wiki.trenz-electronic.de/display/PD/Trenz+Electronic+Documentation
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Table of contents

Table of Contents
outlinetrue

Overview

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General Design description
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Key Features

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Excerpt
  • PetaLinux
  • MicroBlaze
  • SREC
  • I2C
  • Flash
  • MIG
  • FMeter
  • SI5338 initialisation with MCS
  • ETH

Revision History

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...

  • No Design changes
  • small constrain changes

...

  • Add SI5338 initialisation with MCS
  • Add Ethernet IP

...

  • Add Wiki Link in Boart Part Files
  • Set Correct Short Link for te0712-02-200-2c

...

  • initial release

Release Notes and Know Issues

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...

Requirements

Software

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Hardware

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Hardware Support
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Basic description of TE Board Part Files is available on TE Board Part Files.

Complete List is available on <design name>/board_files/*_board_files.csv

Design supports following modules:

...

100_2c

...

te0712-02-200-1i3

...

200_1i

...

Design supports following carriers:

...

Additional HW Requirements:

...

Content

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For general structure and of the reference design, see Project Delivery

Design Sources

...

Additional Sources

...

Prebuilt

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<table width="100%">
<tr> <th>File                                 </th> <th>File-Extension</th>  <th>Description                                                                              </th> </tr>
<tr> <td>BIF-File                             </td> <td>*.bif         </td>  <td>File with description to generate Bin-File                                               </td> </tr>
<tr> <td>BIN-File                             </td> <td>*.bin         </td>  <td>Flash Configuration File with Boot-Image (Zynq-FPGAs)                                    </td> </tr>
<tr> <td>BIT-File                             </td> <td>*.bit         </td>  <td>FPGA Configuration File                                                                  </td> </tr>
<tr> <td>DebugProbes-File                     </td> <td>*.ltx         </td>  <td>Definition File for Vivado/Vivado Labtools Debugging Interface                           </td> </tr>
<tr> <td>Debian SD-Image                      </td> <td>*.img         </td>  <td>Debian Image for SD-Card                                                                </td> </tr>
<tr> <td>Diverse Reports                      </td> <td>  ---         </td>  <td>Report files in different formats                                                        </td> </tr>
<tr> <td>Hardware-Platform-Specification-Files</td> <td>*.hdf         </td>  <td>Exported Vivado Hardware Specification for SDK/HSI                                       </td> </tr>
<tr> <td>LabTools Project-File                </td> <td>*.lpr         </td>  <td>Vivado Labtools Project File                                                             </td> </tr>
<tr> <td>MCS-File                             </td> <td>*.mcs         </td>  <td>Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)                  </td> </tr>
<tr> <td>MMI-File                             </td> <td>*.mmi         </td>  <td>File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only) </td> </tr>
<tr> <td>OS-Image                             </td> <td>*.ub          </td>  <td>Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)             </td> </tr>
<tr> <td>Software-Application-File            </td> <td>*.elf         </td>  <td>Software Application for Zynq or MicroBlaze Processor Systems                            </td> </tr>
<tr> <td>SREC-File                            </td> <td>*.srec        </td>  <td>Converted Software Application for MicroBlaze Processor Systems                          </td> </tr>    
</table>
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...

File

...

File-Extension

...

Description

...

MCS-File

...

*.mcs

...

Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)

...

MMI-File

...

*.mmi

...

File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)

...

SREC-File

...

*.srec

...

Converted Software Application for MicroBlaze Processor Systems

Download

Reference Design is only usable with the specified Vivado/SDK/PetaLinux/SDx version. Do never use different Versions of Xilinx Software for the same Project.

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Reference Design is available on:

Design Flow

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Note

Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first lunch.

Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.

See also:Vivado/SDK/SDSoC

The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.

TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/SDK GUI.  For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality

 

  1. _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
    Image Removed
  2. Press 0 and enter for minimum setup
  3. (optional Win OS) Generate Virtual Drive or use short directory  for the reference design (for example x:\<design name>)
  4. Create Project
    1. Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
      Note: Select correct one, see TE Board Part Files
  5. Create HDF and export to prebuilt folder
    1. Run on Vivado TCL: TE::hw_build_design -export_prebuilt
      Note: Script generate design and export files into \prebuilt\hardware\<short dir>. Use GUI is the same, except file export to prebuilt folder
  6. Create Linux (uboot.elf and image.ub) with exported HDF
    1. HDF is exported to "prebuilt\hardware\<short name>"
      Note: HW Export from Vivado GUI create another path as default workspace.
    2. Create Linux images on VM, see PetaLinux KICKstart
      1. Use TE Template from /os/petalinux
        Note: run init_config.sh before you start petalinux config. This will set correct temporary path variable.
        Important Note: Select correct Flash partition offset on petalinux-config: Subsystem Auto HW Settings → Flash Settings,  FPGA+Boot+bootenv=0x900000 (increase automatically generate Boot partition)
  7. Add Linux files (uboot.elf and image.ub) to prebuilt folder
    1. "prebuilt\os\petalinux\default" or "prebuilt\os\petalinux\<short name>"
      Notes: Scripts select "prebuilt\os\petalinux\<short name>", if exist, otherwise "prebuilt\os\petalinux\default"
  8. Generate UBoot SREC:
    1. Create SDK Project with TE Scripts on Vivado TCL: TE::sw_run_sdk
    2. Create "uboot-dummy" application
      Note: Use Hello World Example
    3. Copy u.boot.elf into "\workspace\sdk\uboot-dummy\Debug"
    4. Open "uboot-dummy" properties → C/C++ Build → Settings and go into Build Steps Tap.
    5. Add to Post-build steps: mb-objcopy -O srec u-boot.elf u-boot.srec
    6. Press Apply or regenerate project
      Note: srec is generated on "\workspace\sdk\uboot-dummy\Debug\u-boot.srec"
  9. Generate MCS Firmware (optional):
    1. Create SDK Project with TE Scripts on Vivado TCL: TE::sw_run_sdk
    2. Create "SCU" application
      Note: Select MCS Microblaze and SCU Application
    3. Select Release Built
    4. Regenerate App
  10. Generate Programming Files with HSI/SDK
    1. Run on Vivado TCL: TE::sw_run_hsi
      Note: Scripts generate applications and bootable files, which are defined in "sw_lib\apps_list.csv"
    2. (alternative) Start SDK with Vivado GUI or start with TE Scripts on Vivado TCL: TE::sw_run_sdk
      Note: See SDK Projects
  11. Copy "\prebuilt\software\<short name>\srec_spi_bootloader.elf" into  "\firmware\microblaze_0\"
  12. (optional) Copy "\\workspace\sdk\scu\Release\scu.elf" into  "\firmware\microblaze_mcs_0\"
  13. Regenerate Vivado Project or Update Bitfile only with "srec_spi_bootloader.elf" and "scu.elf"

Launch

Programming

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Note

Check Module and Carrier TRMs for proper HW configuration before you try any design.

Xilinx documentation for programming and debugging: Vivado/SDK/SDSoC-Xilinx Software Programming and Debugging

QSPI

  1. Connect JTAG and power on PCB
  2. (if not done) Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd" or open with "vivado_open_project_guimode.cmd", if generated.
  3. Type on Vivado Console: TE::pr_program_flash_mcsfile -swapp u-boot
    Note: Alternative use SDK or setup Flash on Vivado manually
  4. Reboot (if not done automatically)

SD

Not used on this Example.

JTAG

Not used on this Example.

Usage

  1. Prepare HW like described on section Programming
  2. Connect UART USB (most cases same as JTAG)
  3. Power on PCB
    Note: FPGA Loads Bitfile from Flash,MCS Firmware configure SI5338 and starts Microblaze, SREC Bootloader from Bitfile Firmware loads U-Boot into DDR (This takes a while), U-boot loads Linux from QSPI Flash into DDR

Boot process takes a while, please wait.

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Linux

Note: Linux boot process is slower on Microblaze.

  1. Open Serial Console (e.g. putty)
    1. Speed: 9600
    2. COM Port: Win OS, see device manager, Linux OS see  dmesg |grep tty  (UART is *USB1)
  2. Linux Console:
    Note: Wait until Linux boot finished For Linux Login use:
    1. User Name: root
    2. Password: root
  3. You can use Linux shell now.
    1. ETH0 works with udhcpc

Vivado HW Manager: 

  1. Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder).
    1. Set radix from VIO signals (MGT REF, MIG_OUT, CLK1B, CLK0) to unsigned integer.
      Note: Frequency Counter is inaccurate and displayed unit is Hz
    2. MGT REF~125MHz, MIG_50MHZ~50MHz., CLK1B ~50MHz, CLK0~100MHz
    3. Additional Infos: System reset from MCS and GIO outputs

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System Design - Vivado

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Block Design

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Constrains

Basic module constrains

Code Block
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title_i_bitgen_common.xdc
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property BITSTREAM.CONFIG.CONFIGRATE 66 [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property CFGBVS VCCO [current_design]
set_property CONFIG_MODE SPIx4 [current_design]
set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design]
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
set_property BITSTREAM.CONFIG.M1PIN PULLNONE [current_design]
set_property BITSTREAM.CONFIG.M2PIN PULLNONE [current_design]
set_property BITSTREAM.CONFIG.M0PIN PULLNONE [current_design]

set_property BITSTREAM.CONFIG.USR_ACCESS TIMESTAMP [current_design]
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title_i_bitgen.xdc
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLDOWN [current_design]

Design specific constrain

Code Block
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title_i_reset.xdc
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set_property PULLDOWN true [get_ports reset]
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title_i_io.xdc
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#I2C
set_property PACKAGE_PIN W21 [get_ports PLL_I2C_scl_io]
set_property IOSTANDARD LVCMOS33 [get_ports PLL_I2C_scl_io]
set_property PACKAGE_PIN T20 [get_ports PLL_I2C_sda_io]
set_property IOSTANDARD LVCMOS33 [get_ports PLL_I2C_sda_io]

#Reset
set_property PACKAGE_PIN T3 [get_ports reset]
set_property IOSTANDARD LVCMOS15 [get_ports reset]
#CLKS
set_property PACKAGE_PIN R4 [get_ports {CLK1B[0]}]
set_property IOSTANDARD SSTL15 [get_ports {CLK1B[0]}]
set_property PACKAGE_PIN K4 [get_ports {CLK0_clk_p[0]}]
set_property IOSTANDARD DIFF_SSTL15 [get_ports {CLK0_clk_p[0]}]

#ETH PHY
set_property PACKAGE_PIN N17 [get_ports phy_rst_n]
set_property IOSTANDARD LVCMOS33 [get_ports phy_rst_n]
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title_i_timing.xdc
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create_clock -period 8.000 -name mgt_clk0_clk_p -waveform {0.000 4.000} [get_ports mgt_clk0_clk_p]


create_clock -period 10.000 -name {CLK0_clk_p[0]} -waveform {0.000 5.000} [get_ports {CLK0_clk_p[0]}]
create_clock -period 20.000 -name {CLK1B[0]} -waveform {0.000 10.000} [get_ports {CLK1B[0]}]
create_clock -period 15.152 -name msys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/LOGIC_FOR_MD_12_GEN.SCK_MISO_STARTUP_USED.QSPI_STARTUP_BLOCK_I/cfgmclk -waveform {0.000 7.576} [get_pins msys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/LOGIC_FOR_MD_12_GEN.SCK_MISO_STARTUP_USED.QSPI_STARTUP_BLOCK_I/STARTUP_7SERIES_GEN.STARTUP2_7SERIES_inst/CFGMCLK]


set_false_path -from [get_clocks {CLK0_clk_p[0]}] -to [get_clocks clk_pll_i]
set_false_path -from [get_clocks mgt_clk0_clk_p] -to [get_clocks clk_pll_i]
set_false_path -from [get_clocks msys_i/axi_quad_spi_0/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/LOGIC_FOR_MD_12_GEN.SCK_MISO_STARTUP_USED.QSPI_STARTUP_BLOCK_I/cfgmclk] -to [get_clocks clk_pll_i]



set_false_path -from [get_clocks -of_objects [get_pins msys_i/mig_7series_0/u_msys_mig_7series_0_0_mig/u_ddr3_infrastructure/gen_ui_extra_clocks.mmcm_i/CLKFBOUT]] -to [get_clocks mgt_clk0_clk_p]

set_false_path -from [get_pins msys_i/labtools_fmeter_0/U0/COUNTER_REFCLK_inst/bl.DSP48E_2/CLK] -to [get_pins {msys_i/vio_0/inst/PROBE_IN_INST/probe_in_reg_reg[*]/D}]
set_false_path -from [get_pins {msys_i/labtools_fmeter_0/U0/F_reg[*]/C}] -to [get_pins {msys_i/vio_0/inst/PROBE_IN_INST/probe_in_reg_reg[*]/D}]
set_false_path -from [get_pins {msys_i/labtools_fmeter_0/U0/FMETER_gen[*].COUNTER_F_inst/bl.DSP48E_2/CLK}] -to [get_pins {msys_i/labtools_fmeter_0/U0/F_reg[*]/D}]
set_false_path -from [get_pins msys_i/labtools_fmeter_0/U0/toggle_reg/C] -to [get_pins {msys_i/labtools_fmeter_0/U0/FMETER_gen[*].COUNTER_F_inst/bl.DSP48E_2/CECARRYIN}]
set_false_path -from [get_pins msys_i/labtools_fmeter_0/U0/toggle_reg/C] -to [get_pins {msys_i/labtools_fmeter_0/U0/FMETER_gen[*].COUNTER_F_inst/bl.DSP48E_2/CEP}]
set_false_path -from [get_pins msys_i/labtools_fmeter_0/U0/toggle_reg/C] -to [get_pins {msys_i/labtools_fmeter_0/U0/FMETER_gen[*].COUNTER_F_inst/bl.DSP48E_2/CEA2}]
set_false_path -from [get_pins msys_i/labtools_fmeter_0/U0/toggle_reg/C] -to [get_pins {msys_i/labtools_fmeter_0/U0/FMETER_gen[*].COUNTER_F_inst/bl.DSP48E_2/CEB2}]
set_false_path -from [get_pins msys_i/labtools_fmeter_0/U0/toggle_reg/C] -to [get_pins {msys_i/labtools_fmeter_0/U0/FMETER_gen[*].COUNTER_F_inst/bl.DSP48E_2/CEALUMODE}]
set_false_path -from [get_pins msys_i/labtools_fmeter_0/U0/toggle_reg/C] -to [get_pins {msys_i/labtools_fmeter_0/U0/FMETER_gen[*].COUNTER_F_inst/bl.DSP48E_2/CECTRL}]
set_false_path -from [get_pins msys_i/labtools_fmeter_0/U0/toggle_reg/C] -to [get_pins {msys_i/labtools_fmeter_0/U0/FMETER_gen[*].COUNTER_F_inst/bl.DSP48E_2/CEC}]
set_false_path -from [get_pins msys_i/labtools_fmeter_0/U0/toggle_reg_replica/C] -to [get_pins {msys_i/labtools_fmeter_0/U0/FMETER_gen[*].COUNTER_F_inst/bl.DSP48E_2/RSTC}]
set_false_path -from [get_pins msys_i/labtools_fmeter_0/U0/toggle_reg_replica/C] -to [get_pins {msys_i/labtools_fmeter_0/U0/FMETER_gen[*].COUNTER_F_inst/bl.DSP48E_2/RSTB}]
set_false_path -from [get_pins msys_i/labtools_fmeter_0/U0/toggle_reg_replica/C] -to [get_pins {msys_i/labtools_fmeter_0/U0/FMETER_gen[*].COUNTER_F_inst/bl.DSP48E_2/RSTA}]
set_false_path -from [get_pins msys_i/labtools_fmeter_0/U0/toggle_reg_replica/C] -to [get_pins {msys_i/labtools_fmeter_0/U0/FMETER_gen[*].COUNTER_F_inst/bl.DSP48E_2/RSTP}]
set_false_path -from [get_pins msys_i/labtools_fmeter_0/U0/toggle_reg_replica/C] -to [get_pins {msys_i/labtools_fmeter_0/U0/FMETER_gen[*].COUNTER_F_inst/bl.DSP48E_2/RSTINMODE}]
set_false_path -from [get_pins msys_i/labtools_fmeter_0/U0/toggle_reg_replica/C] -to [get_pins {msys_i/labtools_fmeter_0/U0/FMETER_gen[*].COUNTER_F_inst/bl.DSP48E_2/RSTALUMODE}]
set_false_path -from [get_pins msys_i/labtools_fmeter_0/U0/toggle_reg_replica/C] -to [get_pins {msys_i/labtools_fmeter_0/U0/FMETER_gen[*].COUNTER_F_inst/bl.DSP48E_2/RSTCTRL}]
set_false_path -from [get_pins msys_i/labtools_fmeter_0/U0/toggle_reg_replica/C] -to [get_pins {msys_i/labtools_fmeter_0/U0/FMETER_gen[*].COUNTER_F_inst/bl.DSP48E_2/RSTALLCARRYIN}]

Software Design - SDK/HSI

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For SDK project creation, follow instructions from:

SDK Projects

Application

SCU

MCS Firmware to configure SI5338 and Reset System.

Template location: \sw_lib\sw_apps\scu

SREC SPI BootLoader

Add some Console outputs and changed Bootloader Read Address.

Template location: \sw_lib\sw_apps\srec_spi_bootloader

xilisf_v5_9

Changed default Flash Typ to 5.

Template location: \sw_lib\sw_services

U-Boot

U-Boot.elf is generated with PetaLinux. SDK/HSI is used to generate u-boot.srec. Vivado to generate *.mcs

Software Design -  PetaLinux

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Description currently not available.

Config

  • Set kernel flash Address to 0x900000 and Kernel size to 0xA00000:
    (--> Subsystem Auto Hardware Settings --> Flash Settings)
    • SUBSYSTEM_FLASH_AXI_QUAD_SPI_0_BANKLESS_PART0_SIZE = 0x400000
    • SUBSYSTEM_FLASH_AXI_QUAD_SPI_0_BANKLESS_PART1_SIZE = 0x4E0000
    • SUBSYSTEM_FLASH_AXI_QUAD_SPI_0_BANKLESS_PART2_SIZE =   0x20000
    • SUBSYSTEM_FLASH_AXI_QUAD_SPI_0_BANKLESS_PART3_SIZE = 0xA00000

U-Boot

Code Block
languagejs

#include <configs/platform-auto.h>


#undef CONFIG_PHY_XILINX
#undef XILINX_EMACLITE_BASEADDR    0x40E00000
#undef CONFIG_MII
#undef CONFIG_PHY_GIGE
#undef CONFIG_PHY_MARVELL
#undef CONFIG_PHY_NATSEMI
#undef CONFIG_NET_MULTI
#undef CONFIG_BOOTP_MAY_FAIL
#undef CONFIG_NETCONSOLE    1
#undef CONFIG_SERVERIP    192.168.150.117
#undef CONFIG_IPADDR


/* PREBOOT */
#define CONFIG_PREBOOT    "echo U-BOOT for petalinux;setenv preboot; echo; "



Device Tree

Code Block
languagejs
/include/ "system-conf.dtsi"
/ {
};

/* ETH PHY */
&axi_ethernetlite_0 {
    phy-handle = <&phy0>;
    mdio {
        #address-cells = <1>;
        #size-cells = <0>;
        phy0: phy@0 {
            device_type = "ethernet-phy";
            reg = <1>;
        };
    };
};


Kernel

No changes.

Rootfs

No changes.

Applications

No changes.

Additional Software

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SI5338

Download  ClockBuilder Desktop for SI5338

  1. Install and start ClockBuilder
  2. Select SI5338
  3. Options → Open register map file
    Note: File location <design name>/misc/Si5338/RegisterMap.txt
  4. Modify settings
  5. Options → save C code header files
  6. Replace Header files from FSBL template with generated file

Appx. A: Change History and Legal Notices

Document Change History

To get content of older revision  got to "Change History"  of this page and select older document revision number.

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...

  • Know Issue for PCB REV01 only


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Design Name is always "TE Series Name" + Design name, for example "TE0720 Test Board"


Date

Version

Changes

Author

2021-06-01

3.1.7

  • carrier reference note

jh

2021-05-04

3.1.6

  • removed zynq_ from zynq_fsbl

ma

2021-04-28

3.1.5

  • added macro "Scroll ignore" for suppression of horizontal dividing lines during .pdf-export

  • minor typos, formatting

ma

2021-04-27

3.1.4

  • Version History

    • changed from list to table

  • Design flow

    • removed step 5 from Design flow

    • changed link from TE Board Part Files to Vivado Board Part Flow

    • changed cmd shell from picture to codeblock

    • added hidden template for "Copy PetaLinux build image files", depending from hardware

    • added hidden template for "Power on PCB", depending from hardware

  • Usage update of boot process

  • Requirements - Hardware

    • added "*used as reference" for hardware requirements

  • all

    • placed a horizontal separation line under each chapter heading

    • changed title-alignment for tables from left to center

  • all tables

    • added "<project folder>\board_files" in Vivado design sources

ma


3.1.3

  • Design Flow

    • formatting

  • Launch

    • formatting

ma


3.1.2

  • minor typing corrections

  • replaced SDK by Vitis

  • changed from / to \ for windows paths

  • replaced <design name> by <project folder>

  • added "" for path names

  • added boot.src description

  • added USB for programming

ma


3.1.1

  • swapped order from prebuilt files

  • minor typing corrections

  • removed Win OS path length from Design flow, added as caution in Design flow

ma


3.1

  • Fix problem with pdf export and side scroll bar

  • update 19.2 to 20.2

  • add prebuilt content option



3.0

  • add fix table of content

  • add table size as macro

  • removed page initial creator



Custom_table_size_100

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Important General Note:

  • Export PDF to download, if vivado revision is changed!

  • Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro

    • Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)

      • Figure template (note: inner scroll ignore/only only with drawIO object):

        Scroll Title
        anchorFigure_xyz
        titleText


        Scroll Ignore

        Create DrawIO object here: Attention if you copy from other page, use


        Scroll Only

        image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed



      • Table template:

        • Layout macro can be use for landscape of large tables

        • Set column width manually (can be used for small tables to fit over whole page) or leave empty (automatically)


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        Example

        Comment

        1

        2



  • ...

Overview

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Notes :

Microblaze Design with linux example.

Refer to http://trenz.org/te0712-info for the current online version of this manual and other available documentation.

For directly getting started with the prebuilt files jump to the section Launch.

Key Features

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Notes :

  • Add basic key futures, which can be tested with the design


Excerpt
  • Vitis/Vivado 2021.2

  • PetaLinux

  • MicroBlaze

  • SPI ELF Bootloader
  • I2C

  • Flash

  • MIG

  • FMeter

  • SI5338 initialisation with MCS

  • ETH

  • EEPROM MAC

Revision History

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  • add every update file on the download

  • add design changes on description


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Date

Vivado

Project Built

Authors

Description

2022-02-162021.2TE0712-test_board_noprebuilt-vivado_2021.2-build_11_20220216064240.zip
TE0712-test_board-vivado_2021.2-build_11_20220216064240.zip
Waldemar Hanemann
  • new spi bootloader by Henrik Brix Andersen
  • adjusted offsets
2022-01-182021.2

TE0712-test_board_noprebuilt-vivado_2021.2-build_8_20220118131243.zip

TE0712-test_board-vivado_2021.2-build_8_20220118131243.zip

Waldemar Hanemann
  • MB_MCS elf-File bugfix
  • eeprom Skript bugfix
2022-01-112021.2

TE0712-test_board_noprebuilt-vivado_2021.2-build_7_20220111091553.zip

TE0712-test_board-vivado_2021.2-build_7_20220111091553.zip

Waldemar Hanemann
  • 2021.2 update
  • added eeprom interface for MAC address read-out
  • added boot script
2021-06-282020.2

TE0712-test_board_noprebuilt-vivado_2020.2-build_5_20210628072407.zip

TE0712-test_board-vivado_2020.2-build_5_20210628072421.zip

Manuela Strücker
  • 2020.2 update
  • document style update
  • update TE Board Part List

2020-03-25

2019.2

TE0712-test_board_noprebuilt-vivado_2019.2-build_8_20200325074937.zip

TE0712-test_board-vivado_2019.2-build_8_20200325074915.zip

John Hartfiel

  • Script update

2020-01-22

2019.2

TE0712-test_board_noprebuilt-vivado_2019.2-build_3_20200122155446.zip

TE0712-test_board-vivado_2019.2-build_3_20200122155355.zip

John Hartfiel

  • update for linux user

  • new script features

2020-01-08

2019.2

TE0712-test_board_noprebuilt-vivado_2019.2-build_2_20200108161124.zip

TE0712-test_board-vivado_2019.2-build_2_20200108155510.zip

John Hartfiel

  • 2019.2 update

  • Vitis support

2019-04-18

2018.3

TE0712-test_board_noprebuilt-vivado_2018.3-build_05_20190418082456.zip

TE0712-test_board-vivado_2018.3-build_05_20190418082240.zip

John Hartfiel

  • MCU depends on EOS now

2019-02-22

2018.3

TE0712-test_board_noprebuilt-vivado_2018.3-build_01_20190222073819.zip

TE0712-test_board-vivado_2018.3-build_01_20190222073754.zip

John Hartfiel

  • TE Script update

  • linux changes

  • SCU rework

  • SI5338 CLKBuilder Pro Project

2018-09-05

2018.2

te0712-test_board-vivado_2018.2-build_03_20180906071356.zip

te0712-test_board_noprebuilt-vivado_2018.2-build_03_20180906071434.zip

John Hartfiel

  • change block design: qspi clks, clock wizard(REV01 only)

  • change timing constrains

  • add hello_te0712 application

  • new SREC bootloader version

  • change linux device tree

2018-05-25

2017.4

te0712-test_board-vivado_2017.4-build_10_20180525155402.zip

te0712-test_board_noprebuilt-vivado_2017.4-build_10_20180525155555.zip

John Hartfiel

  • solved eth issue for REV01

  • changed design + second design for REV01

2018-04-12

2017.4

te0712-test_board-vivado_2017.4-build_07_20180412081225.zip

te0712-test_board_noprebuilt-vivado_2017.4-build_07_20180412081253.zip

John Hartfiel

  • bugfix constrain file - ETH REFCLK, timing

2018-03-28

2017.4

te0712-test_board-vivado_2017.4-build_07_20180328145151.zip

te0712-test_board_noprebuilt-vivado_2017.4-build_07_20180328145135.zip

John Hartfiel

  • new assembly variant

2018-01-08

2017.4

te0712-test_board-vivado_2017.4-build_02_20180108155712.zip

te0712-test_board_noprebuilt-vivado_2017.4-build_02_20180108155735.zip

John Hartfiel

  • no design changes

  • small constraint changes

2017-12-15

2017.2

te0712-test_board-vivado_2017.2-build_07_20171215172447.zip

te0712-test_board_noprebuilt-vivado_2017.2-build_07_20171215172514.zip

John Hartfiel

  • add SI5338 initialisation with MCS

  • add Ethernet IP

2017-11-07

2017.2

te0712-test_board-vivado_2017.2-build_05_20171107172917.zip

te0712-test_board_noprebuilt-vivado_2017.2-build_05_20171107172939.zip

John Hartfiel

  • add wiki link in Boart Part Files

  • set correct short link for te0712-02-200-2c

2017-10-05

2017.2

te0712-test_board-vivado_2017.2-build_03_20171005082148.zip

te0712-test_board_noprebuilt-vivado_2017.2-build_03_20171005082225.zip

John Hartfiel

  • initial release


Release Notes and Know Issues

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  • add known Design issues and general notes for the current revision

  • do not delete known issue, add fixed version time stamp if  issue fixed


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Issues

Description

Workaround

To be fixed version

For PCB REV01 only:  prebuilt does not boot

There is a Pullup missing on REV01 I2C SCL, so SI5338 configuration over MCS fails

Remove MCS

solved with 20180528 update

For PCB REV01 only: CLK1B is not available on

additional clk is not connected on PCB

use other internal generated CLK, maybe more effort is needed to get ETH running

solved with 20180528 update


Requirements

Software

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  • list of software which was used to generate the design


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SoftwareVersionNote
Vitis2021.2needed, Vivado is included into Vitis installation
PetaLinux2021.2needed
SI ClockBuilder Pro---optional



Hardware

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Notes :

  • list of hardware which was used to generate the design
  • mark the module and carrier board, which was used tested with an *
Basic description of TE Board Part Files is available on TE Board Part Files.

Complete List is available on "<project folder>\board_files\*_board_files.csv"

Design supports following modules:

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Module Model

Board Part Short Name

PCB Revision Support

DDR

QSPI Flash

EMMC

Others

Notes

TE0712-01-100-1I01_100_1i_1gbREV011GB32MBNANANA
TE0712-01-100-2C01_100_2c_1gbREV011GB32MBNANANA
TE0712-01-100-2C301_100_2c_1gbREV011GB32MBNA2.5 mm Samtec connectorsNA
TE0712-01-200-1I01_200_1i_1gbREV011GB32MBNANANA
TE0712-01-200-2C01_200_2c_1gbREV011GB32MBNANANA
TE0712-01-200-2C301_200_2c_1gbREV011GB32MBNA2.5 mm Samtec connectorsNA
TE0712-02-100-1I100_1i_1gbREV021GB32MBNANANA
TE0712-02-100-2C100_2c_1gbREV021GB32MBNANANA
TE0712-02-100-2C3100_2c_1gbREV021GB32MBNA2.5 mm Samtec connectorsNA
TE0712-02-100-2CA100_2ca_1gbREV021GB32MBNANAMicron QSPI Flash
TE0712-02-200-1I200_1i_1gbREV021GB32MBNANANA
TE0712-02-200-1I3200_1i_1gbREV021GB32MBNA2.5 mm Samtec connectorsNA
TE0712-02-200-2C200_2c_1gbREV021GB32MBNANANA
TE0712-02-200-2C3200_2c_1gbREV021GB32MBNA2.5 mm Samtec connectorsNA
TE0712-02-200-2I200_2i_1gbREV021GB32MBNANANA
TE0712-02-35-2I*35_2i_1gbREV021GB32MBNANANA
TE0712-02-42I36-A35_2i_1gbREV021GB32MBNANANA
TE0712-02-71I06-M100_1i_1gbREV020GB32MBNANAWithout DDR
TE0712-02-71I36-A100_1i_1gbREV021GB32MBNANANA
TE0712-02-72C03-M100_2ca_1gbREV020GB32MBNANAWithout DDR
TE0712-02-72C06-M100_2c_1gbREV020GB32MBNANAWithout DDR
TE0712-02-72C36-A100_2c_1gbREV021GB32MBNANANA
TE0712-02-72C36-C100_2c_1gbREV021GB32MBNANANA
TE0712-02-72C36-L100_2c_1gbREV021GB32MBNA2.5 mm Samtec connectorsNA
TE0712-02-81I36-A200_1i_1gbREV021GB32MBNANANA
TE0712-02-81I36-AC200_1i_1gbREV021GB32MBNANANA
TE0712-02-81I36-L200_1i_1gbREV021GB32MBNA2.5 mm Samtec connectorsNA
TE0712-02-81I36-X200_1i_1gbREV021GB32MBNA2.5 mm Samtec connectorsNA
TE0712-02-82C11-P200_2c_1gbREV021GB32MBNANANA
TE0712-02-82C36-A200_2c_1gbREV021GB32MBNANANA
TE0712-02-82C36-AW200_2c_1gbREV021GB32MBNANANA
TE0712-02-82C36-L200_2c_1gbREV021GB32MBNA2.5 mm Samtec connectorsNA
TE0712-02-82C36-P200_2c_1gbREV021GB32MBNANANA
TE0712-02-82I36-A200_2i_1gbREV021GB32MBNANANA

*used as reference

Design supports following carriers:

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Carrier Model

Notes

TE0701


TE0703*


TE0705


TE0706


TEBA0841


*used as reference


Additional HW Requirements:

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Additional Hardware

Notes

USB Cable for JTAG/UART

Check Carrier Board and Programmer for correct type

XMOD Programmer

Carrier Board dependent, only if carrier has no own FTDI



Content

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  • content of the zip file

For general structure and usage of the reference design, see Project Delivery - Xilinx devices

Design Sources

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TypeLocationNotes
Vivado<project folder>\block_design
<project folder>\constraints
<project folder>\ip_lib
<project folder>\board_files
Vivado Project will be generated by TE Scripts
Vitis<project folder>\sw_libAdditional Software Template for Vitis and apps_list.csv with settings automatically for Vitis app generation
PetaLinux<project folder>\os\petalinuxPetaLinux template with current configuration



Additional Sources

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Type

Location

Notes

SI5338

<project folder>/misc/Si5338

SI5338 Project with current PLL Configuration


Prebuilt

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  • prebuilt files
  • Template Table:

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      File

      File-Extension

      Description

      BIF-File*.bifFile with description to generate Bin-File
      BIN-File*.binFlash Configuration File with Boot-Image (Zynq-FPGAs)
      BIT-File*.bitFPGA (PL Part) Configuration File
      Boot Script*.scr

      Distro Boot file

      DebugProbes-File*.ltxDefinition File for Vivado/Vivado Labtools Debugging Interface

      Debian SD-Image

      *.img

      Debian Image for SD-Card

      Diverse Reports---Report files in different formats
      Hardware-Platform-Description-File*.xsaExported Vivado hardware description file for Vitis and PetaLinux
      LabTools Project-File*.lprVivado Labtools Project File

      MCS-File

      *.mcs

      Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)

      MMI-File

      *.mmi

      File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)

      OS-Image*.ubImage with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)
      Software-Application-File*.elfSoftware Application for Zynq or MicroBlaze Processor Systems

      SREC-File

      *.srec

      Converted Software Application for MicroBlaze Processor Systems




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File

File-Extension

Description

BIT-File

*.bit

FPGA (PL Part) Configuration File

Boot Script*.scr

Distro Boot file

DebugProbes-File

*.ltx

Definition File for Vivado/Vivado Labtools Debugging Interface

Diverse Reports

---

Report files in different formats

Hardware-Platform-Description-File

*.xsa

Exported Vivado hardware description file for Vitis and PetaLinux

LabTools Project-File

*.lpr

Vivado Labtools Project File

MCS-File

*.mcs

Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)

MMI-File

*.mmi

File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)

OS-Image

*.ub

Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)

Software-Application-File

*.elf

Software Application for Zynq or MicroBlaze Processor Systems

SREC-File

*.srec

Converted Software Application for MicroBlaze Processor Systems


Download

Reference Design is only usable with the specified Vivado/Vitis/PetaLinux version. Do never use different Versions of Xilinx Software for the same Project.

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Reference Design is available on:

Design Flow

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Notes :

  • Basic Design Steps

  • Add/ Remove project specific description


Note

Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first launch.

Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.

See also: Xilinx Development Tools#XilinxSoftware-BasicUserGuides

The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.

TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/Vitis GUI. For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality

Note

Caution! Win OS has a 260 character limit for path lengths which can affect the Vivado tools. To avoid this issue, use Virtual Drive or the shortest possible names and directory locations for the reference design (for example "x:\<project folder>")

  1. Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:

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    title_create_win_setup.cmd/_create_linux_setup.sh
    ------------------------Set design paths----------------------------
    -- Run Design with: _create_win_setup
    -- Use Design Path: <absolute project path>
    --------------------------------------------------------------------
    -------------------------TE Reference Design---------------------------
    --------------------------------------------------------------------
    -- (0)  Module selection guide, project creation...prebuilt export...
    -- (1)  Create minimum setup of CMD-Files and exit Batch
    -- (2)  Create maximum setup of CMD-Files and exit Batch
    -- (3)  (internal only) Dev
    -- (4)  (internal only) Prod
    -- (c)  Go to CMD-File Generation (Manual setup)
    -- (d)  Go to Documentation (Web Documentation)
    -- (g)  Install Board Files from Xilinx Board Store (beta)
    -- (a)  Start design with unsupported Vivado Version (beta)
    -- (x)  Exit Batch (nothing is done!)
    ----
    Select (ex.:'0' for module selection guide):


  2. Press 0 and enter to start "Module Selection Guide"

  3. (optional Win OS) Generate Virtual Drive or use short directory  for the reference design (for example x:\<design name>)
  4. Createproject and follow instructions of the product selection guide, settings file will be configured automatically during this process.
    • optional for manual changes: Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"

      Note

      Note: Select correct one, see also Vivado Board Part Flow


  5. Create hardware description file (.xsa file) for PetaLinux project and export to prebuilt folder

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    TE::hw_build_design -export_prebuilt


    Info

    Using Vivado GUI is the same, except file export to prebuilt folder.


  6. Create and configure your PetaLinux project with exported .xsa-file, see PetaLinux KICKstart
    • use TE Template from "<project folder>\os\petalinux"
    • use exported .xsa file from "<project folder>\prebuilt\hardware\<short name>" . Note: HW Export from Vivado GUI creates another path as default workspace.

    • The build images are located in the "<plnx-proj-root>/images/linux" directory

      Info

      Important Note: Select correct Flash partition offset on petalinux-config: Subsystem Auto HW Settings → Flash Settings,  FPGA+Boot+bootenv=0x900000 (increase automatically generate Boot partition), increase image size to A:, see Config



  7. Configure the boot.scr file as needed, see Distro Boot with Boot.scr. Kernel flash address and kernel size are set here.
  8. Copy PetaLinux build image files to prebuilt folder
    • copy u-boot.elf, image.ub and boot.scr from "<plnx-proj-root>/images/linux" to prebuilt folder

      Info

      "<project folder>\prebuilt\os\petalinux\<ddr size>" or "<project folder>\prebuilt\os\petalinux\<short name>"


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      This step depends on Xilinx Device/Hardware

      for Zynq-7000 series

      • copy u-boot.elf, image.ub and boot.scr from "<plnx-proj-root>/images/linux" to prebuilt folder

      for ZynqMP

      • copy u-boot.elf, bl31.elf, image.ub and boot.scr from "<plnx-proj-root>/images/linux" to prebuilt folder

      for ...

      • ...


  9. Generate Programming Files with Vitis

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    TE::sw_run_vitis -all
    TE::sw_run_vitis (optional; Start Vitis from Vivado GUI or start with TE Scripts on Vivado TCL)


    Note

    TCL scripts generate also platform project, this must be done manually in case GUI is used. See Vitis


  10. (Optional) BlockRam Firmware Update
    1. Copy "<project folder>\prebuilt\software\<short name>\spi_bootloader.elf" into  "<project folder>\firmware\microblaze_0\"

    2. Copy "<project folder>\workspace\sdk\scu_te0712\Release\scu_te0712.elf" into "\firmware\microblaze_mcs_0\"

    3. Regenerate Vivado Project or Update Bitfile only with "spi_bootloader.elf" and "scu_te0712.elf"

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      TE::sw_run_vitis -all


Launch

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Programming

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Note:

  • Programming and Startup procedure


Note

Check Module and Carrier TRMs for proper HW configuration before you try any design.

Reference Design is also available with prebuilt files. It's recommended to use TE prebuilt files for first launch.

Xilinx documentation for programming and debugging: Vivado/Vitis/SDSoC-Xilinx Software Programming and Debugging

Get prebuilt boot binaries

  1. Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell
  2. Press 0 and enter to start "Module Selection Guide"
    1. Select assembly version
    2. Validate selection
    3. Select create and open delivery binary folder

      Info

      Note: Folder "<project folder>\_binaries_<Article Name>" with subfolder "boot_<app name>" for different applications will be generated


QSPI-Boot mode

Option for u-boot.mcs on QSPI Flash.
(u-boot.mcs contains all files necessary to boot up linux)

  1. Connect the USB cable(JTAG) and power supply on carrier with module

  2. Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd".
    Enter the following TCL-Command into the TCL-Console inside Vivado to program the QSPI Flash.

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    titlerun on Vivado TCL (Script programs u-boot.mcs onto QSPI flash)
    TE::pr_program_flash -swapp u-boot
    


  3. Reboot (if not done automatically)

SD-Boot mode

Not used on this Example.

JTAG

Not used on this Example.

Usage

  1. Prepare HW like described on section Programming

  2. Connect UART USB (most cases same as JTAG)

  3. Select QSPI as Boot Mode

    Info

    Note: See TRM of the Carrier, which is used.


  4. Power On PCB and push the reset button if present on carrier.

    Expand
    titleboot process

    1. FPGA Loads Bitfile from Flash,

    2. MCS Firmware configure SI5338 and starts Microblaze,

    3. SPI Bootloader from Bitfile Firmware loads U-Boot into DDR (This takes a while),

    4. U-boot loads Linux from QSPI Flash into DDR


Linux

  1. Open Serial Console (e.g. putty)

    • Speed: 9600

    • COM Port

      Info

      Win OS, see device manager, Linux OS see dmesg |grep tty (UART is *USB1)


  2. Boot process takes a while, please wait...

    Image Added

  3. Linux Console:

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    petalinux login: root
    Password: root


    Info

    Note: Wait until Linux boot finished.

    Linux boot process is slower on Microblaze.


  4. You can use Linux shell now.

    Code Block
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    udhcpc				(ETH0 check)


Vivado HW Manager

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Note:

  • Add picture of HW Manager

  • add notes for the signal either groups or topics, for example:

    Control:

    • add controllable IOs with short notes..

    Monitoring:

    • add short notes for signals which will be monitored only
    • SI5338 CLKs:
      • Set radix from VIO signals to unsigned integer.
        Note: Frequency Counter is inaccurate and displayed unit is Hz
      • expected CLK Frequency...
  • Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder).

    1. Set radix from VIO signals (MGT REF, MIG_OUT, CLK1B, CLK0) to unsigned integer.
      Note: Frequency Counter is inaccurate and displayed unit is Hz

  • Monitoring:

    • MGT REF~125MHz, MIG_50MHZ~50MHz., CLK1B ~50MHz, CLK0~100MHz

    • System reset from MCS and GIO outputs

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title REV02 - Vivado Hardware Manager

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System Design - Vivado

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Note:

  • Description of Block Design, Constrains... BD Pictures from Export...

Block Design

REV02

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titleBlock Design PCB REV02

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REV01

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titleBlock Design PCB REV01 (Same as REV02 but 50 MHz ETH REV CLK is generated from MIG output with 180° Phase shift.)

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Constraints

Basic module constraints

Code Block
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title_i_bitgen_common.xdc
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property BITSTREAM.CONFIG.CONFIGRATE 66 [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property CFGBVS VCCO [current_design]
set_property CONFIG_MODE SPIx4 [current_design]
set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design]
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
set_property BITSTREAM.CONFIG.M1PIN PULLNONE [current_design]
set_property BITSTREAM.CONFIG.M2PIN PULLNONE [current_design]
set_property BITSTREAM.CONFIG.M0PIN PULLNONE [current_design]

set_property BITSTREAM.CONFIG.USR_ACCESS TIMESTAMP [current_design]


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title_i_bitgen.xdc
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLDOWN [current_design]

Design specific constraints

Code Block
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title_i_reset.xdc
set_property PULLDOWN true [get_ports reset]


Code Block
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title_i_io.xdc
#I2C
set_property PACKAGE_PIN W21 [get_ports PLL_I2C_ext_scl_o]
set_property IOSTANDARD LVCMOS33 [get_ports PLL_I2C_ext_scl_o]
set_property PACKAGE_PIN T20 [get_ports PLL_I2C_ext_sda]
set_property IOSTANDARD LVCMOS33 [get_ports PLL_I2C_ext_sda]

#Reset
set_property PACKAGE_PIN T3 [get_ports reset]
set_property IOSTANDARD LVCMOS15 [get_ports reset]
#CLKS
set_property PACKAGE_PIN R4 [get_ports {CLK1B[0]}]
set_property IOSTANDARD LVCMOS15 [get_ports {CLK1B[0]}]
set_property PACKAGE_PIN K4 [get_ports {CLK0_clk_p[0]}]
set_property IOSTANDARD DIFF_SSTL15 [get_ports {CLK0_clk_p[0]}]

#ETH PHY
set_property PACKAGE_PIN N17 [get_ports phy_rst_n]
set_property IOSTANDARD LVCMOS33 [get_ports phy_rst_n]

#EEPROM onewire (MAC ADDRESS)
set_property IOSTANDARD LVCMOS33 [get_ports EEPROM_tri_io]
set_property PACKAGE_PIN V22 [get_ports EEPROM_tri_io]


Code Block
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title_i_timing.xdc
create_clock -period 8.000 -name mgt_clk0_clk_p -waveform {0.000 4.000} [get_ports mgt_clk0_clk_p]


create_clock -period 10.000 -name {CLK0_clk_p[0]} -waveform {0.000 5.000} [get_ports {CLK0_clk_p[0]}]
create_clock -period 20.000 -name {CLK1B[0]} -waveform {0.000 10.000} [get_ports {CLK1B[0]}]
create_clock -period 15.152 -name CFGMCLK -waveform {0.000 7.576} [get_pins -hierarchical -filter {NAME =~*NO_DUAL_QUAD_MODE.QSPI_NORMAL/*STARTUP_7SERIES_GEN.STARTUP2_7SERIES_inst/CFGMCLK}]


set_false_path -from [get_clocks {CLK0_clk_p[0]}] -to [get_clocks clk_pll_i]
set_false_path -from [get_clocks mgt_clk0_clk_p] -to [get_clocks clk_pll_i]
set_false_path -from [get_pins {msys_i/SC0712_0/U0/rst_delay_i_reg[3]/C}] -to [get_pins -hierarchical -filter {NAME =~*u_msys_mig_7series_0_0_mig/u_ddr3_infrastructure/rstdiv0*/PRE}]
set_false_path -from [get_clocks -of_objects [get_pins msys_i/mig_7series_0/u_msys_mig_7series_0_0_mig/u_ddr3_infrastructure/gen_ui_extra_clocks.mmcm_i/CLKFBOUT]] -to [get_clocks mgt_clk0_clk_p]
set_false_path -from [get_clocks clk_pll_i] -to [get_clocks {msys_i/util_ds_buf_0/U0/IBUF_OUT[0]}]
set_false_path -from [get_pins {msys_i/labtools_fmeter_0/U0/F_reg[*]/C}] -to [get_pins {msys_i/vio_0/inst/PROBE_IN_INST/probe_in_reg_reg[*]/D}]
set_false_path -from [get_pins msys_i/labtools_fmeter_0/U0/COUNTER_REFCLK_inst/bl.DSP48E_2/CLK] -to [get_pins {msys_i/vio_0/inst/PROBE_IN_INST/probe_in_reg_reg[*]/D}]
set_false_path -from [get_pins {msys_i/labtools_fmeter_0/U0/FMETER_gen[*].COUNTER_F_inst/bl.DSP48E_2/CLK}] -to [get_pins {msys_i/labtools_fmeter_0/U0/F_reg[*]/D}]

Software Design - Vitis

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Note:

  • optional chapter separate

  • sections for different apps

For Vitis project creation, follow instructions from:

Vitis

Application

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----------------------------------------------------------

FPGA Example

scu

MCS Firmware to configure SI5338 and Reset System.

spi_bootloader

TE modified SPI Bootloader from Henrik Brix Andersen.

Bootloader to load app or second bootloader from flash into DDR

Descriptions:

  • Modified Files: bootloader.c
  • Changes:
    • Change the SPI defines in the header
    • Add some reiteration in the frist spi read call

xilisf_v5_11

TE modified 2020.2 xilisf_v5_11

  • Changed default Flash type to 5.

----------------------------------------------------------

Zynq Example:

fsbl

TE modified 2020.2 FSBL

General:

  • Modified Files: main.c, fsbl_hooks.h/.c (search for 'TE Mod' on source code)
  • Add Files: te_fsbl_hooks.h/.c (for hooks and board)

  • General Changes: 
    • Display FSBL Banner and Device ID

Module Specific:

  • Add Files: all TE Files start with te_*
    • READ MAC from EEPROM and make Address accessible by UBOOT (need copy defines on uboot platform-top.h)
    • CPLD access
    • Read CPLD Firmware and SoC Type
    • Configure Marvell PHY

fsbl_flash

TE modified 2020.2 FSBL

General:

  • Modified Files: main.c
  • General Changes:
    • Display FSBL Banner
    • Set FSBL Boot Mode to JTAG
    • Disable Memory initialisation

ZynqMP Example:

----------------------------------------------------------

zynqmp_fsbl

TE modified 2020.2 FSBL

General:

  • Modified Files: xfsbl_main.c, xfsbl_hooks.h/.c, xfsbl_board.h/.c (search for 'TE Mod' on source code)
  • Add Files: te_xfsbl_hooks.h/.c (for hooks and board)
  • General Changes: 
    • Display FSBL Banner and Device Name

Module Specific:

  • Add Files: all TE Files start with te_*
    • Si5338 Configuration
    • ETH+OTG Reset over MIO

zynqmp_fsbl_flash

TE modified 2020.2 FSBL

General:

  • Modified Files: xfsbl_initialisation.c, xfsbl_hw.h, xfsbl_handoff.c, xfsbl_main.c
  • General Changes:
    • Display FSBL Banner
    • Set FSBL Boot Mode to JTAG
    • Disable Memory initialisation


zynqmp_pmufw

Xilinx default PMU firmware.

----------------------------------------------------------

General Example:

hello_te0820

Hello TE0820 is a Xilinx Hello World example as endless loop instead of one console output.

u-boot

U-Boot.elf is generated with PetaLinux. Vitis is used to generate Boot.bin.

eeprom

eeprom is a petalinux application that executes on startup. It reads the unique 48-bit MAC from the onboard eeprom and uses it to set the system MAC address.


Template location: "<project folder>\sw_lib\sw_apps\"

scu_te0712

MCS Firmware to configure SI5338 and Reset System.

spi_bootloader

TE modified SPI Bootloader from Henrik Brix Andersen.

Bootloader to load app or second bootloader from flash into DDR.

Here it loads the u-boot.elf from QSPI-Flash to RAM. Hence u-boot.srec becomes redundant.

Descriptions:

  • Modified Files: bootloader.c
  • Changes:
    • Change the SPI defines in the header
    • Add some reiteration in the frist spi read call

hello_te0712

Hello TE0712 is a Xilinx Hello World example as endless loop instead of one console output.

u-boot

U-Boot.elf is generated with PetaLinux. Vitis is used to generate u-boot.srec(obsolete). Vivado to generate *.mcs

eeprom

eeprom is a petalinux application that executes on startup. It reads the unique 48-bit MAC from the onboard eeprom and uses it to set the system MAC address.

Software Design -  PetaLinux

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Note:

  • optional chapter separate

  • sections for linux

  • Add "No changes." or "Activate: and add List"

For PetaLinux installation and project creation, follow instructions from:

Config

Start with petalinux-config or petalinux-config --get-hw-description

(Tipp: Search for Settings with shortcut "Shift"+"/")

Changes:

  • SUBSYSTEM_FLASH_AXI_QUAD_SPI_0_BANKLESS_PART0_SIZE = 0x5E0000  (fpga)

  • SUBSYSTEM_FLASH_AXI_QUAD_SPI_0_BANKLESS_PART1_SIZE = 0x400000  (boot)

  • SUBSYSTEM_FLASH_AXI_QUAD_SPI_0_BANKLESS_PART2_SIZE = 0x20000    (bootenv)

  • SUBSYSTEM_FLASH_AXI_QUAD_SPI_0_BANKLESS_PART3_SIZE = 0xB00000  (kernel)

    • (with this kernel flash address is 0xA00000 (fpga+boot+bootenv) and Kernel size 0xB00000)

U-Boot

Start with petalinux-config -c u-boot

Changes:

  • CONFIG_ENV_IS_NOWHERE=y

  • # CONFIG_ENV_IS_IN_SPI_FLASH is not set

  • # CONFIG_PHY_ATHEROS is not set

  • # CONFIG_PHY_BROADCOM is not set

  • # CONFIG_PHY_DAVICOM is not set

  • # CONFIG_PHY_LXT is not set

  • # CONFIG_PHY_MICREL_KSZ90X1 is not set

  • # CONFIG_PHY_MICREL is not set

  • # CONFIG_PHY_NATSEMI is not set

  • # CONFIG_PHY_REALTEK is not set

  • CONFIG_RGMII=y


Content of platform-top.h located in <plnx-proj-root>\project-spec\meta-user\recipes-bsp\u-boot\files:

Code Block
languagejava
#include <configs/microblaze-generic.h>
#include <configs/platform-auto.h>

#define CONFIG_SYS_BOOTM_LEN 0xF000000

Device Tree

Content of system-user.dtsi located in <petalinux project directory>\project-spec\meta-user\recipes-bsp\device-tree\files:

Code Block
languagejs
/include/ "system-conf.dtsi"
/ {
};
 
/* QSPI PHY */
 
&axi_quad_spi_0 {
    #address-cells = <1>;
    #size-cells = <0>;
    flash0: flash@0 {
        compatible = "jedec,spi-nor";
        spi-tx-bus-width=<1>;
        spi-rx-bus-width=<4>;
        reg = <0x0>;
        #address-cells = <1>;
        #size-cells = <1>;
        spi-max-frequency = <25000000>;
    };
};
 
 
/* ETH PHY */
&axi_ethernetlite_0 {
    phy-handle = <&phy0>;
    mdio {
        #address-cells = <1>;
        #size-cells = <0>;
        phy0: phy@0 {
            device_type = "ethernet-phy";
            reg = <1>;
        };
    };
};

Kernel

Start with petalinux-config -c kernel

Changes:

  • No changes.

Rootfs

Start with petalinux-config -c rootfs

Changes:

  • # CONFIG_dropbear is not set

  • # CONFIG_dropbear-dev is not set

  • # CONFIG_dropbear-dbg is not set

  • # CONFIG_package-group-core-ssh-dropbear is not set

  • # CONFIG_packagegroup-core-ssh-dropbear-dev is not set

  • # CONFIG_packagegroup-core-ssh-dropbear-dbg is not set

  • # CONFIG_imagefeature-ssh-server-dropbear is not set


"Dropbear" is part of the "petalinux-image-minimal" configuration, so changes in the petalinux rootfs will not be applied. To remove "dropbear" anyway, enter the following line in petalinuxbsp.conf:

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PACKAGE_EXCLUDE += " dropbear dropbear-openssh-sftp-server dropbear-dev dropbear-dbg dropbear-openssh-sftp-server packagegroup-core-ssh-dropbear packagegroup-core-ssh-dropbear-dbg packagegroup-core-ssh-dropbear-dev"

Applications

No additional application.

Additional Software

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Note:

  • Add description for other Software, for example SI CLK Builder ...

  • SI5338 and SI5345 also Link to:

SI5338

File location "<project folder>\misc\Si5338\Si5338-*.slabtimeproj"

General documentation how you work with this project will be available on Si5338


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Appx. A: Change History and Legal Notices

Document Change History

To get content of older revision  got to "Change History"  of this page and select older document revision number.

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Date

Document Revision

Authors

Description

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dateFormatyyyy-MM-dd

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current-version
current-version
prefixv.

Page info
infoTypeModified by
typeFlat

  • new spi bootloader by Henrik Brix Andersen
  • adjusted offsets

2022-01-18


v.40


Waldemar Hanemann


  • MB_MCS elf-File bugfix
  • eeprom Skript bugfix
2022-01-11


v.39


Waldemar Hanemann


  • 2021.2 update
  • added eeprom interface to get MAC address
  • added boot script
2021-06-28


v.38


Manuela Strücker

  • 2020.2 update
  • document style update
  • update TE Board Part List
2021-06-28v.37John Hartfiel
  • typo correction

2020-03-25

v.35

John Hartfiel

  • update scripts

2020-01-21

v.34

John Hartfiel

  • update scripts, new features and linux support

2020-01-08

v.33

John Hartfiel

  • 2019.2 release

2019-04-18

v.32

John Hartfiel

  • small design changes

2019-02-22

v.31

John Hartfiel

  • 2018.3 release (include design reworks)

2018-09-06

v.30

John Hartfiel

  • 2018.2 release

2018-05-25

v.28

John Hartfiel

  • Design update

2018-05-08

v.27

John Hartfiel

  • Know Issues

  • Documentation

2018-04-12

v.23

John Hartfiel

  • Design Update

2018-03-28

v.22

John Hartfiel

  • Know Issue for PCB REV01 only

  • Fix typo

  • New assembly variant

2018-02-13

v.19

John Hartfiel

  • Release 2017.4

2018-01-08

v.16

John Hartfiel

  • Add SCU source path

2017-12-15

v.15

John Hartfiel

  • Update Design and Description

2017-11-07

v.11

John Hartfiel

  • Update Design Files

2017-10-06

v.10

John Hartfiel

  • small Document Update

2017-10-05

v.8

John Hartfiel

  • Release 2017.2

2017-09-11

v.1

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created-user
created-user

  • Initial release

...

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Legal Notices

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IN:Legal Notices

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