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Design Name is always "TE Series Name" + Design name, for example "TE0720 Test Board"
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Refer to http://trenz.org/te0712-info for the current online version of this manual and other available documentation.
For directly getting started with the prebuilt files jump to the section Launch.
Key Features
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Manuela Strücker |
2020-03-25
John Hartfiel
2020-01-22
John Hartfiel
John Hartfiel
2019-04-18
John Hartfiel
2019-02-22
John Hartfiel
2018-09-05 2018.2
2018-05-25 | te07122017.4
2018-04-12 | te07122017.4
2018-03-28 | te07122017.4
2018-01-08 2017.4
| 20172017-12-15
2017-11-07
| 2017.22017-10-05
|
Release Notes and Know Issues
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title | Known Issues |
Issues
Description
Workaround
To be fixed version
For PCB REV01 only: prebuilt does not boot
There is a Pullup missing on REV01 I2C SCL, so SI5338 configuration over MCS fails
Remove MCS
solved with 20180528 update
For PCB REV01 only: CLK1B is not available on
additional clk is not connected on PCB
use other internal generated CLK, maybe more effort is needed to get ETH running
solved with 20180528 update
SREC SPI BootLoader default Offset
Default load offset is set to 0x400000
Change manually on SDK to 0x5E0000
solved with 20180412 update
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Release Notes and Known Issues
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Requirements
Software
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Software
Note | Vitis | 2020.2 | needed, Vivado is included into Vitis installation | PetaLinux | 2020.2 | needed | SI ClockBuilder Pro | --- | optional | |
Hardware
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Requirements
Software
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Complete List is available on "<project folder>\board_files\*_board_files.csv"
Design supports following modules:
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Hardware
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Complete List is available on "<project folder>\board_files\*_board_files.csv"
Design supports following modules:
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*used as reference |
Design supports following carriers:
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title-alignment | center |
title | Hardware Carrier |
Carrier Model
Notes
TE0701
TE0703*
TE0705
TE0706
TEBA0841
*used as reference
Additional HW Requirements:
anchor | Table_AHW |
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title-alignment | center |
title | Additional Hardware |
Additional Hardware
Notes
USB Cable for JTAG/UART
Check Carrier Board and Programmer for correct type
XMOD Programmer
Carrier Board dependent, only if carrier has no own FTDI
Content
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For general structure and usage of the reference design, see Project Delivery - Xilinx devices
Design Sources
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<project folder>\constraints
<project folder>\ip_lib
<project folder>\board_files
*used as reference |
Design supports following carriers:
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*used as reference |
Additional HW Requirements:
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For general structure and usage of the reference design, see Project Delivery - AMD devices
Design Sources
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Additional Sources
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Prebuilt
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Notes :
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Download
Reference Design is only usable with the specified Vivado/Vitis/PetaLinux version. Do never use different Versions of AMD(Xilinx) Software for the same Project.
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Reference Design is available on:
Design Flow
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Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first launch. |
See also: AMD Development Tools#XilinxSoftware-BasicUserGuides
The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.
TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Vivado/Vitis GUI. For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality
Note |
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Caution! Win OS has a 260 character limit for path lengths which can affect the Vivado tools. To avoid this issue, use Virtual Drive or the shortest possible names and directory locations for the reference design (for example "x:\<project folder>") |
Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
Code Block language bash theme Midnight title _create_win_setup.cmd/_create_linux_setup.sh ------------------------Set design paths---------------------------- -- Run Design with: _create_win_setup -- Use Design Path: <absolute project path> -------------------------------------------------------------------- -------------------------TE Reference Design--------------------------- -------------------------------------------------------------------- -- (0) Module selection guide, project creation...prebuilt export... -- (1) Create minimum setup of CMD-Files and exit Batch -- (2) Create maximum setup of CMD-Files and exit Batch -- (3) (internal only) Dev -- (4) (internal only) Prod -- (c) Go to CMD-File Generation (Manual setup) -- (d) Go to Documentation (Web Documentation) -- (g) Install Board Files from Xilinx Board Store (beta) -- (a) Start design with unsupported Vivado Version (beta) -- (x) Exit Batch (nothing is done!) ---- Select (ex.:'0' for module selection guide):
Press 0 and enter to start "Module Selection Guide"
- (optional Win OS) Generate Virtual Drive or use short directory for the reference design (for example x:\<design name>)
- Createproject and follow instructions of the product selection guide, settings file will be configured automatically during this process.
optional for manual changes: Select correct device and AMD(Xilinx) install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
Note Note: Select correct one, see also Vivado Board Part Flow
Create hardware description file (.xsa file) for PetaLinux project and export to prebuilt folder
Code Block language py theme Midnight title run on Vivado TCL (Script generates design and export files into "<project folder>\prebuilt\hardware\<short name>")
Additional Sources
anchor | Table_ADS |
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title-alignment | center |
title | Additional design sources |
Type
Location
Notes
SI5338
<project folder>/misc/Si5338
SI5338 Project with current PLL Configuration
Prebuilt
hidden | true |
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id | Comments |
Notes :
anchor | Table_PF |
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title-alignment | center |
title | Prebuilt files |
File
File-Extension
Description
Distro Boot file
Debian SD-Image
*.img
Debian Image for SD-Card
MCS-File
*.mcs
Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)
MMI-File
*.mmi
File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)
SREC-File
*.srec
Converted Software Application for MicroBlaze Processor Systems
anchor | Table_PF |
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title-alignment | center |
title | Prebuilt files (only on ZIP with prebuilt content) |
File
File-Extension
Description
BIT-File
*.bit
FPGA (PL Part) Configuration File
DebugProbes-File
*.ltx
Definition File for Vivado/Vivado Labtools Debugging Interface
Diverse Reports
---
Report files in different formats
Hardware-Platform-Description-File
*.xsa
Exported Vivado hardware description file for Vitis and PetaLinux
LabTools Project-File
*.lpr
Vivado Labtools Project File
MCS-File
*.mcs
Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)
MMI-File
*.mmi
File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)
OS-Image
*.ub
Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)
Software-Application-File
*.elf
Software Application for Zynq or MicroBlaze Processor Systems
SREC-File
*.srec
Converted Software Application for MicroBlaze Processor Systems
Download
Reference Design is only usable with the specified Vivado/Vitis/PetaLinux version. Do never use different Versions of Xilinx Software for the same Project.
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Reference Design is available on:
Design Flow
scroll-pdf | true |
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scroll-office | true |
scroll-chm | true |
scroll-docbook | true |
scroll-eclipsehelp | true |
scroll-epub | true |
scroll-html | true |
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Notes :
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Note |
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Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first launch. |
See also:Xilinx Development Tools
The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.
TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/Vitis GUI. For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality
Note |
---|
Caution! Win OS has a 260 character limit for path lengths which can affect the Vivado tools. To avoid this issue, use Virtual Drive or the shortest possible names and directory locations for the reference design (for example "x:\<project folder>") |
Press 0 and enter to start "Module Selection Guide"
- Createproject and follow instructions of the product selection guide, settings file will be configured automatically during this process.
optional for manual changes: Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
Note Note: Select correct one, see also Vivado Board Part Flow
Create hardware description file (.xsa file) for PetaLinux project and export to prebuilt folder
Code Block language py theme Midnight title run on Vivado TCL (Script generates design and export files into "<project folder>\prebuilt\hardware\<short name>") TE::hw_build_design -export_prebuilt
Create and configure your PetaLinux project with exported .xsa-file, see PetaLinux KICKstartInfo Using Vivado GUI is the same, except file export to prebuilt folder.
- use TE Template from "<project folder>\os\petalinux"
use exported .xsa file from "<project folder>\prebuilt\hardware\<short name>" . Note: HW Export from Vivado GUI creates another path as default workspace.
- copy u-boot.elf, image.ub and boot.scr from "<plnx-proj-root>/images/linux" to prebuilt folder
- copy u-boot.elf, bl31.elf, image.ub and boot.scr from "<plnx-proj-root>/images/linux" to prebuilt folder
- ...
Copy "<project folder>\prebuilt\software\<short name>\srec_spi_bootloader.elf" into "<project folder>\firmware\microblaze_0\"
Copy "<project folder>\workspace\sdk\scu_te0712\Release\scu_te0712.elf" into "\firmware\microblaze_mcs_0\"
Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
Code Block | ||||||
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------------------------Set design paths----------------------------
-- Run Design with: _create_win_setup
-- Use Design Path: <absolute project path>
--------------------------------------------------------------------
-------------------------TE Reference Design---------------------------
--------------------------------------------------------------------
-- (0) Module selection guide, project creation...prebuilt export...
-- (1) Create minimum setup of CMD-Files and exit Batch
-- (2) Create maximum setup of CMD-Files and exit Batch
-- (3) (internal only) Dev
-- (4) (internal only) Prod
-- (c) Go to CMD-File Generation (Manual setup)
-- (d) Go to Documentation (Web Documentation)
-- (g) Install Board Files from Xilinx Board Store (beta)
-- (a) Start design with unsupported Vivado Version (beta)
-- (x) Exit Batch (nothing is done!)
----
Select (ex.:'0' for module selection guide): |
The build images are located in the "<plnx-proj-root>/images/linux" directory
Info |
---|
Important Note: Select correct Flash partition offset on petalinux-config: Subsystem Auto HW Settings → Flash Settings, FPGA+Boot+bootenv=0x900000 (increase automatically generate Boot partition), increase image size to A:, see Config |
copy u-boot.elf and image.ub from "<plnx-proj-root>/images/linux" to prebuilt folder
Info |
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"<project folder>\prebuilt\os\petalinux\<ddr size>" or "<project folder>\prebuilt\os\petalinux\<short name>" |
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This step depends on Xilinx Device/Hardware for Zynq-7000 series for ZynqMP for ... |
Generate Programming Files with Vitis
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TE::sw_run_vitis -all
TE::sw_run_vitis (optional; Start Vitis from Vivado GUI or start with TE Scripts on Vivado TCL) |
Note |
---|
TCL scripts generate also platform project, this must be done manually in case GUI is used. See Vitis |
Regenerate Vivado Project or Update Bitfile only with "srec_spi_bootloader.elf" and "scu_te0712.elf"
TE::hw_build_design -export_prebuilt |
Launch
scroll-pdf | true |
---|---|
scroll-office | true |
scroll-chm | true |
scroll-docbook | true |
scroll-eclipsehelp | true |
scroll-epub | true |
scroll-html | true |
Info Using Vivado GUI is the same, except file export to prebuilt folder.
- Create and configure your PetaLinux project with exported .xsa-file, see PetaLinux KICKstart
- use TE Template from "<project folder>\os\petalinux"
use exported .xsa file from "<project folder>\prebuilt\hardware\<short name>" . Note: HW Export from Vivado GUI creates another path as default workspace.
The petalinux build images are located in the "<plnx-proj-root>/images/linux" directory
Info Important Note: Select correct Flash partition offset on petalinux-config: Subsystem Auto HW Settings → Flash Settings, FPGA+Boot+bootenv=0xA00000 (increase automatically generate Boot partition), increase image size to A:, see Config
- Configure the boot.scr file as needed, see Distro Boot with Boot.scr. Kernel flash address and kernel size are set here.
- Copy PetaLinux build image files to prebuilt folder
copy u-boot.elf, image.ub and boot.scr from "<plnx-proj-root>/images/linux" to prebuilt folder
Info "<project folder>\prebuilt\os\petalinux\<ddr size>" or "<project folder>\prebuilt\os\petalinux\<short name>"
Page properties hidden true id Comments
Note:
Programming and Startup procedure
Note |
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Check Module and Carrier TRMs for proper HW configuration before you try any design. Reference Design is also available with prebuilt files. It's recommended to use TE prebuilt files for first launch. |
Xilinx documentation for programming and debugging: Vivado/Vitis/SDSoC-Xilinx Software Programming and Debugging
Get prebuilt boot binaries
This step depends on Xilinx Device/Hardware
for Zynq-7000 series
- copy u-boot.elf, image.ub and boot.scr from "<plnx-proj-root>/images/linux" to prebuilt folder
for ZynqMP
- copy u-boot.elf, bl31.elf, image.ub and boot.scr from "<plnx-proj-root>/images/linux" to prebuilt folder
for ...
- ...
Generate Programming Files with Vitis
Select create and open delivery binary folder
Info |
---|
Note: Folder "<project folder>\_binaries_<Article Name>" with subfolder "boot_<app name>" for different applications will be generated |
QSPI-Boot mode
Connect JTAG and power on carrier with module
Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"
Code Block language py theme Midnight title run on Vivado TCL (Script programs BOOT.bin on QSPI flashgenerates applications and bootable files, which are defined in "test_board\sw_lib\apps_list.csv") TE::prsw_programrun_flashvitis -swapp u-boot
Reboot (if not done automatically)
SD-Boot mode
Not used on this Example.
JTAG
Not used on this Example.
Usage
Prepare HW like described on section Programming
Connect UART USB (most cases same as JTAG)
all TE::sw_run_vitis (optional; Start Vitis from Vivado GUI or start with TE Scripts on Vivado TCL)
Note TCL scripts generate also platform project, this must be done manually in case GUI is used. See Vitis
- (Optional) BlockRam Firmware Update
Power on PCB
Expand | ||
---|---|---|
| ||
1. FPGA Loads Bitfile from Flash, 2. MCS Firmware configure SI5338 and starts Microblaze, 3. SREC Bootloader from Bitfile Firmware loads U-Boot into DDR (This takes a while), 4. U-boot loads Linux from QSPI Flash into DDR |
Linux
Speed: 9600
Boot process takes a while, please wait...
Image Removed
Linux Console:
Code Block Copy "<project folder>\prebuilt\software\<short name>\spi_bootloader.elf" into "<project folder>\firmware\microblaze_0\"
Copy "<project folder>\workspace\sdk\scu_te0712\Release\scu_te0712.elf" into "\firmware\microblaze_mcs_0\"
Regenerate Vivado Project or Update Bitfile only with "spi_bootloader.elf" and "scu_te0712.elf"
Code Block
language bash theme Midnight
petalinux login: root Password: root
Info Note: Wait until Linux boot finished.
Linux boot process is slower on Microblaze.
You can use Linux shell now.
Code Block language bash theme Midnight udhcpc (ETH0 check)
Open Serial Console (e.g. putty)
COM Port
Info |
---|
Win OS, see device manager, Linux OS see dmesg |grep tty (UART is *USB1) |
TE::hw_build_design -export_prebuilt TE::sw_run_vitis -all
Launch
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Programming
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Note:
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Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder).
Set radix from VIO signals (MGT REF, MIG_OUT, CLK1B, CLK0) to unsigned integer.
Note: Frequency Counter is inaccurate and displayed unit is Hz
Monitoring:
MGT REF~125MHz, MIG_50MHZ~50MHz., CLK1B ~50MHz, CLK0~100MHz
System reset from MCS and GIO outputs
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System Design - Vivado
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Block Design
REV02
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REV01
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Constrains
Basic module constrains
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set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property BITSTREAM.CONFIG.CONFIGRATE 66 [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property CFGBVS VCCO [current_design]
set_property CONFIG_MODE SPIx4 [current_design]
set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design]
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
set_property BITSTREAM.CONFIG.M1PIN PULLNONE [current_design]
set_property BITSTREAM.CONFIG.M2PIN PULLNONE [current_design]
set_property BITSTREAM.CONFIG.M0PIN PULLNONE [current_design]
set_property BITSTREAM.CONFIG.USR_ACCESS TIMESTAMP [current_design] |
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set_property BITSTREAM.CONFIG.UNUSEDPIN PULLDOWN [current_design] |
Design specific constrain
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set_property PULLDOWN true [get_ports reset] |
language | ruby |
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title | _i_io.xdc |
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Check Module and Carrier TRMs for proper HW configuration before you try any design. Reference Design is also available with prebuilt files. It's recommended to use TE prebuilt files for first launch. |
AMD(Xilinx) documentation for programming and debugging: Vivado/Vitis/SDSoC-Xilinx Software Programming and Debugging
Get prebuilt boot binaries
- Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell
- Press 0 and enter to start "Module Selection Guide"
- Select assembly version
- Validate selection
Select create and open delivery binary folder
Info Note: Folder "<project folder>\_binaries_<Article Name>" with subfolder "boot_<app name>" for different applications will be generated
QSPI-Boot mode
Option for u-boot.mcs on QSPI Flash.
(u-boot.mcs contains all files necessary to boot up linux)
Connect the USB cable(JTAG) and power supply on carrier with module
Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd".
Enter the following TCL-Command into the TCL-Console inside Vivado to program the QSPI Flash.Code Block language py theme Midnight title run on Vivado TCL (Script programs u-boot.mcs onto QSPI flash) TE::pr_program_flash -swapp u-boot
Reboot (if not done automatically)
SD-Boot mode
Not used on this Example.
JTAG
Not used on this Example.
Usage
Prepare HW like described on section Programming
Connect UART USB (most cases same as JTAG)
Select QSPI as Boot Mode
Info Note: See TRM of the Carrier, which is used.
Power On PCB and push the reset button if present on carrier.
Expand title boot process 1. FPGA Loads Bitfile from Flash,
2. MCS Firmware configure SI5338 (per default off with REV03) and starts Microblaze,
3. SPI Bootloader from Bitfile Firmware loads U-Boot into DDR (This takes a while),
4. U-boot loads Linux from QSPI Flash into DDR
Linux
Open Serial Console (e.g. putty)
Speed: 9600
COM Port
Info Win OS, see device manager, Linux OS see dmesg |grep tty (UART is *USB1)
Boot process takes a while, please wait...
Image AddedLinux Console:
Code Block language bash theme Midnight petalinux login: petalinux -> assign new password
Info Note: Wait until Linux boot finished.
Linux boot process is slower on Microblaze.
You can use Linux shell now.
Code Block language bash theme Midnight udhcpc (ETH0 check)
Vivado HW Manager
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Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder).
Set radix from VIO signals (MGT REF, MIG_OUT, CLK1B, CLK0) to unsigned integer.
Note: Frequency Counter is inaccurate and displayed unit is Hz
Monitoring:
MGT REF~125MHz, MIG_50MHZ~50MHz., CLK1B ~50MHz, CLK0~100MHz
System reset from MCS and GIO outputs
- 1. → Si5338 PLL was programmed 0 = NO | 1 = YES
- 2. → Error occurred during PLL programming 0 = NO | 1 = YES
- 3. → Module Revision ( Can be set in the Blockdiagram → SC0712 IP)
draw.io Diagram border true diagramName HWManager_TE0712 simpleViewer false width 900 links auto tbstyle top diagramDisplayName lbox true diagramWidth 1599 revision 4
System Design - Vivado
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Constraints
Basic module constraints
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set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property BITSTREAM.CONFIG.CONFIGRATE 66 [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property CFGBVS VCCO [current_design]
set_property CONFIG_MODE SPIx4 [current_design]
set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design]
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
set_property BITSTREAM.CONFIG.M1PIN PULLNONE [current_design]
set_property BITSTREAM.CONFIG.M2PIN PULLNONE [current_design]
set_property BITSTREAM.CONFIG.M0PIN PULLNONE [current_design]
set_property BITSTREAM.CONFIG.USR_ACCESS TIMESTAMP [current_design] |
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set_property BITSTREAM.CONFIG.UNUSEDPIN PULLDOWN [current_design] |
Design specific constraints
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createset_clockproperty -period 8.000 -name mgt_clk0_clk_p -waveform {0.000 4.000}PULLDOWN true [get_ports reset] |
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#I2C #set_property PACKAGE_PIN W21 [get_ports mgtPLL_clk0I2C_clkscl_pio] create#set_clockproperty -period 10.000 -name {CLK0_clk_p[0]} -waveform {0.000 5.000}IOSTANDARD LVCMOS33 [get_ports PLL_I2C_scl_io] #set_property PACKAGE_PIN T20 [get_ports {CLK0_clk_p[0]}] create_clock -period 20.000 -name {CLK1B[0]} -waveform {0.000 10.000}PLL_I2C_sda_io] #set_property IOSTANDARD LVCMOS33 [get_ports PLL_I2C_sda_io] set_property PACKAGE_PIN W21 [get_ports {CLK1B[0]}] create_clock -period 15.152 -name CFGMCLK -waveform {0.000 7.576} [get_pins -hierarchical -filter {NAME =~*NO_DUAL_QUAD_MODE.QSPI_NORMAL/*STARTUP_7SERIES_GEN.STARTUP2_7SERIES_inst/CFGMCLK}] set_false_path -from [get_clocks {CLK0_clk_p[0]}] -to [get_clocks clk_pll_i] set_false_path -from [get_clocks mgt_clk0_clk_p] -to [get_clocks clk_pll_i] set_false_path -from [get_pins {msys_i/SC0712_0/U0/rst_delay_i_reg[3]/C}] -to [get_pins -hierarchical -filter {NAME =~*u_msys_mig_7series_0_0_mig/u_ddr3_infrastructure/rstdiv0*/PRE}] set_false_path -from [get_clocks -of_objects [get_pins msys_i/mig_7series_0/u_msys_mig_7series_0_0_mig/u_ddr3_infrastructure/gen_ui_extra_clocks.mmcm_i/CLKFBOUT]] -to [get_clocks mgt_clk0_clk_p] set_false_path -from [get_clocks clk_pll_i] -to [get_clocks {msys_i/util_ds_buf_0/U0/IBUF_OUT[0]}] set_false_path -from [get_pins {msys_i/labtools_fmeter_0/U0/F_reg[*]/C}] -to [get_pins {msys_i/vio_0/inst/PROBE_IN_INST/probe_in_reg_reg[*]/D}] set_false_path -from [get_pins msys_i/labtools_fmeter_0/U0/COUNTER_REFCLK_inst/bl.DSP48E_2/CLK] -to [get_pins {msys_i/vio_0/inst/PROBE_IN_INST/probe_in_reg_reg[*]/D}] set_false_path -from [get_pins {msys_i/labtools_fmeter_0/U0/FMETER_gen[*].COUNTER_F_inst/bl.DSP48E_2/CLK}] -to [get_pins {msys_i/labtools_fmeter_0/U0/F_reg[*]/D}] |
Software Design - Vitis
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PLL_I2C_ext_scl_o]
set_property IOSTANDARD LVCMOS33 [get_ports PLL_I2C_ext_scl_o]
set_property PACKAGE_PIN T20 [get_ports PLL_I2C_ext_sda]
set_property IOSTANDARD LVCMOS33 [get_ports PLL_I2C_ext_sda]
#Reset
set_property PACKAGE_PIN T3 [get_ports reset]
set_property IOSTANDARD LVCMOS15 [get_ports reset]
#CLKS
set_property PACKAGE_PIN R4 [get_ports {CLK1B[0]}]
set_property IOSTANDARD LVCMOS15 [get_ports {CLK1B[0]}]
set_property PACKAGE_PIN K4 [get_ports {CLK0_clk_p[0]}]
set_property IOSTANDARD DIFF_SSTL15 [get_ports {CLK0_clk_p[0]}]
#ETH PHY
set_property PACKAGE_PIN N17 [get_ports phy_rst_n]
set_property IOSTANDARD LVCMOS33 [get_ports phy_rst_n]
#EEPROM onewire (MAC ADDRESS)
set_property IOSTANDARD LVCMOS33 [get_ports EEPROM_tri_io]
set_property PACKAGE_PIN V22 [get_ports EEPROM_tri_io]
#I2C connected to CPLD
set_property -dict {IOSTANDARD LVCMOS33 PACKAGE_PIN W22} [get_ports IIC_0_scl_io]
set_property -dict {IOSTANDARD LVCMOS33 PACKAGE_PIN U22} [get_ports IIC_0_sda_io] |
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create_clock -period 8.000 -name mgt_clk0_clk_p -waveform {0.000 4.000} [get_ports mgt_clk0_clk_p]
create_clock -period 10.000 -name {CLK0_clk_p[0]} -waveform {0.000 5.000} [get_ports {CLK0_clk_p[0]}]
create_clock -period 20.000 -name {CLK1B[0]} -waveform {0.000 10.000} [get_ports {CLK1B[0]}]
create_clock -period 15.152 -name CFGMCLK -waveform {0.000 7.576} [get_pins -hierarchical -filter {NAME =~*NO_DUAL_QUAD_MODE.QSPI_NORMAL/*STARTUP_7SERIES_GEN.STARTUP2_7SERIES_inst/CFGMCLK}]
set_false_path -from [get_clocks {CLK0_clk_p[0]}] -to [get_clocks clk_pll_i]
set_false_path -from [get_clocks mgt_clk0_clk_p] -to [get_clocks clk_pll_i]
set_false_path -from [get_pins {msys_i/SC0712_0/U0/rst_delay_i_reg[3]/C}] -to [get_pins -hierarchical -filter {NAME =~*u_msys_mig_7series_0_0_mig/u_ddr3_infrastructure/rstdiv0*/PRE}]
set_false_path -from [get_clocks -of_objects [get_pins msys_i/mig_7series_0/u_msys_mig_7series_0_0_mig/u_ddr3_infrastructure/gen_ui_extra_clocks.mmcm_i/CLKFBOUT]] -to [get_clocks mgt_clk0_clk_p]
set _xlnx_shared_i0 [get_pins {msys_i/vio_0/inst/PROBE_IN_INST/probe_in_reg_reg[*]/D}]
set_false_path -from [get_pins {msys_i/labtools_fmeter_0/U0/F_reg[*]/C}] -to $_xlnx_shared_i0
set_false_path -from [get_pins msys_i/labtools_fmeter_0/U0/COUNTER_REFCLK_inst/bl.DSP48E_2/CLK] -to $_xlnx_shared_i0
set_false_path -from [get_pins {msys_i/labtools_fmeter_0/U0/FMETER_gen[*].COUNTER_F_inst/bl.DSP48E_2/CLK}] -to [get_pins {msys_i/labtools_fmeter_0/U0/F_reg[*]/D}] |
Software Design - Vitis
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For Vitis project creation, follow instructions from:
Application
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-------- |
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Note:
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For Vitis project creation, follow instructions from:
Application
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---------------------------------------------------------- FPGA Example scuMCS Firmware to configure SI5338 and Reset System. srec_spi_bootloaderTE modified 2020.2 SREC Bootloader to load app or second bootloader from flash into DDR Descriptions:
xilisf_v5_11TE modified 2020.2 xilisf_v5_11
---------------------------------------------------------- Zynq Example: fsblTE modified 2020.2 FSBL General:
Module Specific:
fsbl_flashTE modified 2020.2 FSBL General:
ZynqMP Example: ---------------------------------------------------------- zynqmp_fsblFPGA Example scuMCS Firmware to configure SI5338 and Reset System. spi_bootloaderTE modified 2020.2 FSBLSPI Bootloader from Henrik Brix Andersen. Bootloader to load app or second bootloader from flash into DDR DescriptionsGeneral:
Module Specific:
zynqmp_fsbl_flashTE modified 2020.2 FSBL General:
zynqmp_pmufwXilinx default PMU firmware
xilisf_v5_11TE modified 2020.2 xilisf_v5_11
---------------------------------------------------------- General Zynq Example: hello_te0820Hello TE0820 is a Xilinx Hello World example as endless loop instead of one console output. u-bootU-Boot.elf is generated with PetaLinux. Vitis is used to generate Boot.bin. |
Template location: "<project folder>\sw_lib\sw_apps\"
scu_te0712
MCS Firmware to configure SI5338 and Reset System.
srec_spi_bootloader
TE modified 2020.2 SREC
Bootloader to load app or second bootloader from flash into DDR
Descriptions:
Modified Files: blconfig.h, bootloader.c
Changes:
Add some console outputs and changed bootloader read address.
Add bugfix for 2018.2 qspi flash (some reinitialisation)
hello_te0712
Hello TE0712 is a Xilinx Hello World example as endless loop instead of one console output.
u-boot
U-Boot.elf is generated with PetaLinux. Vitis is used to generate u-boot.srec. Vivado to generate *.mcs
Software Design - PetaLinux
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fsblTE modified 2020.2 FSBL General:
Module Specific:
fsbl_flashTE modified 2020.2 FSBL General:
ZynqMP Example: ---------------------------------------------------------- zynqmp_fsblTE modified 2020.2 FSBL General:
Module Specific:
zynqmp_fsbl_flashTE modified 2020.2 FSBL General:
zynqmp_pmufwXilinx default PMU firmware. ---------------------------------------------------------- General Example: hello_te0820Hello TE0820 is a Xilinx Hello World example as endless loop instead of one console output. u-bootU-Boot.elf is generated with PetaLinux. Vitis is used to generate Boot.bin. eepromeeprom is a petalinux application that executes on startup. It reads the unique 48-bit MAC from the onboard eeprom and uses it to set the system MAC address. |
Template location: "<project folder>\sw_lib\sw_apps\"
scu_te0712
MCS Firmware to configure SI5338 and Reset System.
spi_bootloader
TE modified SPI Bootloader from Henrik Brix Andersen.
Bootloader to load app or second bootloader from flash into DDR.
Here it loads the u-boot.elf from QSPI-Flash to RAM. Hence u-boot.srec becomes redundant.
Descriptions:
- Modified Files: bootloader.c
- Changes:
- Change the SPI defines in the header
- Add some reiteration in the frist spi read call
hello_te0712
Hello TE0712 is a AMD(Xilinx) Hello World example as endless loop instead of one console output.
u-boot
U-Boot.elf is generated with PetaLinux. Vitis is used to generate u-boot.srec(obsolete). Vivado to generate *.mcs
Software Design - PetaLinux
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For PetaLinux installation and project creation, follow instructions from:
Config
Start with petalinux-config or petalinux-config --get-hw-description
(Tipp: Search for Settings with shortcut "Shift"+"/")
Changes:
SUBSYSTEM_FLASH_AXI_QUAD_SPI_0_BANKLESS_PART0_SIZE = 0x5E0000 (fpga)
SUBSYSTEM_FLASH_AXI_QUAD_SPI_0_BANKLESS_PART1_SIZE = 0x400000 (boot)
SUBSYSTEM_FLASH_AXI_QUAD_SPI_0_BANKLESS_PART2_SIZE = 0x20000 (bootenv)
SUBSYSTEM_FLASH_AXI_QUAD_SPI_0_BANKLESS_PART3_SIZE = 0xB00000 (kernel)
(with this kernel flash address is 0xA00000 (fpga+boot+bootenv) and Kernel size 0xB00000)
U-Boot
Start with petalinux-config -c u-boot
Changes:
CONFIG_ENV_IS_NOWHERE=y
# CONFIG_ENV_IS_IN_SPI_FLASH is not set
# CONFIG_PHY_ATHEROS is not set
# CONFIG_PHY_BROADCOM is not set
# CONFIG_PHY_DAVICOM is not set
# CONFIG_PHY_LXT is not set
# CONFIG_PHY_MICREL_KSZ90X1 is not set
# CONFIG_PHY_MICREL is not set
# CONFIG_PHY_NATSEMI is not set
# CONFIG_PHY_REALTEK is not set
CONFIG_RGMII=y
Content of platform-top.h located in <plnx-proj-root>\project-spec\meta-user\recipes-bsp\u-boot\files:
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#include <configs/microblaze-generic.h>
#include <configs/platform-auto.h>
#define CONFIG_SYS_BOOTM_LEN 0xF000000 |
Device Tree
Content of system-user.dtsi located in <petalinux project directory>\project-spec\meta-user\recipes-bsp\device-tree\files:
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For PetaLinux installation and project creation, follow instructions from:
Config
Start with petalinux-config or petalinux-config --get-hw-description
Changes:
SUBSYSTEM_FLASH_AXI_QUAD_SPI_0_BANKLESS_PART0_SIZE = 0x5E0000 (fpga)
SUBSYSTEM_FLASH_AXI_QUAD_SPI_0_BANKLESS_PART1_SIZE = 0x300000 (boot)
SUBSYSTEM_FLASH_AXI_QUAD_SPI_0_BANKLESS_PART2_SIZE = 0x20000 (bootenv)
SUBSYSTEM_FLASH_AXI_QUAD_SPI_0_BANKLESS_PART3_SIZE = 0xB00000 (kernel)
(Set kernel flash Address to 0x900000 (fpga+boot+bootenv) and Kernel size to 0xB00000)
U-Boot
Start with petalinux-config -c u-boot
Changes:
CONFIG_ENV_IS_NOWHERE=y
# CONFIG_ENV_IS_IN_SPI_FLASH is not set
# CONFIG_PHY_ATHEROS is not set
# CONFIG_PHY_BROADCOM is not set
# CONFIG_PHY_DAVICOM is not set
# CONFIG_PHY_LXT is not set
# CONFIG_PHY_MICREL_KSZ90X1 is not set
# CONFIG_PHY_MICREL is not set
# CONFIG_PHY_NATSEMI is not set
# CONFIG_PHY_REALTEK is not set
CONFIG_RGMII=y
Change platform-top.h:
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#include <configs/platform-auto.h>
#define CONFIG_SYS_BOOTM_LEN 0xF000000
/* Extra U-Boot Env settings */
#define CONFIG_EXTRA_ENV_SETTINGS \
SERIAL_MULTI \
CONSOLE_ARG \
TTYUL0 \
"nc=setenv stdout nc;setenv stdin nc;\0" \
"ethaddr=00:0a:35:00:22:01\0" \
"autoload=no\0" \
"sdbootdev=0\0" \
"clobstart=0x80000000\0" \
"netstart=0x80000000\0" \
"dtbnetstart=0x81e00000\0" \
"netstartaddr=0x81000000\0" \
"bootcmd=sf probe 0 0 0 && sf read ${imageub_addr} ${imageub_flash_addr} ${imageub_flash_size} && echo QSPI: Trying to boot image.ub at ${imageub_addr} && bootm ${imageub_addr}; \0" \
"imageub_addr=0x81000000\0" \
"imageub_flash_addr=0x0900000\0" \
"imageub_flash_size=0x00b00000\0" \
"loadaddr=0x81000000\0" \
"initrd_high=0x0\0" \
"bootsize=0x300000\0" \
"bootstart=0x5e0000\0" \
"boot_img=u-boot-s.bin\0" \
"load_boot=tftpboot ${clobstart} ${boot_img}\0" \
"update_boot=setenv img boot; setenv psize ${bootsize}; setenv installcmd \"install_boot\"; run load_boot test_img; setenv img; setenv psize; setenv installcmd\0" \
"install_boot=sf probe 0 && sf erase ${bootstart} ${bootsize} && " \
"sf write ${clobstart} ${bootstart} ${filesize}\0" \
"bootenvsize=0x20000\0" \
"bootenvstart=0x8e0000\0" \
"eraseenv=sf probe 0 && sf erase ${bootenvstart} ${bootenvsize}\0" \
"kernelsize=0xb00000\0" \
"kernelstart=0x900000\0" \
"kernel_img=image.ub\0" \
"load_kernel=tftpboot ${clobstart} ${kernel_img}\0" \
"update_kernel=setenv img kernel; setenv psize ${kernelsize}; setenv installcmd \"install_kernel\"; run load_kernel test_crc; setenv img; setenv psize; setenv installcmd\0" \
"install_kernel=sf probe 0 && sf erase ${kernelstart} ${kernelsize} && " \
"sf write ${clobstart} ${kernelstart} ${filesize}\0" \
"cp_kernel2ram=sf probe 0 && sf read ${netstart} ${kernelstart} ${kernelsize}\0" \
"fpgasize=0x5e0000\0" \
"fpgastart=0x0\0" \
"fpga_img=system.bit.bin\0" \
"load_fpga=tftpboot ${clobstart} ${fpga_img}\0" \
"update_fpga=setenv img fpga; setenv psize ${fpgasize}; setenv installcmd \"install_fpga\"; run load_fpga test_img; setenv img; setenv psize; setenv installcmd\0" \
"install_fpga=sf probe 0 && sf erase ${fpgastart} ${fpgasize} && " \
"sf write ${clobstart} ${fpgastart} ${filesize}\0" \
"fault=echo ${img} image size is greater than allocated place - partition ${img} is NOT UPDATED\0" \
"test_crc=if imi ${clobstart}; then run test_img; else echo ${img} Bad CRC - ${img} is NOT UPDATED; fi\0" \
"test_img=setenv var \"if test ${filesize} -gt ${psize}\\; then run fault\\; else run ${installcmd}\\; fi\"; run var; setenv var\0" \
"netboot=tftpboot ${netstartaddr} ${kernel_img} && bootm\0" \
"default_bootcmd=bootcmd\0" \
"" |
Device Tree
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/include/ "system-conf.dtsi" / { }; /* QSPI PHY */ &axi_quad_spi_0 { #address-cells = <1>; #size-cells = <0>; flash0: flash@0 { compatible = "jedec,spi-nor"; spi-tx-bus-width=<1>; spi-rx-bus-width=<4>; reg = <0x0>; #address-cells = <1>; #size-cells = <1>; spi-max-frequency = <25000000>; }; }; /* ETH PHY */ &axi_ethernetlite_0 { phy-handle = <&phy0>; mdio { #address-cells = <1>; #size-cells = <0>; phy0: phy@0 { device_type = "ethernet-phy"; reg = <1>; }; }; }; |
Kernel
Start with petalinux-config -c kernel
Changes:
No changes.
Rootfs
Start with petalinux-config -c rootfs
Changes:
# CONFIG_dropbear is not set
# CONFIG_dropbear-dev is not set
# CONFIG_dropbear-dbg is not set
# CONFIG_package-group-core-ssh-dropbear is not set
# CONFIG_packagegroup-core-ssh-dropbear-dev is not set
# CONFIG_packagegroup-core-ssh-dropbear-dbg is not set
# CONFIG_imagefeature-ssh-server-dropbear is not set
optional: to change the password settings at startup look at Adding extra users to the petalinux system.
"Dropbear" is part of the "petalinux-image-minimal" configuration, so changes in the petalinux rootfs will not be applied. To remove "dropbear" anyway, enter the following line in petalinuxbsp.in petalinuxbsp.conf in ..\petalinux\project-spec\meta-user\conf:
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PACKAGE_EXCLUDE += " dropbear dropbear-openssh-sftp-server dropbear-dev dropbear-dbg dropbear-openssh-sftp-server packagegroup-core-ssh-dropbear packagegroup-core-ssh-dropbear-dbg packagegroup-core-ssh-dropbear-dev" |
Applications
No additional application.
Additional Software
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SI5338
File location "<project folder>\misc\Si5338\Si5338-*.slabtimeproj"General documentation how you work with this project will be available on Si5338\Si5338\Si5338-*.slabtimeproj"
General documentation how you work with this project will be available on Si5338
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Appx. A: Change History and Legal Notices
Document Change History
To get content of older revision got to "Change History" of this page and select older document revision number.
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Date | Document Revision | Authors | Description | ||||||
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dateFormat | yyyy-MM-dd | ||||||||
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prefix | v. | ||||||||
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infoType | Modified by | type | Flat
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2021-06-28 | v.37 | John Hartfiel |
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2020-03-25 | cv.35 | John Hartfiel |
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2020-01-21 | v.34 | John Hartfiel |
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2020-01-08 | v.33 | John Hartfiel |
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2019-04-18 | v.32 | John Hartfiel |
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2019-02-22 | v.31 | John Hartfiel |
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2018-09-06 | v.30 | John Hartfiel |
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2018-05-25 | v.28 | John Hartfiel |
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2018-05-08 | v.27 | John Hartfiel |
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2018-04-12 | v.23 | John Hartfiel |
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2018-03-28 | v.22 | John Hartfiel |
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2018-02-13 | v.19 | John Hartfiel |
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2018-01-08 | v.16 | John Hartfiel |
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2017-12-15 | v.15 | John Hartfiel |
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2017-11-07 | v.11 | John Hartfiel |
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2017-10-06 | v.10 | John Hartfiel |
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2017-10-05 | v.8 | John Hartfiel |
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2017-09-11 | v.1 |
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