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titleDesign Revision History

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DateVivadoProject BuiltAuthorsDescription
2019-04-182018.3TE0712-test_board_noprebuilt-vivado_2018.3-build_05_20190418082456.zip
TE0712-test_board-vivado_2018.3-build_05_20190418082240.zip
John Hartfiel
  • MCU depends on EOS now
2019-02-222018.3TE0712-test_board_noprebuilt-vivado_2018.3-build_01_20190222073819.zip
TE0712-test_board-vivado_2018.3-build_01_20190222073754.zip
John Hartfiel
  • TE Script update
  • linux changes
  • SCU rework
  • SI5338 CLKBuilder Pro Project
2018-09-052018.2te0712-test_board-vivado_2018.2-build_03_20180906071356.zip
te0712-test_board_noprebuilt-vivado_2018.2-build_03_20180906071434.zip
John Hartfiel
  • chance block design: qspi clks, clock wizard(REV01 only)
  • change timing constrains
  • add hello_te0712 application
  • new SREC bootloader version
  • change linux device tree
2018-05-252017.4te0712-test_board-vivado_2017.4-build_10_20180525155402.zip
te0712-test_board_noprebuilt-vivado_2017.4-build_10_20180525155555.zip
John Hartfiel
  • solved eth issue for REV01
  • changed design + second design for REV01
2018-04-122017.4te0712-test_board-vivado_2017.4-build_07_20180412081225.zip
te0712-test_board_noprebuilt-vivado_2017.4-build_07_20180412081253.zip
John Hartfiel
  • bugfix constrain file - ETH REFCLK, timing
2018-03-282017.4te0712-test_board-vivado_2017.4-build_07_20180328145151.zip
te0712-test_board_noprebuilt-vivado_2017.4-build_07_20180328145135.zip
John Hartfiel
  • new assembly variant
2018-01-082017.4te0712-test_board-vivado_2017.4-build_02_20180108155712.zip
te0712-test_board_noprebuilt-vivado_2017.4-build_02_20180108155735.zip
John Hartfiel
  • no design changes
  • small constrain changes
2017-12-152017.2te0712-test_board-vivado_2017.2-build_07_20171215172447.zip
te0712-test_board_noprebuilt-vivado_2017.2-build_07_20171215172514.zip
John Hartfiel
  • add SI5338 initialisation with MCS
  • add Ethernet IP
2017-11-072017.2te0712-test_board-vivado_2017.2-build_05_20171107172917.zip
te0712-test_board_noprebuilt-vivado_2017.2-build_05_20171107172939.zip
John Hartfiel
  • add wiki link in Boart Part Files
  • set correct short link for te0712-02-200-2c
2017-10-052017.2te0712-test_board-vivado_2017.2-build_03_20171005082148.zip
te0712-test_board_noprebuilt-vivado_2017.2-build_03_20171005082225.zip
John Hartfiel
  • initial release


Release Notes and Know Issues

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titleKnown Issues

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IssuesDescriptionWorkaroundTo be fixed version
For PCB REV01 only:  prebuilt does not bootThere is a Pullup missing on REV01 I2C SCL, so SI5338 configuration over MCS failsRemove MCSsolved with 20180528 update
For PCB REV01 only: CLK1B is not available onadditional clk is not connected on PCBuse other internal generated CLK, maybe more effort is needed to get ETH runningsolved with 20180528 update

SREC SPI BootLoader default Offset

Default load offset is set to 0x400000Change manually on SDK to 0x5E0000solved with 20180412 update


Requirements

Software

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Notes :

  • list of software which was used to generate the design

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titleHardware Carrier

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Carrier ModelNotes
TE0701
TE0703 used as reference carrier
TE0705
TE0706
TEBA0841



Additional HW Requirements:

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Additional HardwareNotes
USB Cable for JTAG/UARTCheck Carrier Board and Programmer for correct typ
XMOD ProgrammerCarrier Board dependent, only if carrier has no own FTDI



Content

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  • content of the zip file

For general structure and of the reference design, see Project Delivery - Xilinx devices

Design Sources

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TypeLocationNotes
Vivado<design name>/block_design
<design name>/constraints
<design name>/ip_lib
Vivado Project will be generated by TE Scripts
SDK/HSI<design name>/sw_libAdditional Software Template for SDK/HSI and apps_list.csv with settings for HSI
PetaLinux<design name>/os/petalinuxPetaLinux template with current configuration


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Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.

See also:Vivado/SDK/SDSoCXilinx Development Tools

The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.

TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/SDK GUI.  For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality


  1. _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
  2. Press 0 and enter to start "Module Selection Guide"
  3. (optional Win OS) Generate Virtual Drive or use short directory  for the reference design (for example x:\<design name>)
  4. Create Project (follow instruction of the product selection guide), settings file will be configured automatically during this process
    1. optional for manual changes) Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
      Note: Select correct one, see TE Board Part Files
  5. Create HDF and export to prebuilt folder
    1. Run on Vivado TCL: TE::hw_build_design -export_prebuilt
      Note: Script generate design and export files into \prebuilt\hardware\<short dir>. Use GUI is the same, except file export to prebuilt folder
  6. Create Linux (uboot.elf and image.ub) with exported HDF
    1. HDF is exported to "prebuilt\hardware\<short name>"
      Note: HW Export from Vivado GUI create another path as default workspace.
    2. Create Linux images on VM, see PetaLinux KICKstart
      1. Use TE Template from /os/petalinux
        Note: run init_config.sh before you start petalinux config. This will set correct temporary path variable.
        Important Note: Select correct Flash partition offset on petalinux-config: Subsystem Auto HW Settings → Flash Settings,  FPGA+Boot+bootenv=0x900000 (increase automatically generate Boot partition), increas image size to A:, see 54395771
  7. Add Linux files (uboot.elf and image.ub) to prebuilt folder
    1. "prebuilt\os\petalinux\default" or "prebuilt\os\petalinux\<short name>"
      Notes: Scripts select "prebuilt\os\petalinux\<short name>", if exist, otherwise "prebuilt\os\petalinux\default"
  8. (not longer needed manually: This will be done with Step 10.a automatically with newer scripts (2017.4.10) ) Generate UBoot SREC:
    1. Create SDK Project with TE Scripts on Vivado TCL: TE::sw_run_sdk
    2. Create "uboot-dummy" application
      Note: Use Hello World Example
    3. Copy u-boot.elf into "\workspace\sdk\uboot-dummy\Debug"
    4. Open "uboot-dummy" properties → C/C++ Build → Settings and go into Build Steps Tap.
    5. Add to Post-build steps: mb-objcopy -O srec u-boot.elf u-boot.srec
    6. Press Apply or regenerate project
      Note: SREC is generated on "\workspace\sdk\uboot-dummy\Debug\u-boot.srec"
  9. Generate MCS Firmware (optional):
    1. Create SDK Project with TE Scripts on Vivado TCL: TE::sw_run_sdk
    2. Create "SCU" application
      Note: Select MCS Microblaze and SCU Application
    3. Select Release Built
    4. Regenerate App
  10. Generate Programming Files with HSI/SDK
    1. Run on Vivado TCL: TE::sw_run_hsi
      Note: Scripts generate applications and bootable files, which are defined in "sw_lib\apps_list.csv"
    2. (alternative) Start SDK with Vivado GUI or start with TE Scripts on Vivado TCL: TE::sw_run_sdk
      Note: See SDK Projects
  11. Copy "\prebuilt\software\<short name>\srec_spi_bootloader.elf" into  "\firmware\microblaze_0\"
  12. (optional) Copy "\\workspace\sdk\scu\Release\scu.elf" into  "\firmware\microblaze_mcs_0\"
  13. Regenerate Vivado Project or Update Bitfile only with "srec_spi_bootloader.elf" and "scu.elf"

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titleDocument change history.

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DateDocument RevisionAuthorsDescription

Page info
modified-date
modified-date
dateFormatyyyy-MM-dd

Page info
current-version
current-version
prefixv.


Page info
infoTypeModified by
typeFlat

  • small design changes
2019-02-22

v.31

John Hartfiel
  • 2018.3 release (include design reworks)

2018-09-06

Sept 2018

v.30John Hartfiel
  • 2018.2 release

2018-05-25

v.28John Hartfiel
  • Design update

2018-05-08

v.27John Hartfiel
  • Know Issues
  • Documentation

2018-04-12

v.23John Hartfiel
  • Design Update

2018-03-28

v.22John Hartfiel
  • Know Issue for PCB REV01 only
  • Fix typo
  • New assembly variant
2018-02-13v.19John Hartfiel
  • Release 2017.4
2018-01-08v.16John Hartfiel
  • Add SCU source path
2017-12-15v.15John Hartfiel
  • Update Design and Description
2017-11-07v.11John Hartfiel
  • Update Design Files
2017-10-06v.10John Hartfiel
  • small Document Update
2017-10-05

v.8

John Hartfiel
  • Release 2017.2
2017-09-11v.1

Page info
created-user
created-user

  • Initial release
---All

Page info
modified-users
modified-users

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