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Template Revision 2.4 7 - on construction Design Name always "TE Series Name" + Design name, for example "TE0720 Test Board" |
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Date | Vivado | Project Built | Authors | Description |
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2020-01-22 | 2019.2 | TE0712-test_board_noprebuilt-vivado_2019.2-build_3_20200122155446.zip TE0712-test_board-vivado_2019.2-build_3_20200122155355.zip | John Hartfiel | - update for linux user
- new script features
| 2020-01-08 | 2019.2 | TE0712-test_board_noprebuilt-vivado_2019.2-build_2_20200108161124.zip TE0712-test_board-vivado_2019.2-build_2_20200108155510.zip | John Hartfiel | - 2019.2 update
- Vitis support
| 2019-04-18 | 2018.3 | TE0712-test_board_noprebuilt-vivado_2018.3-build_05_20190418082456.zip TE0712-test_board-vivado_2018.3-build_05_20190418082240.zip | John Hartfiel | | 2019-02-22 | 2018.3 | TE0712-test_board_noprebuilt-vivado_2018.3-build_01_20190222073819.zip TE0712-test_board-vivado_2018.3-build_01_20190222073754.zip | John Hartfiel | - TE Script update
- linux changes
- SCU rework
- SI5338 CLKBuilder Pro Project
| 2018-09-05 | 2018.2 | te0712-test_board-vivado_2018.2-build_03_20180906071356.zip te0712-test_board_noprebuilt-vivado_2018.2-build_03_20180906071434.zip | John Hartfiel | - chance block design: qspi clks, clock wizard(REV01 only)
- change timing constrains
- add hello_te0712 application
- new SREC bootloader version
- change linux device tree
| 2018-05-25 | 2017.4 | te0712-test_board-vivado_2017.4-build_10_20180525155402.zip te0712-test_board_noprebuilt-vivado_2017.4-build_10_20180525155555.zip | John Hartfiel | - solved eth issue for REV01
- changed design + second design for REV01
| 2018-04-12 | 2017.4 | te0712-test_board-vivado_2017.4-build_07_20180412081225.zip te0712-test_board_noprebuilt-vivado_2017.4-build_07_20180412081253.zip | John Hartfiel | - bugfix constrain file - ETH REFCLK, timing
| 2018-03-28 | 2017.4 | te0712-test_board-vivado_2017.4-build_07_20180328145151.zip te0712-test_board_noprebuilt-vivado_2017.4-build_07_20180328145135.zip | John Hartfiel | | 2018-01-08 | 2017.4 | te0712-test_board-vivado_2017.4-build_02_20180108155712.zip te0712-test_board_noprebuilt-vivado_2017.4-build_02_20180108155735.zip | John Hartfiel | - no design changes
- small constrain changes
| 2017-12-15 | 2017.2 | te0712-test_board-vivado_2017.2-build_07_20171215172447.zip te0712-test_board_noprebuilt-vivado_2017.2-build_07_20171215172514.zip | John Hartfiel | - add SI5338 initialisation with MCS
- add Ethernet IP
| 2017-11-07 | 2017.2 | te0712-test_board-vivado_2017.2-build_05_20171107172917.zip te0712-test_board_noprebuilt-vivado_2017.2-build_05_20171107172939.zip | John Hartfiel | - add wiki link in Boart Part Files
- set correct short link for te0712-02-200-2c
| 2017-10-05 | 2017.2 | te0712-test_board-vivado_2017.2-build_03_20171005082148.zip te0712-test_board_noprebuilt-vivado_2017.2-build_03_20171005082225.zip | John Hartfiel | |
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Xilinx documentation for programming and debugging: Vivado/SDK/SDSoC-Xilinx Software Programming and Debugging
QSPI
Get prebuilt boot binaries
- _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell
- Press 0 and enter to start "Module Selection Guide"
- Select assembly version
- Validate selection
- Select Create and open delivery binary folder
Note: Folder (<project foler>/_binaries_<Artikel Name>) with subfolder (boot_<app name>) for different applications will be generated
QSPI
- Connect JTAG and power on Connect JTAG and power on PCB
- (if not done) Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd" or open with "vivado_open_project_guimode.cmd", if generated.
- Type on Vivado Console: TE::pr_program_flash_mcsfile -swapp u-boot
Note: Alternative use SDK or setup Flash on Vivado manually
optional "TE::pr_program_flash_binfile -swapp hello_te0712" possible - Reboot (if not done automatically)
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For SDK project creation, follow instructions from:
Vitis
Application
Template location: ./sw_lib/sw_apps/
scu
MCS Firmware to configure SI5338 and Reset System.
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---------------------------------------------------------- FPGA Example scuMCS Firmware to configure SI5338 and Reset System. srec_spi_bootloaderTE modified 2019.2 SREC Bootloader to load app or second bootloader from flash into DDR Descriptions: - Modified Files: blconfig.h, bootloader.c
- Changes:
- Add some console outputs and changed bootloader read address.
- Add bugfix for 2018.2 qspi flash
xilisf_v5_11TE modified 2019.2 xilisf_v5_11 - Changed default Flash type to 5.
---------------------------------------------------------- Zynq Example: zynq_fsblTE modified 2019.2 FSBL General: Module Specific: - Add Files: all TE Files start with te_*
- READ MAC from EEPROM and make Address accessible by UBOOT (need copy defines on uboot platform-top.h)
- CPLD access
- Read CPLD Firmware and SoC Type
- Configure Marvell PHY
zynq_fsbl_flashTE modified 2019.2 FSBL General: - Modified Files: main.c
- General Changes:
- Display FSBL Banner
- Set FSBL Boot Mode to JTAG
- Disable Memory initialisation
ZynqMP Example: ---------------------------------------------------------- zynqmp_fsblTE modified 2019.2 FSBL General: - Modified Files: xfsbl_main.c, xfsbl_hooks.h/.c, xfsbl_board.h/.c(search for 'TE Mod' on source code)
- Add Files: te_xfsbl_hooks.h/.c (for hooks and board)\n\
- General Changes:
- Display FSBL Banner and Device Name
Module Specific: - Add Files: all TE Files start with te_*
- Si5338 Configuration
- ETH+OTG Reset over MIO
zynqmp_fsbl_flashTE modified 2019.2 FSBL General: - Modified Files: xfsbl_initialisation.c, xfsbl_hw.h, xfsbl_handoff.c, xfsbl_main.c
- General Changes:
- Display FSBL Banner
- Set FSBL Boot Mode to JTAG
- Disable Memory initialisation
zynqmp_pmufwXilinx default PMU firmware. ---------------------------------------------------------- General Example: hello_te0820Hello TE0820 is a Xilinx Hello World example as endless loop instead of one console output. u-bootU-Boot.elf is generated with PetaLinux. SDK/HSI is used to generate Boot.bin. |
Template location: ./sw_lib/sw_apps/
scu
MCS Firmware to configure SI5338 and Reset System.
srec_spi_bootloader
TE modified 2019.2 SREC
Bootloader to load app or second bootloader from flash into DDR
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Hello TE0712 is a Xilinx Hello World example as endless loop instead of one console output.
u-boot
U-Boot.elf is generated with PetaLinux. SDK/HSI is used to generate u-boot.srec. Vivado to generate *.mcs
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Change platform-top.h:
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#include <configs/platform-auto.h>
#define CONFIG_SYS_BOOTM_LEN 0xF000000
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Device Tree
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/include/ "system-conf.dtsi"
/ {
};
/* QSPI PHY */
&axi_quad_spi_0 {
#address-cells = <1>;
#size-cells = <0>;
flash0: flash@0 {
compatible = "jedec,spi-nor";
spi-tx-bus-width=<1>;
spi-rx-bus-width=<4>;
reg = <0x0>;
#address-cells = <1>;
#size-cells = <1>;
spi-max-frequency = <25000000>;
};
};
/* ETH PHY */
&axi_ethernetlite_0 {
phy-handle = <&phy0>;
mdio {
#address-cells = <1>;
#size-cells = <0>;
phy0: phy@0 {
device_type = "ethernet-phy";
reg = <1>;
};
};
};
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Date | Document Revision | Authors | Description |
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| - update scripts, new features and linux support
| 2020-01-08 | v.33 | John Hartfiel | | 2019-04-18 | v.32 | John Hartfiel | | 2019-02-22 | v.31 | John Hartfiel | - 2018.3 release (include design reworks)
| | v.30 | John Hartfiel | | 2018-05-25 | v.28 | John Hartfiel | | 2018-05-08 | v.27 | John Hartfiel | | 2018-04-12 | v.23 | John Hartfiel | | 2018-03-28 | v.22 | John Hartfiel | - Know Issue for PCB REV01 only
- Fix typo
- New assembly variant
| 2018-02-13 | v.19 | John Hartfiel | | 2018-01-08 | v.16 | John Hartfiel | | 2017-12-15 | v.15 | John Hartfiel | - Update Design and Description
| 2017-11-07 | v.11 | John Hartfiel | | 2017-10-06 | v.10 | John Hartfiel | | 2017-10-05 | v.8 | John Hartfiel | | 2017-09-11 | v.1 | | | --- | All | Page info |
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