Page History

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• PetaLinux
• MicroBlaze
• SREC
• I2C
• Flash
• MIG
• FMeter

Revision History

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Reference Design is available on:

• TE0000 TE0712 Reference Design Download Area

Design Flow

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Basic Design Steps
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1. Open Serial Console (e.g. putty)
   
   1. Speed: 9600
   2. COM Port: Win OS, see device manager, Linux OS see  dmesg |grep tty  (UART is *USB1)
2. Linux Console:
   Note: Wait until Linux boot finished For Linux Login use:
   
   1. User Name: root
   2. Password: root

MGT Reference CLK Counter: 

System Design - Vivado

1. Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder).
   1. Set radix from VIO signals to unsigned integer.
      Note: Frequency Counter is inaccurate and displayed unit is Hz
      

MGT CLK is configured to 125MHz by default, second MIG output CLK is 50MHz.

Image Added

System Design - Vivado

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Description of Block Design, Constrains...

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Block Design

 Image Added

Constrains

Basic module constrains

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Changed default Flash Typ to 5.

U-Boot

U-Boot.elf is generated with PetaLinux. SDK/HSI is used to generate u-boot.srec. Vivado to generate *.mcs

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Description currently not available.

Config

• Set Uboot partition size to 0x4E0000:kernel flash Address to 0x900000:
  (--> Subsystem Auto Hardware Settings --> Flash Settings)
  
  • SUBSYSTEM_FLASH_AXI_QUAD_SPI_0_BANKLESS_PART0_SIZE = 0x400000
  • SUBSYSTEM_FLASH_AXI_QUAD_SPI_0_BANKLESS_PART1_SIZE
    (--> Subsystem Auto Hardware Settings --> Flash Settings)= 0x4E0000
  • SUBSYSTEM_FLASH_AXI_QUAD_SPI_0_BANKLESS_PART2_SIZE =   0x20000

U-Boot

No changes.

Device Tree

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