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titleDesign Revision History

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DateVivadoProject BuiltAuthorsDescription
2018-12-10122018.2TE0728-test_board-vivado_2018.2-build_03_20181212131950.zip
TE0728-test_board_noprebuilt-vivado_2018.2-build_03_20181212134902.zip2018.2
John Hartfiel
  • rework board part files
  • rework petalinux device tree, driver
  • small changes on xdc
2017-10-062017.2TE0728-test_board_noprebuilt-vivado_2017.2-build_03_20171006103655.zip
TE0728-test_board-vivado_2017.2-build_03_20171006103634.zip
John Hartfiel
  • initial release


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titleKnown Issues

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IssuesDescriptionWorkaroundTo be fixed version
Wrong UBoot ETH PHY AddressPHY Address is not set correctly for UBoot---solved with 2018-12--12 update

Linux Message: "macb ... .ethernet eth...: unable to generate target frequency: 25000000 Hz"

This can be ignored, ETH works.------


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For general structure and of the reference design, see Project Delivery - Xilinx devices

Design Sources

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titleDesign sources

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TypeLocationNotes
Vivado<design name>/block_design
<design name>/constraints
<design name>/ip_lib
Vivado Project will be generated by TE Scripts
SDK/HSI<design name>/sw_libAdditional Software Template for SDK/HSI and apps_list.csv with settings for HSI
PetaLinux<design name>/os/petalinuxPetaLinux template with current configuration


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Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.

See also:

The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.

TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/SDK GUI.  For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality

 

  1. _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
  2. Press 0 and enter for minimum setup
  3. (optional Win OS) Generate Virtual Drive or use short directory  for the reference design (for example x:\<design name>)
  4. Create Project
    1. Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
      Note: Select correct one, see TE Board Part Files
  5. Create HDF and export to prebuilt folder
    1. Run on Vivado TCL: TE::hw_build_design -export_prebuilt
      Note: Script generate design and export files into \prebuilt\hardware\<short dir>. Use GUI is the same, except file export to prebuilt folder
  6. Create Linux (uboot.elf and image.ub) with exported HDF
    1. HDF is exported to "prebuilt\hardware\<short name>"
      Note: HW Export from Vivado GUI create another path as default workspace.
    2. Create Linux images on VM, see PetaLinux KICKstart
      1. Use TE Template from /os/petalinux
  7. Add Linux files (uboot.elf and image.ub) to prebuilt folder
    1. "prebuilt\os\petalinux\default" or "prebuilt\os\petalinux\<short name>"
      Notes: Scripts select "prebuilt\os\petalinux\<short name>", if exist, otherwise "prebuilt\os\petalinux\default"
  8. Generate Programming Files with HSI/SDK
    1. Run on Vivado TCL: TE::sw_run_hsi
      Note: Scripts generate applications and bootable files, which are defined in "sw_lib\apps_list.csv"
    2. (alternative) Start SDK with Vivado GUI or start with TE Scripts on Vivado TCL: TE::sw_run_sdk
      Note: See SDK Projects

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Scroll Title
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titlePS Interfaces

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TypeNote
DDR---
QSPIMIO
CAN1MIO
ETH0EMIO
ETH1EMIO
SD0MIO
UART1MIO
I2C0MIO
SPI1MIO
CAN1MIO
GPIOMIO
WDTEMIO
TTC0..1EMIO

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Constrains

Basic module constrains

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DateDocument RevisionAuthorsDescription

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  • Release 2018.2  (working in process)2
  • Design and Documentation is changed

v.10John Hartfiel
  • Release 2017.2

2017-09-11v.1

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  • Initial release
 All

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