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Template Revision 2.1 8 - on construction

Design Name always "TE Series Name" + Design name, for example "TE0720 Test Board"

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Notes :

  • Add basic key futures, which can be tested with the design


Excerpt
  • Vitis/Vivado 2019.2
  • PetaLinux
  • SD
  • ETH (MAC from EEPROM)
  • USB
  • I2C
  • RTC
  • FMeterSI5338
  • Initialisation with FSBLModified FSBL for SI5338 programming
  • Special FSBL for QSPI programming

Revision History

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Notes :

  • add every update file on the download
  • add design changes on description

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2017_noprebuilt2017
DateVivadoProject BuiltAuthorsDescription
20182020-0903-3020192018.2TE0745-test_board_noprebuilt-vivado_20182019.2-build_048_2019091810354520200330083452.zip
TE0745-test_board_noprebuilt-vivado_20182019.2-build_048_2019091810353120200330083503.zip
John Hartfiel
  • BUGFIX in TE0745-02-45-3EA board parts
2018-11-262018
  • 2019.2
TE0745-test_board-
  • update
  • FSBL rework, SI5338 Project with Clock Builder pro
  • device tree update
  • Vitis support
  • new assembly variants
2018-09-20192018.2TE0745-test_board_noprebuilt-vivado_2018.2-build_0304_2018112611513120190918103545.zip
TE0745-test_board_noprebuilt-vivado_2018.2-build_0304_2018112611532020190918103531.zip
John Hartfiel
  • Rework Board Part Files
  • New assembly versions
  • Rework BD Design
  • add init.sh scripts
2017-10-23
  • BUGFIX in TE0745-02-45-3EA board parts
2018-11-262018.2

TE0745-test_board

-vivado_

2018.2-build_03_20181126115131.zip
TE0745-test_board_noprebuilt-vivado_2018.2-build_03_20181126115320.zip

John Hartfiel
  • Rework Board Part Files
  • New assembly versions
  • Rework BD Design
  • add init.sh scripts
2017-10-232017.2TE0745-test_board_noprebuilt-vivado_2017.2-build_05_20171023171903.zip
TE0745-test_board-vivado_2017.2-build_05_20171023171855.zip
John Hartfiel
  • initial release


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SoftwareVersionNote
VivadoVitis20182019.2needed
SDK2018.2needed
PetaLinux2018, Vivado is included into Vitis installation
PetaLinux2019.2neededSI5338 Clock Builder
SI ClockBuilder Pro---optional


Hardware

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Notes :

  • list of software which was used to generate the design

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3EA
Module ModelBoard Part Short NamePCB Revision SupportDDRQSPI FlashEMMCOthersNotes
TE0745-02-30-1I1I    30_1i01,021GB32MB*xc7z030 has lower MGT count_1gb    REV02|REV01   1GB      32MB       NA         NA         smaller FPGA has less MGTs
TE0745-02-30-2IA2IA   30_2i01,021GB64MB*xc7z030 has lower MGT count_1gb    REV02|REV01   1GB      32MB       NA         NA         smaller FPGA has less MGTs
TE0745-02-35-1C1C    35_1c01,021GB32MB_1gb    REV02|REV01   1GB      32MB       NA         NA         
TE0745-02-45-2I2I    45_2i01,021GB32MB_1gb    REV02|REV01   1GB      32MB       NA         NA         
TE0745-02-45-2IA2IA   45_2i01,021GB64MB_1gb    REV02|REV01   1GB      32MB       NA         NA         
TE0745-02-45-1C1C    45_1c01,021GB32MB_1gb    REV02|REV01   1GB      32MB       NA         NA         
TE0745-02-45-1CA1CA   45_1c01,021GB64MB_1gb    REV02|REV01   1GB      32MB       NA         NA         
TE0745-02-45-3EA   45_3e01,021GB64MB

Design supports following carriers:

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titleHardware Carrier

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Additional HW Requirements:

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Content

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  • content of the zip file

For general structure and of the reference design, see Project Delivery - Xilinx devices

...

_1gb    REV02|REV01   1GB      32MB       NA         NA         
TE0745-02-93E11-A  45_3e_1gb    REV02         1GB      32MB       NA         NA         
TE0745-02-92I11-F  45_2i_ff_1gb REV02         1GB      32MB       NA         NA         
TE0745-02-92I11-A  45_2i_1gb    REV02         1GB      32MB       NA         NA         
TE0745-02-91C11-A  45_1c_1gb    REV02         1GB      32MB       NA         NA         
TE0745-02-81C11-A  35_1c_1gb    REV02         1GB      32MB       NA         NA         
TE0745-02-72I11-A  30_2i_1gb    REV02         1GB      32MB       NA         NA         smaller FPGA has less MGTs
TE0745-02-71I11-A  30_1i_1gb    REV02         1GB      32MB       NA         NA         smaller FPGA has less MGTs
TE0745-02-71I11-AK 30_1i_1gb    REV02         1GB      32MB       NA         NA         smaller FPGA has less MGTs


Design supports following carriers:

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TypeCarrier ModelLocationNotes
Vivado<design name>/block_design
<design name>/constraints
<design name>/ip_lib
Vivado Project will be generated by TE Scripts
SDK/HSI<design name>/sw_libAdditional Software Template for SDK/HSI and apps_list.csv with settings for HSI
PetaLinux<design name>/os/petalinuxPetaLinux template with current configuration

Additional Sources

TEB0745


Additional HW Requirements:

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titleAdditional design sourcesHardware

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TypeAdditional HardwareLocationNotes
SI5338<design name>/misc/Si5338Si5338 Project with current PLL Configuration
init.sh<design name>/misc/sdAdditional Initialization Script for Linux

Prebuilt

USB Cable for JTAG/UARTCheck Carrier Board and Programmer for correct typ
XMOD ProgrammerCarrier Board dependent, only if carrier has no own FTDI


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Notes :

  • prebuilt files
  • Template Table:content of the zip file


For general structure and of the reference design, see Project Delivery - Xilinx devices

Design Sources

PFPrebuilt filesConverted Software Application for MicroBlaze Processor Systems
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Design sources

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File
Type
File-Extension
Location
Description

SREC-File

*.srec

Notes
BIF-File*.bifFile with description to generate Bin-FileBIN-File*.binFlash Configuration File with Boot-Image (Zynq-FPGAs)BIT-File*.bitFPGA (PL Part) Configuration FileDebugProbes-File*.ltxDefinition File for Vivado/Vivado Labtools Debugging Interface

Debian SD-Image

*.img

Debian Image for SD-Card

Diverse Reports---Report files in different formatsHardware-Platform-Specification-Files*.hdfExported Vivado Hardware Specification for SDK/HSI and PetaLinuxLabTools Project-File*.lprVivado Labtools Project File

MCS-File

*.mcs

Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)

MMI-File

*.mmi

File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)

OS-Image*.ubImage with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)Software-Application-File*.elfSoftware Application for Zynq or MicroBlaze Processor Systems
Vivado<design name>/block_design
<design name>/constraints
<design name>/ip_lib
Vivado Project will be generated by TE Scripts
SDK/HSI<design name>/sw_libAdditional Software Template for Vitis and apps_list.csv with settings automatically for Vitis app generation
PetaLinux<design name>/os/petalinuxPetaLinux template with current configuration


Additional Sources

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TypeLocationNotes
SI5338<design name>/misc/Si5338Si5338 Project with current PLL Configuration
init.sh<design name>/misc/sdAdditional Initialization Script for Linux


Prebuilt

(only on ZIP with prebult content)
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  • prebuilt files
  • Template Table:

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      File

      File-Extension

      Description

      BIF-File*.bifFile with description to generate Bin-File
      BIN-File*.binFlash Configuration File with Boot-Image (Zynq-FPGAs)
      BIT-File*.bitFPGA (PL Part) Configuration File
      DebugProbes-File*.ltxDefinition File for Vivado/Vivado Labtools Debugging Interface

      Debian SD-Image

      *.img

      Debian Image for SD-Card

      Diverse Reports---Report files in different formats
      Hardware-Platform-Specification-Files*.
hdf
    • xsaExported Vivado Hardware Specification for
SDK/HSI
    • Vitis and PetaLinux
      LabTools Project-File*.lprVivado Labtools Project File
OS
    • MCS-

Image
    • File

      *.

ubImage with Linux Kernel (On Petalinux optional with Devicetree and RAM-

Constrains

Basic module constrains

Code Block
languageruby
title_i_bitgen_common
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property CONFIG_VOLTAGE 1.8 [current_design]
set_property CFGBVS GND [current_design]

Design specific constrain

No additional constrains.

Software Design - SDK/HSI

HTML
<!--
optional chapter
separate sections for different apps
  -->

For SDK project creation, follow instructions from:

SDK Projects

Application

Template location: ./sw_lib/sw_apps/

zynq_fsbl

TE modified 2018.2 FSBL

Changes:

  • Si5338 Configuration see fsbl_hooks.c
  • Add register_map.h, si5338.c, si5338.h

zynq_fsbl_flash

TE modified 2018.2 FSBL

Changes:

  • Set FSBL Boot Mode to JTAG
  • Disable Memory initialisation

hello_te0745

Hello TE0745 is a Xilinx Hello World example as endless loop instead of one console output.

u-boot

U-Boot.elf is generated with PetaLinux. SDK/HSI is used to generate Boot.bin.

Software Design -  PetaLinux

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  • optional chapter separate

  • sections for linux

  • Add "No changes." or "Activate: and add List"

For PetaLinux installation and  project creation, follow instructions from:

Config

No changes.

U-Boot

No changes.

Device Tree

Code Block
languagejs
/include/ "system-conf.dtsi" / { };
    • mcs

      Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)

      MMI-File

      *.mmi

      File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)

      OS-Image*.ubImage with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)
      Software-Application-File*.elfSoftware Application for Zynq or MicroBlaze Processor Systems

Download

Reference Design is only usable with the specified Vivado/SDK/PetaLinux/SDx version. Do never use different Versions of Xilinx Software for the same Project.

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Reference Design is available on:

Design Flow

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Notes :
  • Basic Design Steps

  • Add/ Remove project specific description

Note

Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first lunch.

Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.

See also:

The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.

TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/SDK GUI.  For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality

  1. _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
    Image Removed
  2. Press 0 and enter for minimum setup
  3. (optional Win OS) Generate Virtual Drive or use short directory  for the reference design (for example x:\<design name>)
  4. Create Project
    1. Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
      Note: Select correct one, see TE Board Part Files
  5. Create HDF and export to prebuilt folder
    1. Run on Vivado TCL: TE::hw_build_design -export_prebuilt
      Note: Script generate design and export files into \prebuilt\hardware\<short dir>. Use GUI is the same, except file export to prebuilt folder
  6. Create Linux (uboot.elf and image.ub) with exported HDF
    1. HDF is exported to "prebuilt\hardware\<short name>"
      Note: HW Export from Vivado GUI create another path as default workspace.
    2. Create Linux images on VM, see PetaLinux KICKstart
      1. Use TE Template from /os/petalinux
  7. Add Linux files (uboot.elf and image.ub) to prebuilt folder
    1. "prebuilt\os\petalinux\default" or "prebuilt\os\petalinux\<short name>"
      Notes: Scripts select "prebuilt\os\petalinux\<short name>", if exist, otherwise "prebuilt\os\petalinux\default"
  8. Generate Programming Files with HSI/SDK
    1. Run on Vivado TCL: TE::sw_run_hsi
      Note: Scripts generate applications and bootable files, which are defined in "sw_lib\apps_list.csv"
    2. (alternative) Start SDK with Vivado GUI or start with TE Scripts on Vivado TCL: TE::sw_run_sdk
      Note: See SDK Projects

Launch

Programming

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Note:

  • Programming and Startup procedure
Note

Check Module and Carrier TRMs for proper HW configuration before you try any design.

Xilinx documentation for programming and debugging: Vivado/SDK/SDSoC-Xilinx Software Programming and Debugging

QSPI

Optional for Boot.bin on QSPI Flash and image.ub on SD.

  1. Connect JTAG and power on carrier with module
  2. Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"
  3. Type on Vivado TCL Console: TE::pr_program_flash_binfile -swapp u-boot
    Note: To program with SDK/Vivado GUI, use special FSBL (zynqmp_fsbl_flash) on setup
             optional "TE::pr_program_flash_binfile -swapp hello_te0745" possible
  4. Copy image.ub and init.sh (optional on /misc/sd) on SD-Card
    • For correct prebuilt file location, see <design_name>/prebuilt/readme_file_location.txt
  5. Insert SD-Card

SD

  1. Copy image.ub,Boot.bin and init.sh (optional on /misc/sd) on SD-Card.
    • For correct prebuilt file location, see <design_name>/prebuilt/readme_file_location.txt
  2. Set Boot Mode to SD-Boot.
    • Depends on Carrier, see carrier TRM.
  3. Insert SD-Card in SD-Slot.

JTAG

Not used on this Example.

Usage

  1. Prepare HW like described on section Programming
  2. Connect UART USB (most cases same as JTAG)
  3. Select SD Card as Boot Mode
    Note: See TRM of the Carrier and Module.
  4. Power On PCB
    Note: 1. Zynq Boot ROM loads FSBL from SD into OCM, 2. FSBL loads U-boot from SD into DDR and program PL part, 3. U-boot load Linux from SD into DDR

Linux

  1. Open Serial Console (e.g. putty)
    1. Speed: 115200
    2. COM Port: Win OS, see device manager, Linux OS see  dmesg |grep tty  (UART is *USB1)
  2. Linux Console:
    Note: Wait until Linux boot finished For Linux Login use:
    1. User Name: root
    2. Password: root
  3. You can use Linux shell now.
    1. I2C 0 Bus type: i2cdetect -y -r 0
    2. RTC check: dmesg | grep rtc
    3. ETH0 works with udhcpc
    4. USB type  "lsusb" or connect USB2.0 device
    5. (optional) init.sh scripts: Scripts will enable SFP interface after linux booting, if file is copied on SD

Vivado HW Manager

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Note:

  • Add picture of HW Manager

  • add notes for the signal either groups or topics, for example:

    Control:

    • add controllable IOs with short notes..

    Monitoring:

    • add short notes for signals which will be monitored only

    SI5338_CLK0 Counter: 

    Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder).Set radix from VIO signals to unsigned integer.Note: Frequency Counter is inaccurate and displayed unit is Hz
  • Monitoring:

    • SI5338 CLKs: 

      • Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder).Set radix from VIO signals to unsigned integer.
        Note: Frequency Counter is inaccurate and displayed unit is Hz
        , SI5338 CLK(0 and 3) are configured to 125MHz by default.
Scroll Title
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titleVivado Hardware Manager

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System Design - Vivado

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Note:

  • Description of Block Design, Constrains... BD Pictures from Export...

Block Design

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titleBlock Design

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*clk3 is not available on the smallest SOC (xc7z030)

PS Interfaces

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Note:

  • optional for Zynq / ZynqMP only

  • add basic PS configuration

Activated interfaces:

...

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titlePS Interfaces

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    • SREC-File

      *.srec

      Converted Software Application for MicroBlaze Processor Systems




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File

File-Extension

Description

BIF-File*.bifFile with description to generate Bin-File
BIN-File*.binFlash Configuration File with Boot-Image (Zynq-FPGAs)
BIT-File*.bitFPGA (PL Part) Configuration File
DebugProbes-File*.ltxDefinition File for Vivado/Vivado Labtools Debugging Interface
Diverse Reports---Report files in different formats
Hardware-Platform-Specification-Files*.xsaExported Vivado Hardware Specification for Vitis and PetaLinux
LabTools Project-File*.lprVivado Labtools Project File
OS-Image*.ubImage with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)
Software-Application-File*.elfSoftware Application for Zynq or MicroBlaze Processor Systems


Download

Reference Design is only usable with the specified Vivado/SDK/PetaLinux/SDx version. Do never use different Versions of Xilinx Software for the same Project.

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Reference Design is available on:

Design Flow

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Notes :
  • Basic Design Steps

  • Add/ Remove project specific description


Note

Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first lunch.

Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.

See also:

The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.

TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/SDK GUI.  For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality


  1. _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
    Image Added
  2. Press 0 and enter to start "Module Selection Guide"
  3. (optional Win OS) Generate Virtual Drive or use short directory  for the reference design (for example x:\<design name>)
  4. Create Project (follow instruction of the product selection guide), settings file will be configured automatically during this process)
    1. (optional for manual changes) Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
      Note: Select correct one, see TE Board Part Files
  5. Create XSA and export to prebuilt folder
    1. Run on Vivado TCL: TE::hw_build_design -export_prebuilt
      Note: Script generate design and export files into \prebuilt\hardware\<short dir>. Use GUI is the same, except file export to prebuilt folder
  6. Create Linux (uboot.elf and image.ub) with exported XSA
    1. XSA is exported to "prebuilt\hardware\<short name>"
      Note: HW Export from Vivado GUI create another path as default workspace.
    2. Create Linux images on VM, see PetaLinux KICKstart
      1. Use TE Template from /os/petalinux
  7. Add Linux files (uboot.elf and image.ub) to prebuilt folder
    1. "prebuilt\os\petalinux\<ddr size>" or "prebuilt\os\petalinux\<short name>"
  8. Generate Programming Files with Vitis
    1. Run on Vivado TCL: TE::sw_run_vitis -all
      Note: Scripts generate applications and bootable files, which are defined in "sw_lib\apps_list.csv"
    2. (alternative) Start SDK with Vivado GUI or start with TE Scripts on Vivado TCL: TE::sw_run_vitis
      Note:  TCL scripts generate also platform project, this must be done manuelly in case GUI is used. See Vitis

Launch

Programming

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Note:

  • Programming and Startup procedure


Note

Check Module and Carrier TRMs for proper HW configuration before you try any design.

Xilinx documentation for programming and debugging: Vivado/SDK/SDSoC-Xilinx Software Programming and Debugging

Get prebuilt boot binaries

  1. _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell
  2. Press 0 and enter to start "Module Selection Guide"
    1. Select assembly version
    2. Validate selection
    3. Select Create and open delivery binary folder
      Note: Folder (<project foler>/_binaries_<Artikel Name>) with subfolder (boot_<app name>) for different applications will be generated

QSPI

Optional for Boot.bin on QSPI Flash and image.ub on SD.

  1. Connect JTAG and power on carrier with module
  2. Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"
  3. Type on Vivado TCL Console: TE::pr_program_flash -swapp u-boot
    Note: To program with SDK/Vivado GUI, use special FSBL (zynqmp_fsbl_flash) on setup
             optional "TE::pr_program_flash -swapp hello_te0745" possible
  4. Copy image.ub and init.sh (optional on /misc/sd) on SD-Card
    • use files from (<project foler>/_binaries_<Articel Name>)/boot_linux from generated binary folder,see: Get prebuilt boot binaries
    • or use prebuilt file location, see <design_name>/prebuilt/readme_file_location.txt
  5. Insert SD-Card


SD

  1. Copy image.ub,Boot.bin and init.sh (optional on /misc/sd) on SD-Card.
    • use files from (<project foler>/_binaries_<Articel Name>)/boot_linux from generated binary folder,see: Get prebuilt boot binaries
    • or use prebuilt file location, see <design_name>/prebuilt/readme_file_location.txt
  2. Set Boot Mode to SD-Boot.
    • Depends on Carrier, see carrier TRM.
  3. Insert SD-Card in SD-Slot.

JTAG

Not used on this Example.

Usage

  1. Prepare HW like described on section Programming
  2. Connect UART USB (most cases same as JTAG)
  3. Select SD Card as Boot Mode
    Note: See TRM of the Carrier and Module.
  4. Power On PCB
    Note: 1. Zynq Boot ROM loads FSBL from SD into OCM, 2. FSBL loads U-boot from SD into DDR and program PL part, 3. U-boot load Linux from SD into DDR

Linux

  1. Open Serial Console (e.g. putty)
    1. Speed: 115200
    2. COM Port: Win OS, see device manager, Linux OS see  dmesg |grep tty  (UART is *USB1)
  2. Linux Console:
    Note: Wait until Linux boot finished For Linux Login use:
    1. User Name: root
    2. Password: root
  3. You can use Linux shell now.
    1. I2C 0 Bus type: i2cdetect -y -r 0
    2. RTC check: dmesg | grep rtc
    3. ETH0 works with udhcpc
    4. USB type  "lsusb" or connect USB2.0 device
    5. (optional) init.sh scripts: Scripts will enable SFP interface after linux booting, if file is copied on SD

Vivado HW Manager

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Note:

  • Add picture of HW Manager

  • add notes for the signal either groups or topics, for example:

    Control:

    • add controllable IOs with short notes..

    Monitoring:

    • add short notes for signals which will be monitored only

    SI5338_CLK0 Counter: 

    Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder).Set radix from VIO signals to unsigned integer.Note: Frequency Counter is inaccurate and displayed unit is Hz
  • Monitoring:

    • SI5338 CLKs: 

      • Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder).Set radix from VIO signals to unsigned integer.
        Note: Frequency Counter is inaccurate and displayed unit is Hz
        , SI5338 CLK(0 and 3) are configured to 125MHz by default.
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System Design - Vivado

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Note:

  • Description of Block Design, Constrains... BD Pictures from Export...

Block Design

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*clk3 is not available on the smallest SOC (xc7z030)


PS Interfaces

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Note:

  • optional for Zynq / ZynqMP only

  • add basic PS configuration

Activated interfaces:

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titlePS Interfaces

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TypeNote
DDR
QSPIMIO
ETH0MIO
USB0MIO
SD0MIO
UART0MIO
I2C0MIO
GPIOMIO
ETH0 ResetMIO
USB0 ResetMIO
I2C0 ResetMIO
TTC0..1EMIO
SWDT0EMIO


Constrains

Basic module constrains

Code Block
languageruby
title_i_bitgen_common
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property CONFIG_VOLTAGE 1.8 [current_design]
set_property CFGBVS GND [current_design]

Design specific constrain

Code Block
languageruby
title_i_timing.xdc
set_false_path -from [get_clocks clk_fpga_0] -to [get_clocks si5338_clk0_clk_p]
set_false_path -from [get_clocks clk_fpga_0] -to [get_clocks si5338_clk3_clk_p]
set_false_path -from [get_clocks si5338_clk0_clk_p] -to [get_clocks clk_fpga_0]
set_false_path -from [get_clocks si5338_clk3_clk_p] -to [get_clocks clk_fpga_0]

Software Design - Vitis

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Note:
  • optional chapter separate

  • sections for different apps

For SDK project creation, follow instructions from:

Vitis

Application

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----------------------------------------------------------

FPGA Example

scu

MCS Firmware to configure SI5338 and Reset System.

srec_spi_bootloader

TE modified 2019.2 SREC

Bootloader to load app or second bootloader from flash into DDR

Descriptions:

  • Modified Files: blconfig.h, bootloader.c
  • Changes:
    • Add some console outputs and changed bootloader read address.
    • Add bugfix for 2018.2 qspi flash

xilisf_v5_11

TE modified 2019.2 xilisf_v5_11

  • Changed default Flash type to 5.

----------------------------------------------------------

Zynq Example:

zynq_fsbl

TE modified 2019.2 FSBL

General:

  • Modified Files:main.c, fsbl_hooks.h/.c (search for 'TE Mod' on source code)
  • Add Files: te_fsbl_hooks.h/.c(for hooks and board)\n\

  • General Changes: 
    • Display FSBL Banner and Device ID

Module Specific:

  • Add Files: all TE Files start with te_*
    • READ MAC from EEPROM and make Address accessible by UBOOT (need copy defines on uboot  platform-top.h)
    • CPLD access
    • Read CPLD Firmware and SoC Type
    • Configure Marvell PHY

zynq_fsbl_flash

TE modified 2019.2 FSBL

General:

  • Modified Files: main.c
  • General Changes:
    •  Display FSBL Banner
    • Set FSBL Boot Mode to JTAG
    • Disable Memory initialisation

ZynqMP Example:

----------------------------------------------------------

zynqmp_fsbl

TE modified 2019.2 FSBL

General:

  • Modified Files: xfsbl_main.c, xfsbl_hooks.h/.c, xfsbl_board.h/.c(search for 'TE Mod' on source code)
  • Add Files:  te_xfsbl_hooks.h/.c (for hooks and board)\n\
  • General Changes: 
    • Display FSBL Banner and Device Name

Module Specific:

  • Add Files: all TE Files start with te_*
    • Si5338 Configuration
    • ETH+OTG Reset over MIO

zynqmp_fsbl_flash

TE modified 2019.2 FSBL

General:

  • Modified Files: xfsbl_initialisation.c, xfsbl_hw.h, xfsbl_handoff.c, xfsbl_main.c
  • General Changes:
    •  Display FSBL Banner
    • Set FSBL Boot Mode to JTAG
    • Disable Memory initialisation


zynqmp_pmufw

Xilinx default PMU firmware.

----------------------------------------------------------

General Example:

hello_te0820

Hello TE0820 is a Xilinx Hello World example as endless loop instead of one console output.

u-boot

U-Boot.elf is generated with PetaLinux. Vitis  is used to generate Boot.bin.

Template location: ./sw_lib/sw_apps/

zynq_fsbl

TE modified 2019.2 FSBL

General:

  • Modified Files:main.c, fsbl_hooks.h/.c (search for 'TE Mod' on source code)
  • Add Files: te_fsbl_hooks.h/.c(for hooks and board)\n\

  • General Changes: 
    • Display FSBL Banner and Device ID

Module Specific:

  • Add Files: all TE Files start with te_*
    • Si5338 Configuration

zynq_fsbl_flash

TE modified 2019.2 FSBL

General:

  • Modified Files: main.c
  • General Changes:
    •  Display FSBL Banner
    • Set FSBL Boot Mode to JTAG
    • Disable Memory initialisation

hello_te0745

Hello TE0745 is a Xilinx Hello World example as endless loop instead of one console output.

u-boot

U-Boot.elf is generated with PetaLinux. SDK/HSI is used to generate Boot.bin.

Software Design -  PetaLinux

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Note:
  • optional chapter separate

  • sections for linux

  • Add "No changes." or "Activate: and add List"

For PetaLinux installation and  project creation, follow instructions from:

Config

Start with petalinux-config or petalinux-config --get-hw-description

Changes:

  • CONFIG_SUBSYSTEM_ETHERNET_PS7_ETHERNET_0_MAC=""

U-Boot

Start with petalinux-config -c u-boot

Changes:

  • CONFIG_ENV_IS_NOWHERE=y
  • # CONFIG_ENV_IS_IN_SPI_FLASH is not set
  • CONFIG_I2C_EEPROM=y
  • CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET=0xFA
  • CONFIG_SYS_I2C_EEPROM_ADDR=0x53
  • CONFIG_SYS_I2C_EEPROM_BUS=0
  • CONFIG_SYS_EEPROM_SIZE=256
  • CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=0
  • CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=0
  • CONFIG_SYS_I2C_EEPROM_ADDR_LEN=1
  • CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW=0

Change platform-top.h:

Code Block
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Device Tree

Code Block
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/include/ "system-conf.dtsi"
/ {
  chosen {
    xlnx,eeprom = &eeprom;
  };
};

/* QSPI PHY */
&qspi {
    #address-cells = <1>;
    #size-cells = <0>;
    status = "okay";
    flash0: flash@0 {
        compatible = "jedec,spi-nor";
        reg = <0x0>;
        #address-cells = <1>;
        #size-cells = <1>;
    };
};


/* ethernet */
&gem0 {
    	phy-handle = <&phy0>;
    	mdio {
        		#address-cells = <1>;
        		#size-cells = <0>;
        		phy0: phy@1 {
            			compatible = "marvell,88e1510";
            
			device_type = "ethernet-phy";
            			reg = <1>;
        		} ;
    	} ;
};

/* usb */
/{
    	usb_phy0: usb_phy@0 {
        		compatible = "ulpi-phy";
        		#phy-cells = <0>;
        		reg = <0xe0002000 0x1000>;
        		view-port = <0x0170>;
        		drv-vbus;
    	};
};

&usb0 {
    dr_mode = "host";
    //dr_mode = "peripheral";
    usb-phy = <&usb_phy0>;
};


/* I2C */

&i2c0 {
    	#address-cells = <1>;
    	#size-cells = <0>;

	rtc0: rtc@6F {
		compatible  rtc0: rtc@6F {
        = "isl12022";
		reg = <0x6F>;
	};
	  //MAC EEPROM
	  eeprom: eeprom@53 {
	    compatible = "isl12022atmel,24c08";
    	    reg = <0x6F><0x53>;
  	  };


    	i2cmux_SFP: i2cmux@72  {
        		compatible = "nxp,pca9548";
        		#address-cells = <1>;
        		#size-cells = <0>;
        		reg = <0x72>;

        		SFP@0 {
            			#address-cells = <1>;
            			#size-cells = <0>;
            			reg = <0>;
        		};
        		SFP@1 {
            			#address-cells = <1>;
            			#size-cells = <0>;
            			reg = <1>;
        		};
        		SFP@2 {
            			#address-cells = <1>;
            			#size-cells = <0>;
            			reg = <2>;
        		};
        		SFP@3 {
            			#address-cells = <1>;
            			#size-cells = <0>;
            			reg = <3>;
        		};
        SFP@4 {
            		SFP@4 {
			#address-cells = <1>;
            			#size-cells = <0>;
            			reg = <4>;
        		};
        		SFP@5 {
            			#address-cells = <1>;
            			#size-cells = <0>;
            			reg = <5>;
        		};
        		SFP@6 {
            			#address-cells = <1>;
            			#size-cells = <0>;
             = <0>;
			reg = <6>;
        		};
        		SFP@7 {
            			#address-cells = <1>;
            			#size-cells = <0>;
            			reg = <7>;
         <7>;
		};
    	};

};



Kernel

Activate:

  • USB_ULPI_BUS
  • RTC_DRV_ISL12022

Rootfs

Activate:

...

Start with petalinux-config -c kernel

Changes:

  • CONFIG_RTC_DRV_ISL12022=y

Rootfs

Start with petalinux-config -c rootfs

Changes:

  • i2c-tools
  • CONFIG_busybox-httpd=y (for web server app)
  • CONFIG_packagegroup-petalinux-utils(util-linux,cpufrequtils,bridge-utils,mtd-utils,usbutils,pciutils,canutils,i2c-tools,smartmontools,e2fsprogs)

Applications

startup

Script App to load init.sh from SD Card if available.See: \os\petalinux\project-spec\meta-user\recipes-apps\startup\files

webfwu

Webserver application accemble for Zynq access. Need busybox-httpd

Additional Software

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Note:
  • Add description for other Software, for example SI CLK Builder ...
  • SI5338 and SI5345 also Link to:

...

File location <design name>/misc/Si5338/RegisterMapSi5338-*.txtslabtimeproj

General documentation how you work with these project will be available on Si5338

...

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DateDocument Revision

Authors

Description

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infoTypeModified by
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  • Release 2019.2
2019-09-18v.12John Hartfiel
  • bugfix for TE0745-02-45-3EA
2018-12-19v.11John Hartfiel
  • documentation notes

2018-11-26

v.10John Hartfiel
  • update 2018.2
  • documentation style update

2018-04-09

v.7John Hartfiel
  • Typo correction
2018-02-09v.6John Hartfiel
  • Release 2017.2
2017-09-11v.1John Hartfiel
  • Initial release
--all

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