Page History
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Type or File | Version |
---|---|
Vivado Design Suite | 2017.12 |
Trenz Project Scripts | 2017.12.0502 |
Trenz <board_series>_board_files.csv | 1.3 |
Trenz apps_list.csv | 2.0 |
Trenz zip_ignore_list.csv | 1.0 |
Trenz mod_bd.csv (not included) | 1.1 |
...
- For modules with dual parallel QSPI implementation only:
Configure Flash with TE::pr_program_flash_binfile does not work. Reason: Select FSBL file is not implemented. Workaround: Use Vivado or SDK GUI and select FSBL manually. - Linux OS only: HSI software generation failed. Reason: start gmake failed . Workaround: SDK GUI to generate applications and boot files.
- Linux OS only: Function, which used external programs. Reason: Currently only set correctly for Win OS. Workaround: Change TCL scripts program path manually.
- For modules with dual parallel QSPI implementation only:
Directory structure
File or Directory | Type | Description |
---|---|---|
<design_name> | base directory | Base directory with predefined batch files (*.cmd) to generate or open VIVADO-Project |
<design_name>/block_design/ | source | Script to generate Block Design in Vivado (*_bd.tcl). (optional) Some board part designs used subfolder <board_file_shortname> with Board Part specific Block Design (*_bd.tcl). |
<design_name>/board_files/ | source | Local board part files repository and a list of available board part files (<board_series>_board_files.csv) |
<design_name>/board_files/carrier_extension | source | (Optional) Additional TCL-Scripts to extend Board Part PS-Preset with carrier board specific settings. |
<design_name>/console | source | folder with different console command files. Use _create_win_setup.cmd or _create_linux_setup.sh to generate files on top folder. |
<design_name>/constraints/ | source | Project constrains (*.xdc). Some board part designs used subfolder <board_file_shortname> with additional constrains (*.xdc) |
<design_name>/doc/ | source | Documentation |
<design_name>/hdl/ | source | HDL-File and XCI-Files. Advanced usage only! |
<design_name>/firmware/ | source | ELF-File Location for MicroBlaze Firmware. Additional sub folder is used for MicroBlaze identification. |
<design_name>/ip_lib/ | source | Local Vivado IP repository |
<design_name>/misc/ | source | (Optional) Directory with additional sources |
<design_name>/prebuilt/ | prebuilt | Contains a readme with location information of different assembly variants |
<design_name>/prebuilt/boot_images/ | prebuilt | Directory with prebuilt boot images (*.bin) and configuration files (*.bif) for zynq and configured hardware files (*.bit and *.mcs) for micoblaze included in sub-folders: default or <board_file_shortname>/<app_name> |
<design_name>/prebuilt/hardware/ | prebuilt | Directory with prebuilt hardware sources (*.bit, *hdf, *.mcs) and reports included in subfolders: default or <board_file_shortname> |
<design_name>/prebuilt/software/ | prebuilt | (Optional) Directory with prebuilt software sources (*.elf) included in subfolders: default or <board_file_shortname>/<app_name> |
<design_name>/prebuilt/os/ | prebuilt | (Optional) Directory with predefined OS images included in subfolders <os_name>/<board_file_shortname> or <os_name>/default |
<design_name>/scripts/ | source | TCL scripts to build a project |
<design_name>/settings/ | source | (Optional) Additional design settings: zip_ignore_list.csv, vivado project settings, SDSOC settings |
<design_name>/software/ | source | (Optional) Directory with additional software |
<design_name>/os/ | source | (Optional) Directory with additional os sources in in subfolders <os_name> |
<design_name>/sw_lib/ | source | (Optional) Directory with local SDK/HSI software IP repository and a list of available software (apps_list.csv) |
<design_name>/v_log/ | generated | (Temporary) Directory with vivado log files (used only when Vivado is started with predefined command files (*.cmd) from base folder otherwise this logs will be writen into the vivado working directory) |
<design_name>/vivado/ | work, generated | (Temporary) Working directory where Vivado project is created. Vivado project file is <design_name>.xpr |
<design_name>/vivado_lab/ | work, generated | (Optional/Temporary) Working directory where Vivado LabTools is created. LabTools project file is <design_name>.lpr |
<design_name>/workspace/hsi | work, generated | (Optional/Temporary) Directory where hsi project is created |
<design_name>/workspace/sdk | work, generated | (Optional) Directory where sdk project is created |
<design_name>/.../SDSoC_PFM | work, generated | (Optional) Directory where SDSOC project is created |
<design_name>/backup/ | generated | (Optional) Directory for project backups |
...
File Name | Status | Description |
---|---|---|
Design + Settings | ||
design_basic_settings.sh | available | Settings for the other *.cmd files. Following Settings are avaliable:
|
design_clear_design_folders.sh | not available | (optional) Attention: Delete "<design_name>/v_log/", "<design_name>/vivado/", "<design_name>/vivado_lab/", "<design_name>/sdsoc/", and "<design_name>/workspace/" directory with related documents! Type "Y" into the command line input to start deleting files |
design_run_project_bashmode.sh | not available | (optional) Create Project with setting from "design_basic_settings.cmd" and source folders. Build all Vivado hardware and software files if the sources are available. Delete "<design_name>/vivado/", and "<design_name>/workspace/hsi/" directory with related documents before Project will created. |
Hardware Design | ||
vivado_create_project_guimode.sh | available | Create Project with setting from "design_basic_settings.cmd" and source folders. Vivado GUI will be opened during the process. Delete "<design_name>/vivado/", and "<design_name>/workspace/" directory with related documents before Project will created. If old vivado project exists, type "y" into the command line input to start project creation again. |
vivado_create_project_bashmode.sh | not available | (optional) Create Project with setting from "design_basic_settings.cmd" and source folders. Delete "<design_name>/vivado/", and "<design_name>/workspace/" directory with related documents before Project will created. If old vivado project exists, type "y" into the command line input to start project creation again. |
vivado_open_existing_project_guimode.sh | available | Opens an existing Project "<design_name>/vivado/<design_name>.xpr" and restore Script-Variables. |
Software Design | ||
sdk_create_prebuilt_project_guimode.sh | not available | (optional) Create SDK project with hardware definition file from prebuild folder. It used the *.hdf from: <design_name>/prebuilt/hardware/<board_file_shortname>/. Set <board_file_shortname> and <app_name> in "design_basic_settings.cmd". |
Programming | ||
program_flash_binfile.sh | not available | (optional) For Zynq Systems only. Programming Flash Memory via JTAG with specified Boot.bin. Used SDK Programmer (Same as SDK "Program Flash") or LabTools Programmer (Vivado or LabTools only), depends on installion settings. Default, it used the boot.bin from: <design_name>/prebuilt/boot_images/<board_file_shortname>/<app_name>. Settings are done in "design_basic_settings.cmd". |
program_flash_mcsfile.sh | not available | (optional) For Non-Zynq Systems only. Programming Flash Memory via JTAG with specified <design_name>.mcs. Used LabTools Programmer (Vivado or LabTools only), depends on installion settings. Default, it used the <design_name>.mcs from: <design_name>/prebuilt/hardware/<board_file_shortname>. Settings are done in "design_basic_settings.cmd". |
program_fpga_bitfile.sh | not available | (optional) Programming FPGA via JTAG with specified <design_name>.bit. Used LabTools Programmer (Vivado or LabTools only), depends on installion settings. Default, it used the <design_name>.bit from: <design_name>/prebuilt/hardware/<board_file_shortname>. Settings are done in "design_basic_settings.cmd". |
labtools_open_project_guimode.sh | not available | (optional) Create or open an existing Vivado Lab Tools Project. (Additional TCL functions from Programming and Utilities Group are usable). Settings are done in "design_basic_settings.cmd". |
TE-TCL-Extentsions
Name | Options | Description (Default Configuration) |
---|---|---|
TE::help | Display currently available functions. Important: Use only displayed functions and no functions from sub-namespaces | |
Hardware Design | ||
TE::hw_blockdesign_create_bd | [-bd_name] [-msys_local_mem] [-msys_ecc] [-msys_cache] [-msys_debug_module] [-msys_axi_periph] [-msys_axi_intc] [-msys_clk] [-help] | Create new Block-Design with initial Setting for PS, for predefined bd_names: Typ TE::hw_blockdesign_create_bd -help for more information |
TE::hw_blockdesign_export_tcl | [-no_mig_contents] [-no_validate] [-mod_tcl] [-svntxt <arg>] [-board_part_only] [-help] | Export Block Design to project folder <design_name>/block_design/ . Old *bd.tcl will be overwritten! |
TE::hw_build_design | [-export_prebuilt] [-export_prebuilt_only] [-help] | Run Synthese, Implement, and generate Bit-file, optional MCS-file and some report files |
Software Design | ||
TE::sw_run_hsi | [-run_only] [-prebuilt_hdf <arg>] [-no_hsi] [-no_bif] [-no_bin] [-no_bitmcs] [-clear] [-help] | Copies current Hardware files and reports from the vivado project to the prebuilt folder, if -prebuild_hdf <arg> isn't set.
|
TE::sw_run_sdk | [-open_only] [-update_hdf_only] [-prebuilt_hdf <arg>] [-clear] [-help] | Copies current Hardware files and reports from the vivado project to the prebuilt folder, if -prebuild_hdf <arg> isn't set. |
Programming | ||
TE::pr_init_hardware_manager | [-help] | Open Hardwaremanager, autoconnect target device and initialise flash memory with configuration from *_board_files.csv. |
TE::pr_program_jtag_bitfile | [-used_board <arg>] [-swapp <arg>] [-available_apps] [-used_basefolder_bitfile] [-help] | Copies current Hardware files and reports from the vivado project to the prebuilt folder, if -used_board <arg> isn't set (Vivado only). (MicroBlaze only) If "-swapp" is set, the Bitfile with *.elf configuration is used from <design_name>/prebuilt/boot_images/<board_file_shortname>/<app_name> |
TE::pr_program_flash_binfile | [-no_reboot] [-used_board <arg>] [-swapp <arg>] [-available_apps] [-force_hw_manager] [-used_basefolder_binfile] [-help] | Attention: For Zynq Systems only! |
TE::pr_program_flash_mcsfile | [-no_reboot] [-used_board <arg>] [-swapp <arg>] [-available_apps] [-used_basefolder_mcsfile] [-help] | Copies current Hardware files and reports from the vivado project to the prebuilt folder, if -used_board <arg> isn't set (Vivado only). (MicroBlaze only) If "-swapp" is set, the MCSfile with *.elf configuration is used from <design_name>/prebuilt/boot_images/<board_file_shortname>/<app_name> |
Utilities | ||
TE::util_zip_project | [-save_all] [-remove_prebuilt] [-manual_filename <arg>] [-help] | Make a Backup from your Project in <design_name>/backup/ Zip-Program Variable must be set in start_settings.cmd. Currently only 7-Zip is supported. |
TE::util_package_length | [-help] | Export Package IO length information to *.csv on the doc folder |
Beta Test (Advanced usage only!) | ||
TE::ADV::beta_util_sdsoc_project | [-check_only] [-help] | Create SDSOC-Workspace. Currently only on some Reference-Designs available. Run [-check_only] option to check SDSOC ready state. |
TE::ADV::beta_hw_remove_board_part | [-permanent] [-help] | Reconfigure Vivado project as project without board part. Generate XDC-File from board part IO definitions and change ip board part properties. No all IPs are supported. |
TE::ADV::beta_hw_export_rtl_ip | \[-help\] | Save IPs used on rtl designs as *.xci in <design_name>hdl/xci. If sub folder <board_file_shortname> is defined this will be saved there. |
Design Environment: Usage
...
- Install Xilinx Vivado Design Suite or Xilinx Vivado Webpack (free license for some FPGA only: see http://www.xilinx.com/products/design-tools/vivado/vivado-webpack.html)
(optional) Install Xilinx Vivado LabTools (Lab Edition) - Configure the reference-design:
1. Open “design_basic_settings.cmd” with a text-editor:
a. Set correct Xilinx Environment:
@set XILDIR=C:/Xilinx
@set VIVADO_VERSION=2017.12
Program settings will be search in :
%XILDIR%/VIVADO/%VIVADO_VERSION%/
%XILDIR%/Vivado_Lab/%VIVADO_VERSION%/
%XILDIR%/SDK/%VIVADO_VERSION%/
Example directory: c:/Xilinx/Vivado/2017.12/
Attention: Scripts are supported only with predefined Vivado Version!
b. Set the correct module part-number:
@set PARTNUMBER=x
You found the available Module Numbers in <design_name>/board_files/<board_series>_board_files.csv
c. Set Application name (for programming with batch-files only):
@set SWAPP=NA
NA (No Software Project) used *.bit or *.mcs from <design_name>/prebuilt/hardware/<board_file_shortname>
<app_name> (Software Project) used *.bit or *.mcs or *.bin from <design_name>/prebuilt/boot_images/<board_file_shortname>/<app_name> - Create all prebuilt files in one step:
2. Run “design_run_project_batchmode.cmd” - (optional to Step 2) Create all prebuilt files in single steps:
3. Run “vivado_create_project_guimode.cmd”:
A Vivado Project will be create and open in ./vivado
4. Type “TE::hw_build_design” on Vivado TCL-Console:
Run Synthese, Implement and create Bitfile and optional MCSfile
5. Type “TE::sw_run_hsi” on Vivado TCL-Console:
Create all Software Applications from <design_name>/sw_lib/apps_list.csv
6. (optional to Step 5) Type “TE::sw_run_sdk” on Vivado TCL-Console:
Create a SDK Project in <design_name>/workspace/sdk
Include Hardware-Definition-File, Bit-file and local Software-libraries from <design_name>/sw_lib/sw_apps Programming FPGA or Flash Memory with prebuilt Files:
7. Connect your Hardware-Modul with PC via JTAG.
With Batch-file:
8. (optional) Zynq-Devices Flash Programming (*.bin):
Run “program_flash_binfile.cmd”
9. (optional) FPGA-Device Flash Programming (*.mcs):
Run “program_flash_mcsfile.cmd”
10. (optional) FPGA-Device Programming (*.bit):
Run “program_fpga_bitfile.cmd”
With Vivado/Labtools TCL-Console:
11. Run “vivado_open_existing_project_guimode.cmd” or “labtools_open_project_guimode.cmd” to open Vivado or LabTools
12. (optional) Zynq-Devices Flash Programming (*.bin):
Type “TE::pr_program_flash_binfile -swap <app_name>” on Vivado TCL-Console
Used *.bin from <design_name>/prebuilt/boot_images/<board_file_shortname>/<app_name>
13. (optional) FPGA-Device Flash Programming (*.mcs):
Type “TE:: pr_program_flash_mcsfile -swap <app_name>” on Vivado TCL-Console
Used *.mcs from <design_name>/prebuilt/boot_images/<board_file_shortname>/<app_name>
14. (optional) FPGA-Device Programming (*.bit):
Type “TE:: pr_program_jtag_bitfile -swap <app_name>” on Vivado TCL-Console
Used *.bit from <design_name>/prebuilt/boot_images/<board_file_shortname>/<app_name>
...
- Are you using exactly the same Vivado version? If not then the scripts will not work, no need to try.
- Ary you using Vivado in Windows PC? Vivado works in Linux also, but the scripts are tested on Windows only.
- Is you PC OS Installation English? Vivado may work on national versions also, but there have been known problems.
- Win OS only: Use short path name, OS allows only 256 characters in normal path.
- Linux OS only: Use bash as shell and add access rights to bash files.
- Are space character on the project path? Somtimes TCL-Scripts can't handle this correctly. Remove spaces from project path.
- Did you have the newest reference design build version? Maybe it's only a bug from a older version.
- Check <design_name>/v_log/vivado.log? If no logfile exist, wrong xilinx paths are set in design_basic_settings.cmd
- On project creation process old files will be deleted. Sometimes the access will be denied by os (synchronisiation problem) and the scripts canceled. Please try again.
- If nothing helps, send a mail to Trenz Electronic Support (support[at]trenz-electronic.de) with subject line "[TE-Reference Designs] ", the complete zip-name from your reference design and the last log file (<design_name>/v_log/vivado.log)
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Date | Revision | Vivado Version | Authors | Description | ||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
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| 2017.12 |
| Work in progress | ||||||||||||||||||||||
2017-09-12 | v.131 | 2017.1 | John Hartfiel | Last Vivado 2017.2 supported project delivery version | ||||||||||||||||||||||
2017-04-12 | v.126 | 2016.4 | John Hartfiel | Last Vivado 2016.4 supported project delivery version | ||||||||||||||||||||||
2017-01-16 | v.114 | 2016.2 | Last Vivado 2016.2 supported project delivery version | |||||||||||||||||||||||
2016-06-21 | 2015.4 | Last Vivado 2015.4 supported project delivery version | ||||||||||||||||||||||||
2013-03-11 | v.1 | --- | Initial release | |||||||||||||||||||||||
All |
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