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Template Revision 2.6 7 - on construction Design Name always "TE Series Name" + Design name, for example "TE0720 Test Board" |
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Notes : - Add basic key futures, which can be tested with the design
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Excerpt |
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- Vitis/Vivado 20182019.32
- QSPI
- SDK
- Custom Carrier (minimum PS Design with available module components only)
- Modified FSBL (some additional outputs only)
- Special FSBL for QSPI Programming
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Date | Vivado | Project Built | Authors | Description |
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20192020- | 501- | 062018.323 | 2019-2 | TE0803-test_board | _noprebuilt-vivado_ | 20182019. | 32-build_ | 053_ | 2019050616194820200123070036.zip TE0803-test_board_noprebuilt-vivado_ | 20182019. | 32-build_ | 053_ | 2019050616193620200123070049.zip | John Hartfiel | - 2019.2 update
- Vitis support
- FSBL SI programming procedure update
| 2019-5-06 | - custom FSBL
- new assembly variants
| 2018-10-26 | 2018.23 | TE0803-test_board_noprebuilt-vivado_2018.23-build_0305_2018102614170520190506161948.zip TE0803-test_board-vivado_2018.23-build_05_20190506161936.zip | John Hartfiel | - custom FSBL
- new assembly variants
| 2018-10-26 | 2018.2 | TE0803-test_board_noprebuilt-vivado_2018.2-build_03_20181026141705.zip TE0803-test_board-vivado_2018.2-build_03_03_20181026141651.zip | John Hartfiel | | 2018-08-14 | 2018.2 | TE0803-test_board_noprebuilt-vivado_2018.2-build_02_20180814103119.zip TE0803-test_board-vivado_2018.2-build_02_20180814103105.zip | John Hartfiel | | 2018-07-13 | 2018.2 | TE0803-test_board_noprebuilt-vivado_2018.2-build_02_20180713085721.zip TE0803-test_board-vivado_2018.2-build_02_20180713085704.zip | John Hartfiel | - additional notes for FSBL generated with Win SDK
- changed *.bif
| 2018-05-17 | 2017.4 | TE0803-test_board_noprebuilt-vivado_2017.4-build_09_20180517152118.zip TE0803-test_board-vivado_2017.4-build_09_20180517152103.zip | John Hartfiel | | 2018-04-11 | 2017.4 | TE0803-test_board_noprebuilt-vivado_2017.4-build_07_20180411081821.zip TE0803-test_board-vivado_2017.4-build_07_20180411081757.zip | John Hartfiel | - bugfix TE0803-01-04EG boart part file
| 2018-02-13 | 2017.4 | TE0803-test_board_noprebuilt-vivado_2017.4-build_06_20180213120257.zip TE0803-test_board-vivado_2017.4-build_06_20180213120229.zip | John Hartfiel | | 2018-02-05 | 2017.4 | TE0803-test_board-vivado_2017.4-build_05_20180205101915.zip TE0803-test_board_noprebuilt-vivado_2017.4-build_05_20180205101943.zip | John Hartfiel | | 2018-01-31 | 2017.4 | TE0803-test_board-vivado_2017.4-build_05_20180131124202.zip TE0803-test_board_noprebuilt-vivado_2017.4-build_05_20180131124215.zip | John Hartfiel | | 2018-01-18 | 2017.4 | TE0803-test_board-vivado_2017.4-build_05_20180118160549.zip TE0803-test_board_noprebuilt-vivado_2017.4-build_05_20180118160604.zip | John Hartfiel | | 2017-11-16 | 2017.2 | TE0803-test_board-vivado_2017.2-build_05_20171116152716.zip TE0803-test_board_noprebuilt-vivado_2017.2-build_05_20171116154619.zip | John Hartfiel | - Update Board Part CSV File with new Flash assembly variants
| | 2017.2 | TE0803-test_board-vivado_2017.2-build_05_20171114090712.zip TE0803-test_board_noprebuilt-vivado_2017.2-build_05_20171114090725.zip | John Hartfiel | |
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Notes : - list of software which was used to generate the design
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Software | Version | Note |
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VivadoVitis | 20182019.32 | needed |
SDK | 2018.3 | needed |
Hardware
, Vivado is included into Vitis installation |
Hardware
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Notes : - list of software which was used to generate the design
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Type | Location | Notes |
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Vivado | <design name>/block_design <design name>/constraints <design name>/ip_lib | Vivado Project will be generated by TE Scripts | SDK/HSIVitis | <design name>/sw_lib | Additional Software Template for SDK/HSI Vitis and apps_list.csv with settings automatically for HSIVitis app generation |
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Additional Sources
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Type | Location | Notes |
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--- | --- | --- |
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Notes : - prebuilt files
- Template Table:
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File | File-Extension | Description |
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BIF-File | *.bif | File with description to generate Bin-File | BIN-File | *.bin | Flash Configuration File with Boot-Image (Zynq-FPGAs) | BIT-File | *.bit | FPGA (PL Part) Configuration File | DebugProbes-File | *.ltx | Definition File for Vivado/Vivado Labtools Debugging Interface | Debian SD-Image | *.img | Debian Image for SD-Card | Diverse Reports | --- | Report files in different formats | Hardware-Platform-Specification-Files | *.hdfxsa | Exported Vivado Hardware Specification for SDK/HSI Vitis and PetaLinux | LabTools Project-File | *.lpr | Vivado Labtools Project File | MCS-File | *.mcs | Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only) | MMI-File | *.mmi | File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only) | OS-Image | *.ub | Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk) | Software-Application-File | *.elf | Software Application for Zynq or MicroBlaze Processor Systems | SREC-File | *.srec | Converted Software Application for MicroBlaze Processor Systems |
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File | File-Extension | Description |
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BIF-File | *.bif | File with description to generate Bin-File | BIN-File | *.bin | Flash Configuration File with Boot-Image (Zynq-FPGAs) | BIT-File | *.bit | FPGA (PL Part) Configuration File | Diverse Reports | --- | Report files in different formats | Hardware-Platform-Specification-Files | *.hdfxsa | Exported Vivado Hardware Specification for SDK/HSI Vitis and PetaLinux | LabTools Project-File | *.lpr | Vivado Labtools Project File | Software-Application-File | *.elf | Software Application for Zynq or MicroBlaze Processor Systems |
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Reference Design is available on:
Design Flow
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- _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
- Press 0 and enter to start "Module Selection Guide"
- (optional Win OS) Generate Virtual Drive or use short directory for the reference design (for example x:\<design name>)
- Create Project (follow instruction of the product selection guide), settings file will be configured automatically during this process
- S(optional for manual changes) elect Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
Note: Select correct one, see TE Board Part Files
Important: Use Board Part Files, which did not ends with *_tebf0808
- Create HDF XSA and export to prebuilt folder
- Run on Vivado TCL: TE::hw_build_design -export_prebuilt
Note: Script generate design and export files into \prebuilt\hardware\<short dir>. Use GUI is the same, except file export to prebuilt folder
- Generate Programming Files with HSI/SDKVitis
- Run on Vivado TCL: TE::sw_run_hsivitis -all
Note: Scripts generate applications and bootable files, which are defined in "sw_lib\apps_list.csv" - (alternative) Start SDK with Vivado GUI or start with TE Scripts on Vivado TCL: TE::sw_run_sdkvitis
Note: See SDK Projects TCL scripts generate also platform project, this must be done manuelly in case GUI is used. See Vitis
Launch
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Note: - Programming and Startup procedure
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Xilinx documentation for programming and debugging: Vivado/SDK/SDSoC-Xilinx Software Programming and Debugging
QSPI
- Connect JTAG and power on carrier with module
- Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"
- Type on Vivado TCL Console: TE::pr_program_flash_binfile -swapp hello_te0808
Note: To program with SDK/Vivado GUI, use special FSBL (zynqmp_fsbl_flash) on setup
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Get prebuilt boot binaries
- _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell
- Press 0 and enter to start "Module Selection Guide"
- Select assembly version
- Validate selection
- Select Create and open delivery binary folder
Note: Folder (<project foler>/_binaries_<Artikel Name>) with subfolder (boot_<app name>) for different applications will be generated
QSPI
- Connect JTAG and power on carrier with module
- Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"
- Type on Vivado TCL Console: TE::pr_program_flash_binfile -swapp hello_te0803
Note: To program with SDK/Vivado GUI, use special FSBL (zynqmp_fsbl_flash) on setup
SD
This does not work, because SD controller is not selected on PS.
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- Prepare HW like described on section Programming
- Connect UART USB (most cases same as JTAG)
- Select QSPI Card as Boot Mode
Note: See TRM of the Carrier, which is used. - Power On PCB
Note: 1. ZynqMP Boot ROM loads PMU Firmware and FSBL from QSPI into OCM, 2. FSBL loads Application into DDR
Debugging:
System Design System Design - Vivado
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Design specific constrain
Not needed.
Software Design - SDK/HSI
For SDK project creation, follow instructions from:
SDK Projects
Application
needed.
Software Design - SDK/HSI
For SDK project creation, follow instructions from:
Vitis
Application
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---------------------------------------------------------- FPGA Example scuMCS Firmware to configure SI5338 and Reset System. srec_spi_bootloaderTE modified 2019.2 SREC Bootloader to load app or second bootloader from flash into DDR Descriptions: - Modified Files: blconfig.h, bootloader.c
- Changes:
- Add some console outputs and changed bootloader read address.
- Add bugfix for 2018.2 qspi flash
xilisf_v5_11TE modified 2019.2 xilisf_v5_11 - Changed default Flash type to 5.
---------------------------------------------------------- Zynq Example: zynq_fsblTE modified 2019.2 FSBL General: Module Specific: - Add Files: all TE Files start with te_*
- READ MAC from EEPROM and make Address accessible by UBOOT (need copy defines on uboot platform-top.h)
- CPLD access
- Read CPLD Firmware and SoC Type
- Configure Marvell PHY
zynq_fsbl_flashTE modified 2019.2 FSBL General: - Modified Files: main.c
- General Changes:
- Display FSBL Banner
- Set FSBL Boot Mode to JTAG
- Disable Memory initialisation
ZynqMP Example: ---------------------------------------------------------- zynqmp_fsblTE modified 2019.2 FSBL General: - Modified Files: xfsbl_main.c, xfsbl_hooks.h/.c, xfsbl_board.h/.c(search for 'TE Mod' on source code)
- Add Files: te_xfsbl_hooks.h/.c (for hooks and board)\n\
- General Changes:
- Display FSBL Banner and Device Name
Module Specific: - Add Files: all TE Files start with te_*
- Si5338 Configuration
- ETH+OTG Reset over MIO
zynqmp_fsbl_flashTE modified 2019.2 FSBL General: - Modified Files: xfsbl_initialisation.c, xfsbl_hw.h, xfsbl_handoff.c, xfsbl_main.c
- General Changes:
- Display FSBL Banner
- Set FSBL Boot Mode to JTAG
- Disable Memory initialisation
zynqmp_pmufwXilinx default PMU firmware. ---------------------------------------------------------- General Example: hello_te0820Hello TE0820 is a Xilinx Hello World example as endless loop instead of one console output. u-bootU-Boot.elf is generated with PetaLinux. SDK/HSI is used to generate Boot.bin. |
Template location: ./sw_lib/sw_apps/
zynqmp_fsbl
TE modified 20182019.3 2 FSBL
General:
- Modified Files: xfsbl_main.c, xfsbl_hooks.h/.c, xfsbl_board.h/.c(search for 'TE Mod' on source code)
- Add Files: te_xfsbl_hooks.h/.c (for hooks and board)\n\
- General Changes:
- Display FSBL Banner and Device Name
zynqmp_fsbl_flash
TE modified 20182019.3 2 FSBL
General:
- Modified Files: xfsbl_initialisation.c, xfsbl_hw.h, xfsbl_handoff.c, xfsbl_main.c
- General Changes:
- Display FSBL Banner
- Set FSBL Boot Mode to JTAG
- Disable Memory initialisation
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dateFormat | yyyy-MM-dd |
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infoType | Current version |
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dateFormat | yyyy-MM-dd |
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prefix | v. |
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type | Flat |
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infoType | Modified by |
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type | Flat |
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| | 2019-05-07 | v.21 | John Hartfiel | | 2018-10-26 | v.18 | John Hartfiel | | | v.16 | John Hartfiel | | | v.15 | John Hartfiel | | | v.14 | John Hartfiel | | | v.13 | John Hartfiel | | | v.11 | John Hartfiel | | 2018-01-18 | v.6 | John Hartfiel | | 2017-11-16 | v.4 | John Hartfiel | - Update assembly versions with new Flash size
| 2017-11-14 | v.3 | John Hartfiel | |
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