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Figure 1: TEBA0841-01 Block Diagram.

Main Components

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Figure 2TEBA0841-01 Carrier Board.

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Table 5: JTAG interface signals.

UART Interface

UART interface is available on B2B connector JB1 and is usually established by MIO-pins of the PS-bank of the mounted SoM's Zynq device. With the TE0790 XMOD USB2.0 adapter, the UART signals can be converted to USB2.0 interface signals:

XMOD FTDI JTAG-Adapter Header

The JTAG interface of the mounted SoM can be accessed via XMOD header JX1, so in use with the XMOD-FT2232H adapter-board TE0790 the mounted SoM can be programmed via USB2.0 interface. The TE0790 board provides also an UART interface to the SoM's Zynq device which can be accessed by the USB2.0 interface of the adapter-board while the signals between these serial interfaces will be converted.

Following table describes the signals and interfaces of the XMOD header JX1:

Pin Schematic NameXMOD Header JX1 PinB2BNote
TCKC (pin 4)JB3-100-
TDOD (pin 8)JB3-98-
TDIF (pin 10)JB3-96-
TMSH (pin 12)JB3-94-
MIO15A (pin 3)JB1-86
UART Signal Schematic NameB2BXMOD Header JX1Pin Header J3NoteMIO14JB1-91JX1-7J3-7UART-RX (receive line)MIO15JB1-86JX1-3J3-3
UART-TX (transmit line)
MIO14B (pin 7)

Table 6: UART interface signals.

SD IO Interface

The SD IO interface of the mounted SoM is routed to the pin header J4. Due to the different operation voltage levels of the MicroSD Card socket (3.3V) and the and the SoM's Zynq device MIO-bank (1.8V), a VDD/VCCIO translation is necessary which can be provided for example by Texas Instruments TXS02612 SDIO port expander IC. Both voltage levels are available on pin header J4:

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Table 7: SD IO interface signals.

USB2.0 Interface

TEBA0841 board has one physical Micro USB2.0 type B socket J10, the differential data signals of the USB2.0 socket are routed to the B2B connector JB2, where they can be accessed by the corresponding USB2.0 PHY transceiver of the mounted SoM.

With Micro USB2.0 type B socket, the USB2.0 interface can also be used in Device or OTG mode.

Following table gives an overview of the USB2.0 interface signals:

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JB2-48

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Table 8: USB2.0 interface signals and connections.

XMOD FTDI JTAG-Adapter Header

The JTAG interface of the mounted SoM can be accessed via XMOD header JX1 and pin header J3, which has a 'XMOD FTDI JTAG Adapter'-compatible pin-assignment, but also two additional pins (15,16) as differential pairs to supply the mounted SoM with an external MGT reference clock signal.

So in use with the XMOD-FT2232H adapter-board TE0790 the mounted SoM can be programmed via USB2.0 interface. The TE0790 board provides also an UART interface to the SoM's Zynq device which can be accessed by the USB2.0 interface of the adapter-board while the signals between these serial interfaces will be converted.

Following table describes the signals and interfaces of the XMOD header JX1 and pin header J3:

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When using XMOD FTDI JTAG Adapter TE0790, the adapter-board's VCC and VCCIO will be sourced by the on-boards 3.3V supply voltage. Set the DIP-switch with the setting:

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Use Xilinx compatible TE0790 adapter board (designation TE-0790-xx with out 'L') to program the Xilinx Zynq devices.

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JB1-91UART-RX (receive line)
BOOTMODEE (pin 9)JB1-90JTAGSEL at TE 4 x 5 SoMs standard pin assignment
RESING (pin 11)JB3-17System Reset at TE 4 x 5 SoMs standard pin assignment

Table 6: XMOD header JX1 signals and connections.

When using XMOD FTDI JTAG Adapter TE0790, the adapter-board's VCC and VCCIO will be sourced by the on-boards 3.3V supply voltage. Set the XMOD DIP-switch with the setting:

XMOD DIP-switchesPosition
Switch 1ON
Switch 2OFF
Switch 3OFF
Switch 4OFF

Table 7: XMOD adapter board DIP-switch positions for voltage configuration.

Note

Use Xilinx compatible TE0790 adapter board (designation TE-0790-xx with out 'L') to program the Xilinx Zynq devices.

The TE0790 adapter board's CPLD have to be configured with the Standard variant of the firmware. Refer to the TE0790 Resources Site for further information and firmware download.

JTAG/UART header J3

As alternative to the XMOD header JX1, on the Carrier Board pin header J3 is present, which has a XMOD header-compatible pin-assignment, but also two additional pins (15,16) as differential pairs to supply the mounted SoM with an external MGT reference clock signal:

Pin Schematic NameHeader J3 PinB2BNote
TCK4JB3-100-
TDO8JB3-98-
TDI10JB3-96-
TMS12JB3-94-
MIO153JB1-86UART-TX (transmit line)
MIO147JB1-91UART-RX (receive line)
BOOTMODE9JB1-90usually 'JTAGSEL' on TE 4 x 5 SoMs
RESIN11JB3-17SoM Reset pin
CLK0_N15JB2-32AC decoupled on-board (100 nF capacitor)
CLK0_P16JB2-34AC decoupled on-board (100 nF capacitor)

Table 8: JTAG/UART header J3 signals and connections.

UART Interface

UART interface is available on B2B connector JB1 and is usually established by MIO-pins of the PS-bank of the mounted SoM's Zynq device. With the TE0790 XMOD USB2.0 adapter, the UART signals can be converted to USB2.0 interface signals:

UART Signal Schematic NameB2BXMOD Header JX1Pin Header J3Note
MIO14JB1-91JX1-7J3-7UART-RX (receive line)
MIO15JB1-86JX1-3J3-3UART-TX (transmit line)

Table 9: UART interface signals.

SD IO Interface

The SD IO interface of the mounted SoM is routed to the pin header J4. Due to the different operation voltage levels of the MicroSD Card socket (3.3V) and the and the SoM's Zynq device MIO-bank (1.8V), a VDD/VCCIO translation is necessary which can be provided for example by Texas Instruments TXS02612 SDIO port expander IC. Both voltage levels are available on pin header J4:

SD IO Signal Schematic NameB2BPin Header J4Note
SD_DAT0JB1-24J4-8SD IO data
SD_DAT1JB1-22J4-10SD IO data
SD_DAT2JB1-20J4-9SD IO data
SD_DAT3JB1-18J4-7SD IO data
SD_CLKJB1-28J4-4SD IO clock
SD_CMDJB1-26J4-3SD IO command

Table 7: SD IO interface signals.

USB2.0 Interface

TEBA0841 board has one physical Micro USB2.0 type B socket J10, the differential data signals of the USB2.0 socket are routed to the B2B connector JB2, where they can be accessed by the corresponding USB2.0 PHY transceiver of the mounted SoM.

With Micro USB2.0 type B socket, the USB2.0 interface can also be used in Device or OTG mode.

Following table gives an overview of the USB2.0 interface signals:

USB2.0 Signal Schematic NameB2BConnected toNote
OTG_N

JB2-48

J10-2USB2.0 data
OTG_PJB2-50J10-3USB2.0 data
OTG-IDJB2-52J10-4Ground this pin for A-Device (host),  left floating this pin for B-Device (peripheral).
USB-VBUSJB2-56J10-1USB supply voltage for Host mode. Not supplied by the Carrier Board.

Table 8: USB2.0 interface signals and connections.

On-board Peripherals

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On-board Pin Header DesignatorVCC / VCCIODirectionPinsNotes
J17

3.3V

In / Out

5, 48

3.3V external supply voltage
VCCIODIn / Out6, 45PL IO-bank VCCIO, depends on Jumper settings
J20

3.3V

In / Out

5, 48

3.3V external supply voltage
VCCIOAIn / Out6, 45PL IO-bank VCCIO, depends on Jumper settings
J43.3VOut5-
M1.8VOUTOut6-

Table 17: Power Pin description of on-board connector.

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Jumper / Header DesignatorVCC / VCCIODirectionPinsNotes
J26VCCIOAIn2, 4, 6-
M1.8VOUTOut1-
2.5VOut3-
3.3V_OUTOut5-
J27

VCCIOD

In2, 4, 6-
M1.8VOUTOut1-
2.5VOut3-
3.3V_OUTOut5-J43.3VOut5-
M1.8VOUTOut6-

Table 18: Power Pin description of VCCIO selection jumper pin header.

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Table 19: Power pin description of peripheral connector.


XMOD JTAG Header DesignatorVCC / VCCIODirectionPinsNotes
JX1 (XMOD)3.3VOut5 connected connected to 3.3V external supply voltage
VIOOut6
J33.3VOut5connected to 3.3V external supply voltage
3.3VOut6

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