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Table 2: General overview of PL I/O signals, SoM's interfaces and control signals connected to the on-board connectors.
SFP+ Connector
On the TEBA0841 carrier board is a The TEBA0841 Carrier Board is equipped with one SFP+ connector J1 (board-rev. 01: Molex 74441-0001). The connector is embedded into a SFP cage J2 (board-rev. 01: Molex 74737-0009).
The differential RX/TX data lanes are connected to B2B connector JB2, the control-lines are connected to B2B connector JB1 and are assigned to MIO-bank pins of the mounted SoM.
The Following table describes the pin-assignment of the SFP+ connector is in detail as fellows:
| SFP+ pin | Pin Schematic Name | B2B | FPGA Direction | Description | Note | ||
|---|---|---|---|---|---|---|---|
| Transmit Data + (pin 18) | MGT_TX3_P | JB2-26 | Output | SFP+ transmit data differential pair | - | ||
| Transmit Data - (pin 19) | MGT_TX3_N | JB2-28 | Output | - | |||
| Receive Data + (pin 13) | MGT_RX3_P | JB2-25 | Input | SFP+ receive data differential pair | - | ||
| Receive Data - (pin 12) | MGT_RX3_N | JB2-27 | Input | - | |||
| Receive Fault (pin 2) | MIO10 | JB1-96 | Input | Fault / Normal Operation | High active logic | ||
| Receive disable (pin 3) 1) | SFP0_TX_DIS | not connected | Output | SFP Enabled / Disabled | Low active logic | ||
| MOD-DEF2 (pin 4) | MIO13 | JB1-98 | Input | Module present / not present | BiDir | 2-wire Serial Interface data | 3.3V pull-up on-boardLow active logic |
| MOD-DEF1 (pin 5) | MIO12 | JB1-100 | Output | 2-wire Serial Interface clock | 3.3V pull-up on-board | ||
| MOD-DEF0 (pin 6) | MIO11 | JB1-94 | BiDir | 2-wire Serial Interface data | Input | Module present / not present | Low active logic3.3V pull-up on-board |
| RS0 (pin 7) | SFP0_RS0 | not connected | Output | Full RX bandwidth | Low active logic | ||
| LOS (pin 8) | MIO0 | JB1-88 | Input | Loss of receiver signal | High active logic | ||
| RS1 (pin 9) | SFP0_RS1 | not connected | Output | Reduced RX bandwidth | Low active logic |
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