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Template Revision 2.1 - on construction

Design Name always "TE Series Name" + Design name, for example "TE0720 Test Board"

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Template Revision 1.2
Basic Notes
 - export PDF to download, if vivado revision is changed!
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Online version of this manual and other related documents can be found at https://wiki.trenz-electronic.de/display/PD/Trenz+Electronic+Documentation
Scroll pdf ignore

Table of contents

Table of Contents
outlinetrue

Overview

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General Design description
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TEF1001 SI5338 Configuration and PCIe Core Example Design.

Key Features

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Excerpt
  • MicroBlaze
  • I2C
  • Flash
  • FMeter
  • PCIe
  • SI5338
  • DDR SODIMM

Revision History

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- Add changes from design
- Export PDF to download, if vivado revision is changed!
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...

Release Notes and Know Issues

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...

Requirements

Software

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Hardware

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Hardware Support
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Basic description of TE Board Part Files is available on TE Board Part Files.

Complete List is available on <design name>/board_files/*_board_files.csv

Design supports following modules:

...

Design supports following carriers:

...

Additional HW Requirements:

...

Content

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For general structure and of the reference design, see Project Delivery

Design Sources

...

Additional Sources

...

Prebuilt

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<table width="100%">
<tr> <th>File                                 </th> <th>File-Extension</th>  <th>Description                                                                              </th> </tr>
<tr> <td>BIF-File                             </td> <td>*.bif         </td>  <td>File with description to generate Bin-File                                               </td> </tr>
<tr> <td>BIN-File                             </td> <td>*.bin         </td>  <td>Flash Configuration File with Boot-Image (Zynq-FPGAs)                                    </td> </tr>
<tr> <td>BIT-File                             </td> <td>*.bit         </td>  <td>FPGA Configuration File                                                                  </td> </tr>
<tr> <td>DebugProbes-File                     </td> <td>*.ltx         </td>  <td>Definition File for Vivado/Vivado Labtools Debugging Interface                           </td> </tr>
<tr> <td>Debian SD-Image                      </td> <td>*.img         </td>  <td>Debian Image for SD-Card                                                                </td> </tr>
<tr> <td>Diverse Reports                      </td> <td>  ---         </td>  <td>Report files in different formats                                                        </td> </tr>
<tr> <td>Hardware-Platform-Specification-Files</td> <td>*.hdf         </td>  <td>Exported Vivado Hardware Specification for SDK/HSI                                       </td> </tr>
<tr> <td>LabTools Project-File                </td> <td>*.lpr         </td>  <td>Vivado Labtools Project File                                                             </td> </tr>
<tr> <td>MCS-File                             </td> <td>*.mcs         </td>  <td>Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)                  </td> </tr>
<tr> <td>MMI-File                             </td> <td>*.mmi         </td>  <td>File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only) </td> </tr>
<tr> <td>OS-Image                             </td> <td>*.ub          </td>  <td>Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)             </td> </tr>
<tr> <td>Software-Application-File            </td> <td>*.elf         </td>  <td>Software Application for Zynq or MicroBlaze Processor Systems                            </td> </tr>
<tr> <td>SREC-File                            </td> <td>*.srec        </td>  <td>Converted Software Application for MicroBlaze Processor Systems                          </td> </tr>    
</table>
-->

...

File

...

File-Extension

...

Description

...

MCS-File

...

*.mcs

...

Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)

...

MMI-File

...

*.mmi

...

File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)

...

Download

Reference Design is only usable with the specified Vivado/SDK/PetaLinux/SDx version. Do never use different Versions of Xilinx Software for the same Project.

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Reference Design is available on:

Design Flow

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Basic Design Steps
Add/ Remove project specific 
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Note

Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first lunch.

Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.

See also:

The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.

TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/SDK GUI.  For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality

 

  1. _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
    Image Removed
  2. Press 0 and enter for minimum setup
  3. (optional Win OS) Generate Virtual Drive or use short directory  for the reference design (for example x:\<design name>)
  4. Create Project
    1. Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
      Note: Select correct one, see TE Board Part Files
  5. Create HDF and export to prebuilt folder
    1. Run on Vivado TCL: TE::hw_build_design -export_prebuilt
      Note: Script generate design and export files into \prebuilt\hardware\<short dir>. Use GUI is the same, except file export to prebuilt folder
  6. Generate Programming Files with HSI/SDK
    1. Start SDK with Vivado GUI or start with TE Scripts on Vivado TCL: TE::sw_run_sdk
      Note: See SDK Projects
    2. Create SI5338 Firmware Example project
    3. (only without DDR on SODIMM) Change Linker Script to BlockRAM (lscript.ld)
    4. Regenerate Design
  7. (optional Block RAM Update) Copy SI5338.elf into "test_board\firmware\microblaze_0" and regenerate Design with TE::hw_build_design -export_prebuilt

Launch

Programming

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Note

Check Module and Carrier TRMs for proper HW configuration before you try any design.

...

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Important General Note:

  • Export PDF to download, if vivado revision is changed!

  • Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro

    • Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)
      • Figure template (note: inner scroll ignore/only only with drawIO object):

        Scroll Title
        anchorFigure_xyz
        titleText
        Scroll Ignore

        Create DrawIO object here: Attention if you copy from other page, use

        Scroll Only

        image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed

      • Table template:

        • Layout macro can be use for landscape of large tables
        • Set column width manually(can be used for small tables to fit over whole page) or leave empty (automatically)
      • Scroll Title
        anchorTable_xyz
        titleText

        Scroll Table Layout
        orientationportrait
        sortDirectionASC
        repeatTableHeadersdefault
        style
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        sortByColumn1
        sortEnabledfalse
        cellHighlightingtrue

        ExampleComment
        12
  • ...
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Table of contents

Table of Contents
outlinetrue

Overview

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Notes :


TEF1001 SI5338 Configuration, DDR Configuration and PCIe Core Example Design.

Refer to http://trenz.org/tef1001-info for the current online version of this manual and other available documentation.

Key Features

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Notes :

  • Add basic key futures, which can be tested with the design
Excerpt
  • MicroBlaze
  • I2C
  • Flash
  • FMeter
  • PCIe
  • SI5338
  • DDR3 ECC SODIMM (currently ECC disabled)

Revision History

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Notes :

  • add every update file on the download
  • add design changes on description
Scroll Title
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titleDesign Revision History

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DateVivadoProject BuiltAuthorsDescription
2018-10-252018.2TEF1001-test_board-vivado_2018.2-build_03_20181025165553.zip
TEF1001-test_board_noprebuilt-vivado_2018.2-build_03_20181025165625.zip
John Hartfiel
  • Add -410 assembly variant
  • Add some notes on Board part Files (summary window description)
2018-10-252018.2TEF1001-test_board_noprebuilt-vivado_2018.2-build_03_20181024154054.zip
TEF1001-test_board-vivado_2018.2-build_03_20181024154034.zip
John Hartfiel
  • 2018.2
  • add TEF1001-02
  • MIG Configuration for AW12P7218BLK0M (4GB for REV01)
  • MIG Configuration for AW24P7228BLK0M (8GB for REV02)
  • BUGFIX QSPI IP configuration
  • add SREC to load application into DDR
2018-03-072017.4TEF1001-test_board_noprebuilt-vivado_2017.4-build_06_20180307102924.zip
TEF1001-test_board-vivado_2017.4-build_06_20180307102845.zip
John Hartfiel
  • 2017.4 update
  • new assembly variant
2017-11-282017.2TEF1001-test_board-vivado_2017.2-build_05_20171128114335.zip
TEF1001-test_board_noprebuilt-vivado_2017.2-build_05_20171128114350.zip
John Hartfiel
  • initial release

Release Notes and Know Issues

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Notes :
  • add known Design issues and general notes for the current revision
  • do not delete known issue, add fixed version time stamp if  issue fixed
Scroll Title
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titleKnown Issues

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IssuesDescriptionWorkaroundTo be fixed version
DDR3 ECC SODIMMDDR3 does not work with ECC enabled

Disable ECC:

  • for Block Design MIG with AXI Interface, create 64Bit MIG
  • for RTL MIG with Native Interface, disable ECC on MIG configuration and use 72Bit for Data
---

Requirements

Software

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Notes :

  • list of software which was used to generate the design
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titleSoftware

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SoftwareVersionNote
Vivado2018.2needed
SDK2018.2needed
SI5338 Clock Builder---optional

Hardware

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Notes :

  • list of software which was used to generate the design

Basic description of TE Board Part Files is available on TE Board Part Files.

Complete List is available on <design name>/board_files/*_board_files.csv

Design supports following modules:

Scroll Title
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titleHardware Modules

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Module ModelBoard Part Short NamePCB Revision SupportDDRQSPI FlashOthersNotes
TEF1001-01-160-2I1_160_2REV01DDR3 ECC SODIMM*32MB
  • DDR configured for AW12P7218BLK0M (4GB for REV01)
TEF1001-01-325-2C1_325_2REV01DDR3 ECC SODIMM*32MB
  • DDR configured for AW12P7218BLK0M (4GB for REV01)
TEF1001-02-160-2I2_160_2REV02DDR3 ECC SODIMM32MB
  • DDR configured for AW24P7228BLK0M (8GB for REV02)
TEF1001-02-325-2C2_325_2REV02DDR3 ECC SODIMM32MB
  • DDR configured for AW24P7228BLK0M (8GB for REV02)
TEF1001-02-410-2I2_410_2REV02DDR3 ECC SODIMM32MB
  • DDR configured for AW24P7228BLK0M (8GB for REV02)

* PCB REV01 DDR3 ECC SODIMM is limited to 4GB, for PCB REV02 up to 8GB is possible

Design supports following carriers:

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titleHardware Carrier

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Carrier ModelNotes
PC with PCIe Card slot
Stand-alone

Additional HW Requirements:

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titleAdditional Hardware

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Additional HardwareNotes
 JTAG Programmer
  •  TE0790 with TE0791 for CPLD or FPGA
  • Xilinx compatible JTAG programmer for FPGA
DDR3 (204 Pin with ECC)
  • for example:
    • AW12P7218BLK0M ( max. 4GB for REV01)
    • AW24P7228BLK0M (max. 8GB for REV02)

Content

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Notes :

  • content of the zip file


For general structure and of the reference design, see Project Delivery - Xilinx devices

Design Sources

Scroll Title
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titleDesign sources

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TypeLocationNotes
Vivado<design name>/block_design
<design name>/constraints
<design name>/ip_lib
Vivado Project will be generated by TE Scripts
SDK/HSI<design name>/sw_libAdditional Software Template for SDK/HSI and apps_list.csv with settings for HSI

Additional Sources

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titleAdditional design sources

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TypeLocationNotes
SI5338<design name>/misc/Si5338SI5338 Project with current PLL Configuration

Prebuilt

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  • prebuilt files
  • Template Table:
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      titlePrebuilt files

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      File

      File-Extension

      Description

      BIF-File*.bifFile with description to generate Bin-File
      BIN-File*.binFlash Configuration File with Boot-Image (Zynq-FPGAs)
      BIT-File*.bitFPGA (PL Part) Configuration File
      DebugProbes-File*.ltxDefinition File for Vivado/Vivado Labtools Debugging Interface

      Debian SD-Image

      *.img

      Debian Image for SD-Card

      Diverse Reports---Report files in different formats
      Hardware-Platform-Specification-Files*.hdfExported Vivado Hardware Specification for SDK/HSI and PetaLinux
      LabTools Project-File*.lprVivado Labtools Project File

      MCS-File

      *.mcs

      Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)

      MMI-File

      *.mmi

      File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)

      OS-Image*.ubImage with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)
      Software-Application-File*.elfSoftware Application for Zynq or MicroBlaze Processor Systems

      SREC-File

      *.srec

      Converted Software Application for MicroBlaze Processor Systems

Scroll Title
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titlePrebuilt files (only on ZIP with prebult content)

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File

File-Extension

Description

BIT-File*.bitFPGA (PL Part) Configuration File
DebugProbes-File*.ltxDefinition File for Vivado/Vivado Labtools Debugging Interface
Diverse Reports---Report files in different formats
Hardware-Platform-Specification-Files*.hdfExported Vivado Hardware Specification for SDK/HSI and PetaLinux
LabTools Project-File*.lprVivado Labtools Project File

MCS-File

*.mcs

Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)

MMI-File

*.mmi

File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)

Software-Application-File*.elfSoftware Application for Zynq or MicroBlaze Processor Systems

SREC-File

*.srec

Converted Software Application for MicroBlaze Processor Systems

Download

Reference Design is only usable with the specified Vivado/SDK/PetaLinux/SDx version. Do never use different Versions of Xilinx Software for the same Project.

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Reference Design is available on:

Design Flow

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Notes :
  • Basic Design Steps

  • Add/ Remove project specific description

Note

Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first lunch.

Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.

See also:

The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.

TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/SDK GUI.  For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality


  1. _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
    Image Added
  2. Press 0 and enter for minimum setup
  3. (optional Win OS) Generate Virtual Drive or use short directory  for the reference design (for example x:\<design name>)
  4. Create Project
    1. Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
      Note: Select correct one, see TE Board Part Files
  5. Create HDF and export to prebuilt folder
    1. Run on Vivado TCL: TE::hw_build_design -export_prebuilt
      Note: Script generate design and export files into \prebuilt\hardware\<short dir>. Use GUI is the same, except file export to prebuilt folder
  6. Generate Programming Files with HSI/SDK
    1. Start with TE Scripts on Vivado TCL: TE::sw_run_hsi
      (optional) Start SDK with Vivado GUI or start with TE Scripts on Vivado TCL: TE::sw_run_sdk to generate files manually
      Note: See SDK Projects
    2. (optional )Copy "prebuilt\software\<short dir>\srec_spi_bootloader.elf" into "\firmware\microblaze_0" (replace shipped one) and regenerate design again (HW (Step5)+SW(Step6 only a.))

Launch

Programming

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Note:

  • Programming and Startup procedure
Note

Check Module and Carrier TRMs for proper HW configuration before you try any design.

Xilinx documentation for programming and debugging: Vivado/SDK/SDSoC-Xilinx Software Programming and Debugging

QSPI

  1. Connect JTAG and Power ON PC
  2. Open Vivado HW Manager with: TE::pr_init_hardware_manager
  3. Select generated mcs and prm file: test_board/prebuilt/hardware/<assembly option>/ and test_board/prebuilt/hardware/<assembly option>/reports/
  4. Configure Flash
  5. Reboot PC
HTML
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Example:
Connect JTAG and power on PCB
(if not done) Select 
correct device and Xilinx install path on "design_basic_settings.cmd" 
and create Vivado project with "vivado_create_project_guimode.cmd" or 
open with "vivado_open_project_guimode.cmd", if generated.
Type on Vivado Console: TE::pr_program_flash_mcsfile -swapp u-boot
Note: Alternative use SDK or setup Flash on Vivado manually
Reboot (if not done automatically)

   -->

SD

Not used on this Example.

JTAG

Not used on this Example.

Usage

  1. Prepare HW like described on section Programming
  2. Power On PCB
    Note: 1. Artix Load Bitfile (optional with SI5338 Initialisation App) into FPGA

Vivado HW Manager

  1. Open Vivado HW Manager
  2. Add VIO to Dashboard:
  3. Set Radix to unsigned integer for FMeterCLKs
  4. Control:
    1. USER LED is selectable
    2. Optional PCIe Core Reset (on FPGA only)
    3. Optional System Reset (on FPGA only)
  5. Read: All SI5338 CLKs (Unit Hz), PCIe Cor MMCM Lock signal, MIG MMCM Lock signal, MIG Init Calibration
    Image Removed

 PC

Use for example PCI-Z (Win) or KInfoCenter (Linux) to detect PCIe Card

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System Design - Vivado

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Block Design

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Constrains

Basic module constrains

Code Block
languageruby
title_i_bitgen_common.xdc
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property BITSTREAM.CONFIG.CONFIGRATE 66 [current_design]
set_property CONFIG_VOLTAGE 1.8 [current_design]
set_property CFGBVS GND [current_design]
set_property CONFIG_MODE SPIx4 [current_design]
set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design]
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
set_property BITSTREAM.CONFIG.M1PIN PULLNONE [current_design]
set_property BITSTREAM.CONFIG.M2PIN PULLNONE [current_design]
set_property BITSTREAM.CONFIG.M0PIN PULLNONE [current_design]

set_property BITSTREAM.CONFIG.USR_ACCESS TIMESTAMP [current_design]

Design specific constrain

...

languageruby
title_i_io.xdc

...

  1. Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"
  2. Type on Vivado TCL Console: TE::pr_program_flash_mcsfile -swapp hello_tef1001
  3. Reboot PC

SD

Not supported.

JTAG

  • Connect Vivado HW Manager and program FPGA
    Note: PCIe enumeration will be not done in this case. SREC Bootloader need Hello TEF1001 application on QSPI Flash for output

Usage

  1. Prepare HW like described on section Programming
  2. Power On PCB
    Note: 1. FPGA Load Bitfile  into FPGA, modified SREC Bootloader configure SI5338 and load application from QSPI into DDR (Depends on linker script)

JTAG/UART Console:

  • Launch the XSDB console on SDK (Xilinx → XSCT Console):
    • type: connect
    • type: targets -set -filter {name =~ "MicroBlaze Debug*"} -index 0
    • type: jtagterminal -start
    • Separat console starts:
      Image Added

Vivado HW Manager:

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Note:

  • Add picture of HW Manager

  • add notes for the signal either groups or topics, for example:

    Control:

    • add controllable IOs with short notes..

    Monitoring:

    • add short notes for signals which will be monitored only

    SI5338_CLK0 Counter: 

    Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder).Set radix from VIO signals to unsigned integer.Note: Frequency Counter is inaccurate and displayed unit is Hz
  1. Open Vivado HW Manager
  2. Add VIO to Dashboard:
  3. Set Radix to unsigned integer for FMeterCLKs (labt_SI_*)
  4. Control:
    1. USER LEDs are selectable
      Note USR_CPLD_LED on PCB REV1 and REV02, USR_LED Matrix only on REV02
    2. Optional PCIe Core Reset (on FPGA only)
    3. Optional System Reset (on FPGA only)
  5. Read: All SI5338 CLKs (Unit Hz), PCIe Cor MMCM Lock signal, MIG MMCM Lock signal, MIG Init Calibration Done
    Image Added

 PC:

  • Use for example PCI-Z (Win) or KInfoCenter (Linux) or lspci command (Linux console) to detect PCIe Card

Image Added

System Design - Vivado

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Note:

  • Description of Block Design, Constrains... BD Pictures from Export...

Block Design

Scroll Title
anchorFigure_BD
titleBlock Design
Image Added

Constrains

Basic module constrains

Code Block
languageruby
title_i_bitgen_common.xdc
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property BITSTREAM.CONFIG.CONFIGRATE 66 [current_design]
set_property CONFIG_VOLTAGE 1.8 [current_design]
set_property CFGBVS GND [current_design]
set_property CONFIG_MODE SPIx4 [current_design]
set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design]
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
set_property BITSTREAM.CONFIG.M1PIN PULLNONE [current_design]
set_property BITSTREAM.CONFIG.M2PIN PULLNONE [current_design]
set_property BITSTREAM.CONFIG.M0PIN PULLNONE [current_design]

set_property BITSTREAM.CONFIG.USR_ACCESS TIMESTAMP [current_design]
Code Block
languageruby
title_i_common.xdc
#
#
#
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLUP [current_design]

Design specific constrain

Code Block
languageruby
title_i_io.xdc
#----------
#USER LED Matrix
#

#USER LEDS CONNECTED TO A FMC_ADJ VCCO BANK (default config 1.8V)
set_property PACKAGE_PIN K25 [get_ports {USR_LED[0]}]
set_property PACKAGE_PIN K26 [get_ports {USR_LED[1]}]
set_property PACKAGE_PIN P26 [get_ports {USR_LED[2]}]
set_property PACKAGE_PIN R26 [get_ports {USR_LED[3]}]
set_property PACKAGE_PIN N16 [get_ports {USR_LED[4]}]
set_property IOSTANDARD LVCMOS18 [get_ports {USR_LED[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports {USR_LED[1]}]
set_property IOSTANDARD LVCMOS18 [get_ports {USR_LED[2]}]
set_property IOSTANDARD LVCMOS18 [get_ports {USR_LED[3]}]
set_property IOSTANDARD LVCMOS18 [get_ports {USR_LED[4]}]

#USER LEDS CONNECTED TO A 1.8V VCCO BANK
set_property PACKAGE_PIN J26 [get_ports {USR_LED[5]}]
set_property PACKAGE_PIN H26 [get_ports {USR_LED[6]}]
set_property PACKAGE_PIN E26 [get_ports {USR_LED[7]}]
set_property PACKAGE_PIN A24 [get_ports {USR_LED[8]}]
set_property IOSTANDARD LVCMOS18 [get_ports {USR_LED[5]}]
set_property IOSTANDARD LVCMOS18 [get_ports {USR_LED[6]}]
set_property IOSTANDARD LVCMOS18 [get_ports {USR_LED[7]}]
set_property IOSTANDARD LVCMOS18 [get_ports {USR_LED[8]}]

#USER LED CONNECTED TO A FMC_ADJ VCCO BANK (default config 1.8V)
set_property PACKAGE_PIN F19 [get_ports {USR_LED[9]}]
set_property IOSTANDARD LVCMOS18 [get_ports {USR_LED[9]}]


#----------
#USER LED over CPLD
# FEX11
set_property PACKAGE_PIN B21 [get_ports {USR_CPLD_LED[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports {USR_CPLD_LED[0]}]
#----------
#CLK DDR3
#AC9 /AD9 for REV01
#AB11 / AC11 for REV02
##set_property PACKAGE_PIN AB11 [get_ports CLK_DDR3_200MHz_clk_p]
##set_property PACKAGE_PIN AC11 [get_ports CLK_DDR3_200MHz_clk_n]
##set_property IOSTANDARD DIFF_SSTL15 [get_ports CLK_DDR3_200MHz_clk_p]
##set_property IOSTANDARD DIFF_SSTL15 [get_ports CLK_DDR3_200MHz_clk_n]
#----------
#QSPI
set_property PACKAGE_PIN C23 [get_ports {spi_rtl_ss_io[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports {spi_rtl_ss_io[0]}]
set_property PACKAGE_PIN B24 [get_ports spi_rtl_io0_io]
set_property PACKAGE_PIN A25 [get_ports spi_rtl_io1_io]
set_property PACKAGE_PIN B22 [get_ports spi_rtl_io2_io]
set_property PACKAGE_PIN A22 [get_ports spi_rtl_io3_io]
set_property IOSTANDARD LVCMOS18 [get_ports {USR_LED[0]}]
#----------
#CLK DDR3spi_rtl_io0_io]
set_property PACKAGE_PINIOSTANDARD AC9LVCMOS18 [get_ports CLKspi_DDR3rtl_200MHzio1_clk_pio]
set_property IOSTANDARD DIFF_SSTL15LVCMOS18 [get_ports CLKspi_DDR3rtl_200MHzio2_clk_pio]
set_property IOSTANDARD DIFF_SSTL15LVCMOS18 [get_ports CLKspi_DDR3rtl_200MHzio3_clk_nio]
#----------
#QSPI#IIC to CPLD
set_property PACKAGE_PIN C23G26 [get_ports {spiSCF_rtlcpld_ss1_io[0scl]}]
set_property IOSTANDARDPACKAGE_PIN LVCMOS18F25 [get_ports {spiSCF_rtlcpld_ss14_io[0oe]}]
set_property PACKAGE_PIN B24 G25 [get_ports SCF_cpld_16_sda]
set_property IOSTANDARD LVCMOS18 [get_ports spiSCF_rtlcpld_io01_ioscl]
set_property PACKAGE_PINIOSTANDARD A25LVCMOS18 [get_ports spiSCF_rtlcpld_io114_iooe]
set_property PACKAGE_PINIOSTANDARD B22LVCMOS18 [get_ports spiSCF_rtlcpld_io216_io]
sda]
#----------
#SI5338 CLKs
set_property PACKAGE_PIN A22H6 [get_ports spi_rtl_io3_io]
{SI_MGT115_0_clk_p[0]}]

set_property IOSTANDARDPACKAGE_PIN LVCMOS18G22 [get_ports spi{SI_rtlFCLK_io0_ioclk_p[1]}]
set_property IOSTANDARDPACKAGE_PIN LVCMOS18D23 [get_ports spi{SI_rtlFCLK_io1_ioclk_p[2]}]
set_property IOSTANDARDPACKAGE_PIN LVCMOS18G24 [get_ports spi{SI_rtlFCLK_io2_ioclk_p[0]}]
set_property IOSTANDARD LVCMOS18LVDS_25 [get_ports spi_rtl_io3_io]
{SI_FCLK_*}]
Code Block
languageruby
title_i_pcie.xdc
#----------
#IIC# to CPLDFEX0
set_property PACKAGE_PIN G26B20 [get_ports SCF_cpld_1_scl{PCI_PERSTN}]
set_property PACKAGE_PINIOSTANDARD F25LVCMOS18 [get_ports SCF_cpld_14_oe]
{PCI_PERSTN}]
#----------
set_property PACKAGE_PIN G25K6 [get_ports SCF_cpld_16_sda]
set_property IOSTANDARD LVCMOS18 [get_ports SCF_cpld_1_scl{CLK_PCIe_100MHz_clk_p[0]}]
set_property IOSTANDARDPACKAGE_PIN LVCMOS18N4 [get_ports SCF{pcie_cpld7x_14_oemgt_rxp[2]}]
set_property IOSTANDARDPACKAGE_PIN LVCMOS18R4 [get_ports SCF{pcie_cpld7x_16_sda]
#----------
#SI5338 CLKs
mgt_rxp[3]}]
set_property PACKAGE_PIN H6L4 [get_ports {SIpcie_MGT1157x_0_clkmgt_prxp[01]}]

set_property PACKAGE_PIN G22J4 [get_ports {SIpcie_FCLK7x_clkmgt_prxp[10]}]
set_property PACKAGE_PIN D23 [get_ports {SI_FCLK_clk_p[2]}]

PCB REV01:

Code Block
languageruby
title_i_io_ddr_clk.xdc
#----------
#CLK DDR3
#AC9 /AD9 for REV01
#AB11 / AC11 for REV02
set_property PACKAGE_PIN G24AC9 [get_ports {SI_FCLKCLK_DDR3_200MHz_clk_p[0]}]
set_property IOSTANDARD LVDS_25 [get_ports {SI_FCLK_*}]
Code Block
languageruby
title_i_pcie.xdc
#----------
# FEX0PACKAGE_PIN AD9 [get_ports CLK_DDR3_200MHz_clk_n]
set_property IOSTANDARD PACKAGEDIFF_PIN B20SSTL15 [get_ports {PCI_PERSTN}CLK_DDR3_200MHz_clk_p]
set_property IOSTANDARD LVCMOS18DIFF_SSTL15 [get_ports {PCI_PERSTN}]
CLK_DDR3_200MHz_clk_n]

PCB REV02:

Code Block
languageruby
title_i_io_ddr_clk.xdc
#----------
#CLK DDR3
#AC9 /AD9 for REV01
#AB11 / AC11 for REV02
set_property PACKAGE_PIN K6AB11 [get_ports {CLK_PCIeDDR3_100MHz200MHz_clk_p[0]}]
set_property PACKAGE_PIN N4AC11 [get_ports {pcie_7x_mgt_rxp[2]}CLK_DDR3_200MHz_clk_n]
set_property IOSTANDARD PACKAGEDIFF_PIN R4SSTL15 [get_ports {pcie_7x_mgt_rxp[3]}]CLK_DDR3_200MHz_clk_p]
set_property IOSTANDARD PACKAGEDIFF_PINSSTL15 L4 [get_ports {pcie_7x_mgt_rxp[1]}]
set_property PACKAGE_PIN J4 [get_ports {pcie_7x_mgt_rxp[0]}]

Software Design - SDK/HSI

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For SDK project creation, follow instructions from:

SDK Projects

Application

SI5338 Initalisation

Si5338 I2C Configuration example.

Additional Software

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Add Description for other Software, for example SI CLK Builder ...
 -->

SI5338 CLKBuilder

  1. Open Register Map File:"\test_board\misc\SI5338\RegisterMap.txt"
  2. Change CLK if needed
  3. Save project and generate "register_map.h"
  4. Overwrite "register_map.h" from SI5338 Init Application with generate file

Appx. A: Change History and Legal Notices

Document Change History

To get content of older revision  got to "Change History"  of this page and select older document revision number.

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  -->CLK_DDR3_200MHz_clk_n]

Software Design - SDK/HSI

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Note:
  • optional chapter separate

  • sections for different apps



For SDK project creation, follow instructions from:

SDK Projects

Application

Template location: ./sw_lib/sw_apps/

hello_tef1001

  • Xiline Hello World as endless loop

SI5338_Init

  • Si5338 I2C Configuration example only.

srec_spi_bootloader

  • modified Xilinx SREC Bootloader, including SI5338 configuration
    • modified Files: blconfig.h, bootloader.c

    • add Files: si5338.h, si5338.c, register_map.h

    • modified  xilisf_v5_11: xilisf.mld (default Flash Typ:5)

Additional Software

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Note:
  • Add description for other Software, for example SI CLK Builder ...
  • SI5338 and SI5345 also Link to:


SI5338

File location <design name>/misc/Si5338/RegisterMap.txt

General documentation how you work with these project will be available on Si5338

Appx. A: Change History and Legal Notices

Document Change History

To get content of older revision  got to "Change History"  of this page and select older document revision number.

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DateDocument Revision

Authors

Description

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modified-date
modified-date
dateFormatyyyy-MM-dd

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infoTypeCurrent version
dateFormatyyyy-MM-dd
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typeFlat

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...

infoTypeModified by
dateFormatyyyy-MM-dd
typeFlat

  • typo correction part name
  • typo correction on programming chapter
  • note pcie

v.9John Hartfiel
  • add -410 assembly variant

v.8John Hartfiel
  • 2018.2 release

v.6John Hartfiel
  • 2017.4 release
2018-02-08v.5John Hartfiel
  • 2017.2 release
2017-11-28v.1

...

  • Initial release

...

John Hartfiel
  • initial release
--all

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Modified users

...

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Legal Notices

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