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Overview
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Zynq PS Design with Linux for TE0701 with HDMI support.
Key Features
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- initial release
Release Notes and Know Issues
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Requirements
Software
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Hardware
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Basic description of TE Board Part Files is available on TE Board Part Files.
Complete List is available on <design name>/board_files/*_board_files.csv
Design supports following modules:
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1GB
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Design supports following carriers:
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- See restrictions on usage with 7 Series Carriers: 4 x 5 SoM Carriers
Additional HW Requirements:
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Content
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For general structure and of the reference design, see Project Delivery
Design Sources
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Overview
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Zynq PS Design with Linux for TE0701 with HDMI support.
Refer to http://trenz.org/te0720-info for the current online version of this manual and other available documentation.
Key Features
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Hardware
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Basic description of TE Board Part Files is available on TE Board Part Files.
Complete List is available on <design name>/board_files/*_board_files.csv
Design supports following modules:
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For general structure and of the reference design, see Project Delivery - AMD devices
Design Sources
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Additional Sources
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Prebuilt
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<tr> <td>BIF-File </td> <td>*.bif </td> <td>File with description to generate Bin-File </td> </tr>
<tr> <td>BIN-File </td> <td>*.bin </td> <td>Flash Configuration File with Boot-Image (Zynq-FPGAs) </td> </tr>
<tr> <td>BIT-File </td> <td>*.bit </td> <td>FPGA Configuration File </td> </tr>
<tr> <td>DebugProbes-File </td> <td>*.ltx </td> <td>Definition File for Vivado/Vivado Labtools Debugging Interface </td> </tr>
<tr> <td>Debian SD-Image </td> <td>*.img </td> <td>Debian Image for SD-Card </td> </tr>
<tr> <td>Diverse Reports </td> <td> --- </td> <td>Report files in different formats </td> </tr>
<tr> <td>Hardware-Platform-Specification-Files</td> <td>*.hdf </td> <td>Exported Vivado Hardware Specification for SDK/HSI </td> </tr>
<tr> <td>LabTools Project-File </td> <td>*.lpr </td> <td>Vivado Labtools Project File </td> </tr>
<tr> <td>MCS-File </td> <td>*.mcs </td> <td>Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only) </td> </tr>
<tr> <td>MMI-File </td> <td>*.mmi </td> <td>File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only) </td> </tr>
<tr> <td>OS-Image </td> <td>*.ub </td> <td>Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk) </td> </tr>
<tr> <td>Software-Application-File </td> <td>*.elf </td> <td>Software Application for Zynq or MicroBlaze Processor Systems </td> </tr>
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Reference Design is only usable with the specified Vivado/SDK/PetaLinux/SDx version. Do never use different Versions of Xilinx Software for the same Project.
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Reference Design is available on:
Design Flow
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Basic Design Steps
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Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first lunch. |
Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.
See also:
The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.
TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/SDK GUI. For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality
- _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
- Press 0 and enter for minimum setup
- (optional Win OS) Generate Virtual Drive or use short directory for the reference design (for example x:\<design name>)
- Create Project
- Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
Note: Select correct one, see TE Board Part Files
- Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
- Create HDF and export to prebuilt folder
- Run on Vivado TCL: TE::hw_build_design -export_prebuilt
Note: Script generate design and export files into \prebuilt\hardware\<short dir>. Use GUI is the same, except file export to prebuilt folder
- Run on Vivado TCL: TE::hw_build_design -export_prebuilt
- Create Linux (uboot.elf and image.ub) with exported HDF
- HDF is exported to "prebuilt\hardware\<short name>"
Note: HW Export from Vivado GUI create another path as default workspace. - Create Linux images on VM, see PetaLinux KICKstart
- Use TE Template from /os/petalinux
Note: run init_config.sh before you start petalinux config. This will set correct temporary path variable.
- Use TE Template from /os/petalinux
- HDF is exported to "prebuilt\hardware\<short name>"
- Add Linux files (uboot.elf and image.ub) to prebuilt folder
- "prebuilt\os\petalinux\default" or "prebuilt\os\petalinux\<short name>"
Notes: Scripts select "prebuilt\os\petalinux\<short name>", if exist, otherwise "prebuilt\os\petalinux\default"
- "prebuilt\os\petalinux\default" or "prebuilt\os\petalinux\<short name>"
- Generate Programming Files with HSI/SDK
- Run on Vivado TCL: TE::sw_run_hsi
Note: Scripts generate applications and bootable files, which are defined in "sw_lib\apps_list.csv" - (alternative) Start SDK with Vivado GUI or start with TE Scripts on Vivado TCL: TE::sw_run_sdk
Note: See SDK Projects
- Run on Vivado TCL: TE::sw_run_hsi
Launch
Programming
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Check Module and Carrier TRMs for proper HW configuration before you try any design. |
Xilinx documentation for programming and debugging: Vivado/SDK/SDSoC-Xilinx Software Programming and Debugging
QSPI
Not used on this Example.
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Reference Design is only usable with the specified Vivado/SDK/PetaLinux/SDx version. Do never use different Versions of Xilinx Software for the same Project.
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Reference Design is available on:
Design Flow
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Note |
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Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first lunch. |
Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.
See also:
- AMD Development Tools#XilinxSoftware-BasicUserGuides
- Vivado Projects - TE Reference Design
- Project Delivery.
The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.
TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/SDK GUI. For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality
- _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
- Press 0 and enter for minimum setup
- (optional Win OS) Generate Virtual Drive or use short directory for the reference design (for example x:\<design name>)
- Create Project
- Select correct device and Xilinx install path on "design_basic_settings.cmd"
...
- and
...
- create
...
- Vivado
...
- project
...
- with
...
- "vivado_create_project_guimode.cmd"
...
Note: Select correct one, see TE Board Part Files
- Create XSA and export to prebuilt folder
- Run on Vivado TCL: TE::hw_build_design -export_prebuilt
Note: Script generate design and export files into \prebuilt\hardware\<short dir>. Use GUI is the same, except file export to prebuilt folder
- Run on Vivado TCL: TE::hw_build_design -export_prebuilt
- Create Linux (uboot.elf and image.ub) with exported XSA
- XSA is exported to "prebuilt\hardware\<short name>"
Note: HW Export from Vivado GUI create another path as default workspace. - Create Linux images on VM, see PetaLinux KICKstart
- Use TE Template from /os/petalinux
- Build the Debian image/Ubuntu image file with executing the "mkdebian_stretch.sh"/"mkubuntu_BionicBeaver.sh" file in Linux Terminal
- XSA is exported to "prebuilt\hardware\<short name>"
- Add Linux files (uboot.elf and image.ub) to prebuilt folder
- "prebuilt\os\petalinux\<ddr size>" or "prebuilt\os\petalinux\<short name>"
- Generate Programming Files with Vitis
- Run on Vivado TCL: TE::sw_run_vitis -all
Note: Scripts generate applications and bootable files, which are defined in "sw_lib\apps_list.csv" - (alternative) Start SDK with Vivado GUI or start with TE Scripts on Vivado TCL: TE::sw_run_vitis
Note: TCL scripts generate also platform project, this must be done manuelly in case GUI is used. See Vitis
- Run on Vivado TCL: TE::sw_run_vitis -all
Launch
Programming
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Check Module and Carrier TRMs for proper HW configuration before you try any design. |
Xilinx documentation for programming and debugging: Vivado/SDK/SDSoC-Xilinx Software Programming and Debugging
Get prebuilt boot binaries
- _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell
- Press 0 and enter to start "Module Selection Guide"
- Select assembly version
- Validate selection
- Select Create and open delivery binary folder
Note: Folder (<project folder>/_binaries_<Articel Name>) with subfolder (boot_linux)
QSPI
Not used on this Example.
SD
- Format the SD Card with SD Card Formatter or other tool
- Write the Debian image or Ubuntu image file on SD Card with Win32DiskImager
- Copy Petalinux image.ub and Boot.bin on SD-Card.
- use files from (<project foler>/_binaries_<Articel Name>)/boot_linux from generated binary folder,see: Get prebuilt boot binaries
- or use prebuilt file location, see <design_name>/prebuilt/readme_file_location.txt
- Set Boot Mode to SD-Boot.
- Depends on Carrier, see carrier TRM.
- Insert SD-Card in SD-Slot.
JTAG
Not used on this Example.
Usage
- Prepare HW like described on section 46040563
- Connect UART USB (most cases same as JTAG)
- Select SD Card as Boot Mode
Note: On TE0701 Default Firmware Boot Mode is selected via SD card (insered SD Card for SD Boot Mode) - Connect HDMI to Monitor
- Connect USB Adapter with Hub and Mouse+Keyboard
- Power On PCB
Note: 1. Zynq Boot ROM loads FSBL from SD into OCM, 2. FSBL loads U-boot from SD into DDR, 3. U-boot load Linux from SD into DDR
Linux
- Open Serial Console (e.g. putty)
- Speed: 115200
- COM Port: Win OS, see device manager, Linux OS see dmesg |grep tty (UART is *USB1)
- Linux Console:
Note: Wait until Linux boot finished For Linux Login use:- User Name: root
- Password: root
- You can use Linux shell now.
- I2C 0 Bus type: i2cdetect -y -r 0
- I2C 1 Bus type: i2cdetect -y -r 1
- RTC check: dmesg | grep rtc
- ETH0 works with udhcpc
- USB: insert USB device
- Debian Desktop
- Debian Desktop will be started automatically
- Use connected mouse + keyboard for interaction with GUI
- Web Browser Dillo open console and type dillo or use browser
- open console and start video or audio with "mplayer <video or audio file>"
- Ubuntu Desktop
- Ubuntu Desktop will be started automatically
- Use connected mouse + keyboard for interaction with GUI
- Web Browser Mozilla firefox can be used.
- Audio or Vider file can also be performed directly in GUI.
HDMI Monitor
Second Linux GUI is displayed on HDMI monitor.
Vivado HW Manager
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Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder).
PHY LED:
System Design - Vivado
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Block Design
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PS Interfaces
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Constrains
Basic module constrains
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#
# Common BITGEN related settings for TE0720 SoM
#
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property CFGBVS VCCO [current_design |
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#
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLUP [current_design] |
Design specific constrain
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#
# Constraints for System controller support logic
#
set_property PACKAGE_PIN K16 [get_ports PL_pin_K16]
set_property PACKAGE_PIN K19 [get_ports PL_pin_K19]
set_property PACKAGE_PIN K20 [get_ports PL_pin_K20]
set_property PACKAGE_PIN L16 [get_ports PL_pin_L16]
set_property PACKAGE_PIN M15 [get_ports PL_pin_M15]
set_property PACKAGE_PIN N15 [get_ports PL_pin_N15]
set_property PACKAGE_PIN N22 [get_ports PL_pin_N22]
set_property PACKAGE_PIN P16 [get_ports PL_pin_P16]
set_property PACKAGE_PIN P22 [get_ports PL_pin_P22]
#
# If Bank 34 is not 2.5V Powered need change the IOSTANDARD
#
set_property IOSTANDARD LVCMOS25 [get_ports PL_pin*]
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#
# TE0701 I2C Bus
#
set_property PACKAGE_PIN W20 [get_ports IIC_0_scl_io]
set_property PACKAGE_PIN W21 [get_ports IIC_0_sda_io]
set_property IOSTANDARD LVCMOS25 [get_ports IIC_0_scl_io]
set_property IOSTANDARD LVCMOS25 [get_ports IIC_0_sda_io]
#
# ADV7511 Interface
#
set_property PACKAGE_PIN N20 [get_ports hdmi_out_clk]
set_property PACKAGE_PIN N19 [get_ports hdmi_out_de]
set_property PACKAGE_PIN R19 [get_ports hdmi_out_hsync]
set_property PACKAGE_PIN T19 [get_ports hdmi_out_vsync]
set_property PACKAGE_PIN T18 [get_ports {hdmi_out_data[0]}]
set_property PACKAGE_PIN R18 [get_ports {hdmi_out_data[1]}]
set_property PACKAGE_PIN R21 [get_ports {hdmi_out_data[2]}]
set_property PACKAGE_PIN R20 [get_ports {hdmi_out_data[3]}]
set_property PACKAGE_PIN M22 [get_ports {hdmi_out_data[4]}]
set_property PACKAGE_PIN K21 [get_ports {hdmi_out_data[5]}]
set_property PACKAGE_PIN M21 [get_ports {hdmi_out_data[6]}]
set_property PACKAGE_PIN J20 [get_ports {hdmi_out_data[7]}]
set_property PACKAGE_PIN T17 [get_ports {hdmi_out_data[8]}]
set_property PACKAGE_PIN J22 [get_ports {hdmi_out_data[9]}]
set_property PACKAGE_PIN T16 [get_ports {hdmi_out_data[10]}]
set_property PACKAGE_PIN J21 [get_ports {hdmi_out_data[11]}]
set_property IOSTANDARD LVCMOS25 [get_ports hdmi_*]
set_property PACKAGE_PIN AB16 [get_ports {cec_clk[0]}]
set_property PACKAGE_PIN AB17 [get_ports {ct_hpd[0]}]
set_property PACKAGE_PIN AA16 [get_ports {ls_oe[0]}]
set_property IOSTANDARD LVCMOS25 [get_ports {cec_clk[0]}]
set_property IOSTANDARD LVCMOS25 [get_ports {ct_hpd[0]}]
set_property IOSTANDARD LVCMOS25 [get_ports {ls_oe[0]}]
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Software Design - Vitis
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---------------------------------------------------------- FPGA Example scuMCS Firmware to configure SI5338 and Reset System. srec_spi_bootloaderTE modified 2019.2 SREC Bootloader to load app or second bootloader from flash into DDR Descriptions:
xilisf_v5_11TE modified 2019.2 xilisf_v5_11
---------------------------------------------------------- Zynq Example: zynq_fsblTE modified 2019.2 FSBL General:
Module Specific:
zynq_fsbl_flashTE modified 2019.2 FSBL General:
ZynqMP Example: ---------------------------------------------------------- zynqmp_fsblTE modified 2019.2 FSBL General:
Module Specific:
zynqmp_fsbl_flashTE modified 2019.2 FSBL General:
zynqmp_pmufwXilinx default PMU firmware. ---------------------------------------------------------- General Example: hello_te0820Hello TE0820 is a Xilinx Hello World example as endless loop instead of one console output. u-bootU-Boot.elf is generated with PetaLinux. Vitis is used to generate Boot.bin. |
zynq_fsbl
TE modified 2019.2 FSBL
General:
- Modified Files:main.c, fsbl_hooks.h/.c (search for 'TE Mod' on source code)
Add Files: te_fsbl_hooks.h/.c(for hooks and board)\n\
- General Changes:
- Display FSBL Banner and Device ID
Module Specific:
- Add Files: all TE Files start with te_*
- READ MAC from EEPROM and make Address accessible by UBOOT (need copy defines on uboot platform-top.h)
- CPLD access
- Read CPLD Firmware and SoC Type
- Configure Marvell PHY
- USB PHY Reset
- Configure LED usage
TE modified 2019.2 FSBL
General:
- Modified Files:main.c, fsbl_hooks.h/.c (search for 'TE Mod' on source code)
Add Files: te_fsbl_hooks.h/.c(for hooks and board)\n\
- General Changes:
- Display FSBL Banner and Device ID
Module Specific:
- Add Files: all TE Files start with te_*
- READ MAC from EEPROM and make Address accessible by UBOOT (need copy defines on uboot platform-top.h)
- CPLD access
- Read CPLD Firmware and SoC Type
- Configure Marvell PHY
- Configure ADV7511
- Configure Video Timing Controller core
- Configure VDMA core and enable transfers
zynq_fsbl_flash
TE modified 2019.2 FSBL
General:
- Modified Files: main.c
- General Changes:
- Display FSBL Banner
- Set FSBL Boot Mode to JTAG
- Disable Memory initialisation
U-Boot
U-Boot.elf is generated with PetaLinux. Vitis is used to generate Boot.bin.
Software Design - PetaLinux
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For PetaLinux installation and project creation, follow instructions from:
Config
Start with petalinux-config or petalinux-config --get-hw-description
Select Image Packaging Configuration ==> Root filesystem type ==> Select SD Card
Changes:
# CONFIG_SUBSYSTEM_ROOTFS_INITRAMFS is not set
# CONFIG_SUBSYSTEM_ROOTFS_INITRD is not set
# CONFIG_SUBSYSTEM_ROOTFS_JFFS2 is not set
# CONFIG_SUBSYSTEM_ROOTFS_NFS is not set
CONFIG_SUBSYSTEM_ROOTFS_SD=y
# CONFIG_SUBSYSTEM_ROOTFS_OTHER is not set
U-Boot
Start with petalinux-config -c u-boot
Changes:
- CONFIG_ENV_IS_NOWHERE=y
- # CONFIG_ENV_IS_IN_SPI_FLASH is not set
Change platform-top.h:
Code Block | ||
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#include <configs/platform-auto.h>
#define UBOOT_ENV_MAGIC 0xCAFEBABE
#define UBOOT_ENV_MAGIC_ADDR 0xFFFFFC00
#define UBOOT_ENV_ADDR 0xFFFFFC04
#define CONFIG_SYS_BOOTM_LEN 0xF000000
#define DFU_ALT_INFO_RAM \
"dfu_ram_info=" \
"setenv dfu_alt_info " \
"image.ub ram $netstart 0x1e00000\0" \
"dfu_ram=run dfu_ram_info && dfu 0 ram 0\0" \
"thor_ram=run dfu_ram_info && thordown 0 ram 0\0"
#define DFU_ALT_INFO_MMC \
"dfu_mmc_info=" \
"set dfu_alt_info " \
"${kernel_image} fat 0 1\\\\;" \
"dfu_mmc=run dfu_mmc_info && dfu 0 mmc 0\0" \
"thor_mmc=run dfu_mmc_info && thordown 0 mmc 0\0"
/*Required for uartless designs */
#ifndef CONFIG_BAUDRATE
#define CONFIG_BAUDRATE 115200
#ifdef CONFIG_DEBUG_UART
#undef CONFIG_DEBUG_UART
#endif
#endif
/*Dependencies for ENV to be stored in EEPROM. Ensure environment fits in eeprom size*/
#ifdef CONFIG_ENV_IS_IN_EEPROM
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x54
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
#define CONFIG_SYS_EEPROM_SIZE 1024 /* Bytes */
#define CONFIG_SYS_I2C_MUX_ADDR 0x74
#define CONFIG_SYS_I2C_MUX_EEPROM_SEL 0x4
#endif
#define CONFIG_PREBOOT "echo U-BOOT for petalinux;echo importing env from FSBL shared area at 0xFFFFFC00; if itest *0xFFFFFC00 == 0xCAFEBABE; then echo Found valid magic; env import -t 0xFFFFFC04; fi;setenv preboot; echo; dhcp"
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Device Tree
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/include/ "system-conf.dtsi"
/ {
};
/ {
memory { // Reduce memory for framebuffers
device_type = "memory";
reg = <0x0 0x3FC00000>; // Reduce memory for 1GB assembly variant
// reg = <0x0 0x1FC00000>; // Reduce memory for 1GB assembly variant
// reg = <0x0 0x0FC00000>; // Reduce memory for 1GB assembly variant
};
framebuffer0: framebuffer@0x3FC00000 { // HDMI out
compatible = "simple-framebuffer";
reg = <0x3FC00000 (1280 * 720 * 4)>; // 720p
width = <1280>; // 720p
height = <720>; // 720p
stride = <(1280 * 4)>; // 720p
format = "a8b8g8r8";
};
/*
framebuffer0: framebuffer@0x1FC00000 { // HDMI out
compatible = "simple-framebuffer";
reg = <0x1FC00000 (1280 * 720 * 4)>; // 720p
width = <1280>; // 720p
height = <720>; // 720p
stride = <(1280 * 4)>; // 720p
format = "a8b8g8r8";
};
*/
/*
framebuffer0: framebuffer@0x0FC00000 { // HDMI out
compatible = "simple-framebuffer";
reg = <0x0FC00000 (1280 * 720 * 4)>; // 720p
width = <1280>; // 720p
height = <720>; // 720p
stride = <(1280 * 4)>; // 720p
format = "a8b8g8r8";
};
*/
};
&axi_vdma_0 {
status = "disabled";
};
&v_tc_0 {
//xilinx-vtc: probe of 43c20000.v_tc failed with error -2
status = "disabled";
};
/* default */
/* QSPI PHY */
&qspi {
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
flash0: flash@0 {
compatible = "jedec,spi-nor";
reg = <0x0>;
#address-cells = <1>;
#size-cells = <1>;
};
};
/* ETH PHY */
&gem0 {
phy-handle = <&phy0>;
mdio {
#address-cells = <1>;
#size-cells = <0>;
phy0: phy@0 {
compatible = "marvell,88e1510";
device_type = "ethernet-phy";
reg = <0>;
} |
SD
- Copy image.ub and Boot.bin on SD-Card.
- For correct prebuilt file location, see <design_name>/prebuilt/readme_file_location.txt
- Set Boot Mode to SD-Boot.
- Depends on Carrier, see carrier TRM.
- Insert SD-Card in SD-Slot.
JTAG
Not used on this Example.
Usage
- Prepare HW like described on section 46040558
- Connect UART USB (most cases same as JTAG)
- Select SD Card as Boot Mode
Note: See TRM of the Carrier, which is used. - Power On PCB
Note: 1. Zynq Boot ROM loads FSBL from SD into OCM, 2. FSBL loads U-boot from SD into DDR, 3. U-boot load Linux from SD into DDR
Linux
- Open Serial Console (e.g. putty)
- Speed: 115200
- COM Port: Win OS, see device manager, Linux OS see dmesg |grep tty (UART is *USB1)
- Linux Console:
Note: Wait until Linux boot finished For Linux Login use:- User Name: root
- Password: root
- You can use Linux shell now.
- I2C 0 Bus type: i2cdetect -y -r 0
- I2C 1 Bus type: i2cdetect -y -r 1
- RTC check: dmesg | grep rtc
- ETH0 works with udhcpc
- USB: insert USB device
Vivado HW Manager
Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder).
PHY LED:
System Design - Vivado
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Block Design
PS Interfaces
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Constrains
Basic module constrains
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#
# Common BITGEN related settings for TE0720 SoM
#
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property CFGBVS VCCO [current_design |
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#
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLUP [current_design] |
Design specific constrain
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#
# Constraints for System controller support logic
#
set_property PACKAGE_PIN K16 [get_ports PL_pin_K16]
set_property PACKAGE_PIN K19 [get_ports PL_pin_K19]
set_property PACKAGE_PIN K20 [get_ports PL_pin_K20]
set_property PACKAGE_PIN L16 [get_ports PL_pin_L16]
set_property PACKAGE_PIN M15 [get_ports PL_pin_M15]
set_property PACKAGE_PIN N15 [get_ports PL_pin_N15]
set_property PACKAGE_PIN N22 [get_ports PL_pin_N22]
set_property PACKAGE_PIN P16 [get_ports PL_pin_P16]
set_property PACKAGE_PIN P22 [get_ports PL_pin_P22]
#
# If Bank 34 is not 3.3V Powered need change the IOSTANDARD
#
set_property IOSTANDARD LVCMOS33 [get_ports PL_pin_P22]
set_property IOSTANDARD LVCMOS33 [get_ports PL_pin_P16]
set_property IOSTANDARD LVCMOS33 [get_ports PL_pin_N22]
set_property IOSTANDARD LVCMOS33 [get_ports PL_pin_N15]
set_property IOSTANDARD LVCMOS33 [get_ports PL_pin_M15]
set_property IOSTANDARD LVCMOS33 [get_ports PL_pin_L16]
set_property IOSTANDARD LVCMOS33 [get_ports PL_pin_K20]
set_property IOSTANDARD LVCMOS33 [get_ports PL_pin_K19]
set_property IOSTANDARD LVCMOS33 [get_ports PL_pin_K16] |
Software Design - SDK/HSI
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For SDK project creation, follow instructions from:
Application
FSBL
TE modified 2017.2 FSBL
Functions:
- Read EEPROM MAC Address and make Address accessible by UBOOT (need defines on uboot platform-top.h)
- Read CPLD Firmware and SoC Type
- Configure Marvell PHY
Changes:
- Add te_fsbl_config.h,, te_fsbl_hooks.h te_fsbl_hooks.c, and includ into fsbl_hooks.c
U-Boot
U-Boot.elf is generated with PetaLinux. SDK/HSI is used to generate Boot.bin.
Software Design - PetaLinux
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For PetaLinux installation and project creation, follow instructions from:
Config
- Subsystem Auto Hardware Settings:Serial Settings: ps7_uart_0
U-Boot
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#include <configs/platform-auto.h>
#define UBOOT_ENV_MAGIC 0xCAFEBABE
#define UBOOT_ENV_MAGIC_ADDR 0xFFFFFC00
#define UBOOT_ENV_ADDR 0xFFFFFC04
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/include/ "system-conf.dtsi" / { }; /* default */ /* Flash */ &qspi { flash0: flash@0 { compatible = "w25q256"; }; }; /* ETHUSB PHY */ &gem0 /{ phy-handle = <&phy0>; usb_phy0: usb_phy@0 { mdio { compatible = "ulpi-phy"; #address-cells//compatible = <1>"usb-nop-xceiv"; #size#phy-cells = <0>; reg phy0:= phy@0<0xe0002000 {0x1000>; view-port = <0x0170>; compatible = "marvell,88e1510" drv-vbus; }; }; &usb0 { devicedr_typemode = "ethernet-phyhost"; //dr_mode = "peripheral"; regusb-phy = <0><&usb_phy0>; }; /* I2C need I2C1 connected to te0720 }; system controller ip }; }; /* USB PHY */ /{ usb_phy0: usb_phy@0 {*/ &i2c1 { iexp@20 { // GPIO in CPLD compatible#gpio-cells = "ulpi-phy"<2>; //compatible = "usb-nop-xceivti,pcf8574"; #phy-cellsreg = <0><0x20>; gpio-controller; reg = <0xe0002000 0x1000>}; iexp@21 { view-port = <0x0170>;// GPIO in CPLD #gpio-cells = drv-vbus<2>; }; }; &usb0 { compatible dr_mode = "hostti,pcf8574"; //dr_mode = "peripheral"; usb-phyreg = <&usb_phy0><0x21>; }; /* I2C need I2C1 connected to te0720 system controller ip */ &i2c1 { gpio-controller; }; iexp@20 { // GPIO in CPLD rtc@6F { // #gpio-cellsReal =Time <2>;Clock compatible = "ti,pcf8574isl12022"; reg = <0x20><0x6F>; gpio-controller; }; iexp@21 { // GPIO in CPLD #gpio-cells = <2>; compatible = "ti,pcf8574"; reg = <0x21>; gpio-controller; }; rtc@6F { // Real Time Clock compatible = "isl12022"; reg = <0x6F>; }; }; |
Kernel
Activate:
- RTC_DRV_ISL12022
Rootfs
Activate:
- i2c-tools
Applications
startup
Script App to load init.sh from SD Card if available.
See: \os\petalinux\project-spec\meta-user\recipes-apps\startup\files
Additional Software
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No additional software is needed.
Appx. A: Change History and Legal Notices
Document Change History
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};
};
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Kernel
Start with petalinux-config -c kernel
Changes:
- RTC_DRV_ISL12022
- CONFIG_FB_SIMPLE
- CONFIG_LOGO
- CONFIG_LOGO_LINUX_MONO
- CONFIG_LOGO_LINUX_VGA16
- CONFIG_LOGO_LINUX_CLUT224
Rootfs
File system will be generated with Debian script or Ubuntu script (mkdebian_stretch.sh/mkubuntu_BionicBeaver.sh)
Applications
Applications will be generated with Debian script or Ubuntu script (mkdebian_stretch.sh/mkubuntu_BionicBeaver.sh)
Additional Software
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No additional software is needed.
Appx. A: Change History and Legal Notices
Document Change History
To get content of older revision got to "Change History" of this page and select older document revision number.
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