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- Xilinx Artix-7 FPGA, U1
- 128K I2C CMOS serial EEPROM, U2
- Low-power programmable oscillator @25.000000 MHz, U3
- Cypress S26KS512S 512-Mbit (64-MByte) 1.8V HyperFlash™ memory, U4
- Low VIN high-efficiency step-down converter (1.5A max.), U5
- Low VIN high-efficiency step-down converter (1.5A max.), U6
- 1.8V, 256-MBit (32-MByte) quad SPI serial flash memory, U7
- Ultra-low supply-current voltage monitor with optional watchdog, U8
- 50-pin header placeholder for breadboard connector, J1
- 50-pin header placeholder for breadboard connector, J2
- 14-pin header placeholder for connector, J3
- JTAG/UART connector, JB1
- Red LED (SYSLED), D2
Initial Delivery State
On-board Programmable Device | Content | Notes | |
---|---|---|---|
Quad SPI Flash OTP area | Empty | ||
I2C EEPROM, U2 | Empty |
Boot Process
Boot...
Signals, Interfaces and Pins
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I/O signals connected to the SoCs I/O bank and B2B connector:
Bank | Type | B2B Connector | I/O Signal Count | Bank Voltage |
---|---|---|---|---|
34 | HR | J2 | 42 I/Os, 21 LVDS pairs | VCCIO34 |
35 | HR | J1 | 42 I/Os, 21 LVDS pairs | VCCIO35 |
Table x: General overview of PL I/O signals connected to the B2B connectors.
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Overview
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