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Xilinx Artix-7 XC7A100T FPGA
32 MByte QSPI Flash memory
2 x 50-pin headers with 2,54mm pitch, ideal for breadboard use
- 92 x GPIOs (42 + 42 + 8)
- 25.000000 MHz system clock
- 128 KBit (16 KByte) I2C EEPROM for FPGA bitstream
3.3V single power supply with on-board voltage regulators
JTAG/UART connector
1 user LED
- Optional HyperRAM (8 to 32 MByte)
- Commercial temperature grade (Industrial on Request)
- Size 73 x 35 mm
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- XMOD header, JB1
- 14-pin header placeholder for connector, J3
- Xilinx Artix-7 FPGA, U1
- 1.8V, 256 MBit (32 MByte) quad SPI serial flash memory, U7
- Red LED (SYSLED), D2
- Cypress S26KS512S 512 Mbit MBit (64 MByte) 1.8V HyperFlash™ memory, U4 (optional)
- Low-power programmable oscillator @25.000000 MHz, U3
- Low VIN high-efficiency step-down converter (1.5A max.), U5
- Low VIN high-efficiency step-down converter (1.5A max.), U6 (optional)
- 50-pin header placeholder for breadboard connector, J1
- 50-pin header placeholder for breadboard connector, J2
- Ultra-low supply-current voltage monitor with optional watchdog, U8
- 128K 128KBit I2C CMOS serial EEPROM, U2
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PL I/O-Banks
| Bank | VCCIO | Available I/O 's Count | B2B I/O Count On Connectors | Notes |
|---|---|---|---|---|
| 0 | 3.3V | 11 | 4 | 4 I/O's used for JTAG interface, 3 control signals (DONE, PROG_B, INIT). |
| 14 | 3.3V | 12 | 11 | 8 I/O's (4 LVDS pairs) connected to J3, 3 I/O's to XMOD header JB1 (2 UART I/O's, 1 user I/O), 1 I/O to LED D2. |
| 15 | 1.8V | 18 | 0 | Used for optional Hyper RAM HyperFlash™ U4. |
| 34 | User select | 42 | 42 | 0-Ohm resistor R17 option to select 1.8V I/O-bank VCCIO. |
| 35 | User select | 42 | 42 | 0-Ohm resistor R25 option to select 1.8V I/O-bank VCCIO. |
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Following table describes the signals and interfaces of the XMOD header JB1:
| Pin Schematic Name | XMOD Header JB1 Pin | Note |
|---|---|---|
| F_TCK | C (pin J3-4) | - |
| F_TDO | D (pin J3-8) | - |
| F_TDI | F (pin J3-10) | - |
| F_TMS | H (pin J3-12) | - |
| UART_RXD | A (pin J3-3) | UART receive line, connected to PL I/O-bank 14. |
| UART_TXD | B (pin J3-7) | UART transmit line, connected to PL I/O-bank 14. |
| XMOD_E | E (pin J3-9) | User configurable, connected to PL I/O-bank 14, pin M17. |
| NRST | G (pin J3-11) | Assigned to 'PROG_B' (configuration-reset |
| signal of FPGA) via IC U8. |
Table 6: XMOD header JX1 signals and connections.
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For this configuration, set the XMOD DIP-switch as follows in table below:
| XMOD DIP-switches | Position |
|---|---|
| Switch 1 | ON |
| Switch 2 | OFF |
| Switch 3 | OFF |
| Switch 4 | ON |
Table 7: XMOD adapter board DIP-switch positions for voltage configuration.
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UART interface is available on B2B connector JM2. With the TE0790 XMOD USB2.0 adapter, the UART signals can be converted to USB2.0 interface signals:
| UART Signal Schematic Name | B2B | XMOD Header JX1 | Pin Header J3 | Note |
|---|---|---|---|---|
| B14_L0 | JM2-99 | JX1-7 | J3-7 | UART-TX (transmit line) |
| B14_L25 | JM2-97 | JX1-3 | J3-3 | UART-RX (receive line) |
Table 10: UART interface signals.
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The QSPI interface of the FPGA device is routed to and used by the on-module QSPI flash IC U7:
| SD IO Signal Schematic Name | FPGA I/O | Flash IC U7 Pin | Note |
|---|---|---|---|
| SPI-DQO | Bank 14, pin K17 | D3 | QSPI data |
| SPI-DQ1 | Bank 14, pin K18 | D2 | QSPI data |
| SPI-DQ2 | Bank 14, pin L14 | C4 | QSPI data |
| SPI-DQ3 | Bank 14, pin M14 | D4 | QSPI data |
| SPI_SCK | Bank 0, pin E9 | B2 | QSPI clock |
| SPI-CS | Bank 14, pin L13 | C2 | QSPI chip select |
Table 11: QSPI interface signals.
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The I2C interface of the FPGA device is routed to and used by the on-module EEPROM IC U2:
| I²C Signal Schematic Name | FPGA I/O | EEPROM IC U2 Pin | Notes |
|---|---|---|---|
| I2C_SDA | Bank 14, pin U18 | 5 | I²C data line, 1.8V reference voltage |
| I2C_SCL | Bank 14, pin U17 | 6 | I²C clock line, 1.8V reference voltage |
| I2C_WP | Bank 14, pin T18 | 7 | Write-protect signal of EEPROM |
Table 10: I2C interface signals.
Differential Analog Input
The TE0725LP FPGA module provides access to the XADC (Analog-to-Digital Converter) unit of the Xilinx FPGA via connector J3:
| I²C Signal Schematic Name | FPGA I/O | Connector J3 pin | Notes |
|---|---|---|---|
| XADC_P | Bank 0, pin J10 (VP_0) | J3-14 | - |
| XADC_N | Bank 0, pin K9 (VN_0) | J3-13 | - |
Table 10: XADC interface signals.
On-board Peripherals
Quad SPI Flash Memory
On-module QSPI flash memory (U7) is provided by Micron Serial NOR Flash Memory N25Q256A with 256 Mbit MBit (32 MByte) storage capacity. This non volatile memory is used to store initial FPGA configuration. Besides FPGA configuration, remaining free flash memory can be used for user application and data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths. Maximum data rate depends on the selected bus width and clock frequency used.
HyperFlash™ Memory
On the TE0725LP FPGA module is optionally available a Cypress S26KS512S 512 MBit (64 MByte) 1.8V HyperFlash™ memory IC (U4).
HyperFlash RAM
Configaration EEPROM
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This flash memory IC is connected to the FPGA bank 15 via the Cypress specific HyperBus interface, which offers read bandwidth up to 333MByete/s.
EEPROM
A Microchip 24AA128 128 KBit (16 KByte) CMOS Serial EEPROM (U2). The device is organized as eight blocks of 16 KBit memory with a 2-wire serial interface connected on FPGA bank 14. The memory as is available for application use. It is accessible over I2C bus with slave device address 0x50.
System Clock Oscillator
A low-power SiTime programmable oscillator (U3) configured on-module @25.000000 MHz is connected to PL I/O-bank 14 and provides the system reference clock signal for the FPGA PL.
On-board LEDs
There is one red LED connected to the FPGA bank 14, pin M16. This LED is user configurable to indicate for example any system status.
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