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Design Name is always "TE Series Name" + Design name, for example "TE0720 Test Board"
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Important General Note:
Export PDF to download, if vivado revision is changed!
Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro
Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)Figure template (note: inner scroll ignore/only only with drawIO object):
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image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed |
Table template:
- Layout macro can be use for landscape of large tables
- Set column width manually (can be used for small tables to fit over whole page) or leave empty (automatically)
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Overview
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Refer to http://trenz.org/te0808-info for the current online version of this manual and other available documentation.
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Refer to http://trenz.org/te0808-info for the current online version of this manual and other available documentation.
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2021-05-12 | 2020.2 | TE0808-StarterKit-vivado_2020.2-build_5_20210512133800.zip TE0808-StarterKit_noprebuilt-vivado_2020.2-build_5_20210512133822.zip | John Hartfiel |
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2021-02-05 | 2020.2 | TE0808-StarterKit-vivado_2020.2-build_1_20210205120058.zip TE0808-StarterKit_noprebuilt-vivado_2020.2-build_1_20210205120122.zip | John Hartfiel |
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2021-02-05 | 2020.2 | TE0808-StarterKit_noprebuilt-vivado_2020.2-build_1_20210204142828.zip TE0808-StarterKit-vivado_2020.2-build_1_20210204142713.zip | John Hartfiel |
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2020-09-29 | 2019.2 | TE0808-StarterKit_noprebuilt-vivado_2019.2-build_15_20200928195324.zip TE0808-StarterKit-vivado_2019.2-build_15_20200928195304.zip | John Hartfiel |
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2020-09-22 | 2019.2 | TE0808-StarterKit_noprebuilt-vivado_2019.2-build_14_20200922071643.zip TE0808-StarterKit-vivado_2019.2-build_14_20200922071704.zip | John Hartfiel |
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2020-03-25 | 2019.2 | TE0808-StarterKit_noprebuilt-vivado_2019.2-build_8_20200325083508.zip TE0808-StarterKit-vivado_2019.2-build_8_20200325083436.zip | John Hartfiel |
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2020-01-22 | 2019.2 | TE0808-StarterKit_noprebuilt-vivado_2019.2-build_3_20200122142340.zip TE0808-StarterKit-vivado_2019.2-build_3_20200122142318.zip | John Hartfiel |
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2019-08-09 | 2018.3 | TE0808-StarterKit_noprebuilt-vivado_2018.3-build_07_20190809131638.zip TE0808-StarterKit-vivado_2018.3-build_07_20190809131620.zip | John Hartfiel |
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2019-05-07 | 2018.3 | TE0808-StarterKit_noprebuilt-vivado_2018.3-build_05_20190507124429.zip TE0808-StarterKit-vivado_2018.3-build_05_20190507124418.zip | John Hartfiel |
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2018-07-11 | 2018.2 | TE0808-StarterKit_noprebuilt-vivado_2018.2-build_02_20180711091558.zip TE0808-StarterKit-vivado_2018.2-build_02_20180711091049.zip | John Hartfiel |
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2018-05-24 | 2017.4 | TE0808-StarterKit_noprebuilt-vivado_2017.4-build_10_20180524091231.zip TE0808-StarterKit-vivado_2017.4-build_10_20180524091208.zip | John Hartfiel |
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2018-03-29 | 2017.4 | TE0808-StarterKit_noprebuilt-vivado_2017.4-build_07_20180329145308.zip TE0808-StarterKit-vivado_2017.4-build_07_20180329145246.zip | John Hartfiel |
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2018-02-06 | 2017.4 | TE0808-StarterKit_noprebuilt-vivado_2017.4-build_05_20180206082740.zip TE0808-StarterKit-vivado_2017.4-build_05_20180206082722.zip | John Hartfiel |
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2018-02-05 | 2017.4 | TE0808-StarterKit_noprebuilt-vivado_2017.4-build_05_20180205083231.zip TE0808-StarterKit-vivado_2017.4-build_05_20180205083208.zip | John Hartfiel |
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2018-01-17 | 2017.4 | TE0808-StarterKit-vivado_2017.4-build_05_20180117094213.zip TE0808-StarterKit_noprebuilt-vivado_2017.4-build_05_20180117094231.zip | John Hartfiel |
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2018-01-15 | 2017.4 | TE0808-StarterKit-vivado_2017.4-build_03_20180115092306.zip | John Hartfiel |
| 2017-12-18 | 2017
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- initial release
Release Notes and Know Issues
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title | Known Issues |
Do not use HW Manager connection, or if debugging is necessary:
- Boot linux with usb terminal
- From the terminal: root root mount ifconfig eth0
- Open two new SSH terminals via ethernet: root root , run user application ...
- Exit and close the usb terminal
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Software
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Basic description of TE Board Part Files is available on TE Board Part Files.
Complete List is available on "<project folder>\board_files\*_board_files.csv"
Design supports following modules:
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*used as reference |
Additional HW Requirements:
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*used as reference |
Content
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For general structure and of the reference design, see Project Delivery - AMD devices
Design Sources
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Prebuilt
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Download
Reference Design is only usable with the specified Vivado/Vitis/PetaLinux version. Do never use different Versions of Xilinx Software for the same Project.
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Design Flow
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Note |
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Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first launch. |
See also:
- AMD Development Tools#XilinxSoftware-BasicUserGuides
- Vivado Projects - TE Reference Design
- Project Delivery.
The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.
TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/Vitis GUI. For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality
Note |
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Caution! Win OS has a 260 character limit for path lengths which can affect the Vivado tools. To avoid this issue, use Virtual Drive or the shortest possible names and directory locations for the reference design (for example "x:\<project folder>") |
Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
Code Block language bash theme Midnight title _create_win_setup.cmd/_create_linux_setup.sh ------------------------Set design paths---------------------------- -- Run Design with: _create_win_setup -- Use Design Path: <absolute project path> ----
Requirements
Software
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anchor | Table_SW |
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title-alignment | center |
title | Software |
Hardware
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Notes :
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Basic description of TE Board Part Files is available on TE Board Part Files.
Complete List is available on "<project folder>\board_files\*_board_files.csv"
Design supports following modules:
anchor | Table_HWM |
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title-alignment | center |
title | Hardware Modules |
Note: Design contains also Board Part Files for TE0808 only configuration, this board part files are not used for this reference design.
Design supports following carriers:
anchor | Table_HWC |
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title-alignment | center |
title | Hardware Carrier |
Additional HW Requirements:
anchor | Table_AHW |
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title-alignment | center |
title | Additional Hardware |
Optional HW
Not all monitors are supported, also Adapter to other Standard can make trouble.
Design was tested with DELL U2412M
Can be used to get access to console which is show on Display Port
USB was tested with USB memory stick
Ethernet works with DHCP, but can be setup also manually
Content
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Notes :
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For general structure and of the reference design, see Project Delivery - Xilinx devices
Design Sources
anchor | Table_DS |
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title-alignment | center |
title | Design sources |
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<project folder>\constraints
<project folder>\ip_lib
<project folder>\board_files
Additional Sources
anchor | Table_ADS |
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title-alignment | center |
title | Additional design sources |
Prebuilt
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id | Comments |
Notes :
anchor | Table_PF |
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title-alignment | center |
title | Prebuilt files |
File
File-Extension
Description
Distro Boot file
Debian SD-Image
*.img
Debian Image for SD-Card
MCS-File
*.mcs
Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)
MMI-File
*.mmi
File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)
SREC-File
*.srec
Converted Software Application for MicroBlaze Processor Systems
anchor | Table_PF |
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title-alignment | center |
title | Prebuilt files (only on ZIP with prebult content) |
File
File-Extension
Description
Distro Boot file
Download
Reference Design is only usable with the specified Vivado/Vitis/PetaLinux version. Do never use different Versions of Xilinx Software for the same Project.
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Design Flow
scroll-pdf | true |
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scroll-office | true |
scroll-chm | true |
scroll-docbook | true |
scroll-eclipsehelp | true |
scroll-epub | true |
scroll-html | true |
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Notes :
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Note |
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Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first launch. |
See also:
The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.
TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/Vitis GUI. For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality
Note |
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Caution! Win OS has a 260 character limit for path lengths which can affect the Vivado tools. To avoid this issue, use Virtual Drive or the shortest possible names and directory locations for the reference design (for example "x:\<project folder>") |
Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
Code Block language bash theme Midnight title _create_win_setup.cmd/_create_linux_setup.sh ------------------------Set design paths---------------------------- -- Run Design with: _create_win_setup -- Use Design Path: <absolute project path> ---------------------------------------------------------------------------- -------------------------TE Reference Design--------------------------- -------------------------------------------------------------------- -- (0) Module selection guide, project creation...prebuilt export... -- (1) Create minimum setup of CMD-Files and exit Batch -- (2) Create maximum setup of CMD-Files and exit Batch -- (3) (internal only) Dev -- (4) (internal only) Prod -- (c) Go to CMD-File Generation (Manual setup) -- (d) Go to Documentation (Web Documentation) -- (g) Install Board Files from Xilinx Board Store (beta) -- (a) Start design with unsupported Vivado Version (beta) -- (x) Exit Batch (nothing is done!) ---- Select (ex.:'0' for module selection guide):
- Press 0 and enter to start "Module Selection Guide"
- Create Project (follow instruction of the product selection guide), settings file will be configured automatically during this process
- (optional for manual changes) Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
Note: Select correct one, see TE Board Part Files
Important: Use Board Part Files, which ends with *_tebf0808
- (optional for manual changes) Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
Documentation) -- (g) Install Board Files from Xilinx Board Store (beta) -- (a) Start design with unsupported Vivado Version (beta) -- (x) Exit Batch (nothing is done!) ---- Select (ex.:'0' for module selection guide):
- Press 0 and enter to start "Module Selection Guide"
- Create project and follow instructions of the product selection guide, settings file will be configured automatically during this process.
optional for manual changes: Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
Note Note: Select correct one, see also Vivado Board Part Flow
Important: Use Board Part Files, which ends with *_tebf0808
Create hardware description file (.xsa file) for PetaLinux project and export to prebuilt folder
Code Block language py theme Midnight title run on Vivado TCL (Script generates design and export files into "<project folder>\prebuilt\hardware\<short name>") TE::hw_build_design -export_prebuilt
Info Using Vivado GUI is the same, except file export to prebuilt folder.
- Create and configure your PetaLinux project with exported .xsa-file, see PetaLinux KICKstart
- use TE Template from "<project folder>\os\petalinux"
use exported .xsa file from "<project folder>\prebuilt\hardware\<short name>" . Note: HW Export from Vivado GUI creates another path as default workspace.
The build images are located in the
- Create and configure your PetaLinux project with exported .xsa-file, see PetaLinux KICKstart
- use TE Template from "<project folder>\os\petalinux"
use exported .xsa file from "<project folder>\prebuilt\hardware\<short name>" . Note: HW Export from Vivado GUI creates another path as default workspace.
The build images are located in the "<plnx-proj-root>/images/linux" directory
Configure the boot.scr file as needed, see Distro Boot with Boot.scr
- Copy PetaLinux build image files to prebuilt folder
copy u-boot.elf, bl31.elf, image.ub and boot.scr from "<plnx-proj-root>/images/linux" to prebuilt folder
Info "<project folder>\prebuilt\os\petalinux\<ddr size>" or "<project folder>\prebuilt\os\petalinux\<short name>"
Page properties hidden true id Comments This step depends on Xilinx Device/Hardware
for Zynq-7000 series
copy u-boot.elf, image.ub and boot.scr from"<plnx-proj-root>/images/linux" directory
Configure the boot.scr file as needed, see Distro Boot with Boot.scr
- Generate Programming Files with Vitis (recommended)
- Copy PetaLinux build image files to prebuilt folder
- copy u-boot.elf, system.dtb, bl31.elf, image.ub and boot.scr from "<plnx-proj-root>/images/linux" to prebuilt folder
- copy u-boot.elf, system.dtb, bl31.elf, image.ub and boot.scr from "<plnx-proj-root>/images/linux" to prebuilt folder
for ...
- ...
Generate Programming Files
Code Block language py theme Midnight title run on Vivado TCL (Script generates applications and bootable files, which are defined in "test_board\sw_lib\apps_list.csv") TE::sw_run_vitis -all TE::sw_run_vitis (optional; Start Vitis from Vivado GUI or start with TE Scripts on Vivado TCL)
Note TCL scripts generate also platform project, this must be done manually in case GUI is used. See Vitis
- Generate Programming Files with Petalinux (alternative), see PetaLinux KICKstart
Create hardware description file (.xsa file) for PetaLinux project and export to prebuilt folder
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Launch
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For basic board setup, LEDs... see: TEBF0808 Getting Started
Programming
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Get prebuilt boot binaries
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For basic board setup, LEDs... see: TEBF0808 Getting Started
Programming
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Get prebuilt boot binaries
- Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell
- Press 0 and enter to start "Module Selection Guide"
- Select assembly version
- Validate selection
Select create and open delivery binary folder
Info Note: Folder
Select create and open delivery binary folder
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Note: Folder "<project folder>\_binaries_<Article Name>" with subfolder "boot_<app name>" for different applications will be generated |
QSPI-Boot mode
Option for Boot.bin on QSPI Flash and image.ub and boot.scr on SD or USB.
- Connect JTAG and power on carrier with module
Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"
Code Block language py theme Midnight title run on Vivado TCL (Script programs BOOT.bin on QSPI flash) TE::pr_program_flash -swapp u-boot TE::pr_program_flash -swapp hello_te0808 (optional)
Copy image.ub and boot.scr on SD or USBNote To program with Vitis/Vivado GUI, use special FSBL (zynqmp_fsbl_flash) on setup
use files from"<project folder>\_binaries_<Article Name>
" with subfolder "boot_
<app name>" for different applications will be generated
QSPI-Boot mode
Option for Boot.bin on QSPI Flash.
- Connect JTAG and power on carrier with module
Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"
Code Block language py theme Midnight title run on Vivado TCL (Script programs BOOT.bin on QSPI flash) TE::pr_program_flash -swapp hello_te0808
- Set Boot Mode to QSPI-Boot and insert SD or USB.
- Depends on Carrier, see carrier TRM.
- TEBF0808 change automatically the Boot Mode to SD, if SD is inserted, optional CPLD Firmware without Boot Mode changing for microSD Slot is available on the download area
SD-Boot mode
- Copy image.ub, boot.srcscr and Boot.bin on SD
- use files from "<project folder>\_binaries_<Article Name>\boot_linux" from generated binary folder, see: Get prebuilt boot binaries
- or use prebuilt file location, see "<project folder>\prebuilt\file_location.txt"
- Set Boot Mode to SD-Boot.
- Depends on Carrier, see carrier TRM.
- Insert SD-Card in SD-Slot.
JTAG
Not used on this Example.
Usage
- Prepare HW like described on section Programming
- Connect UART USB (most cases same as JTAG)
Select SD Card as Boot Mode (or QSPI - depending on step 1)
Info Note: See TRM of the Carrier, which is used.
Tip Starting with Petalinux version 2020.1, the industry standard "Distro-Boot" boot flow for U-Boot was introduced, which significantly expands the possibilities of the boot process and has the primary goal of making booting much more standardised and predictable.
The boot options described above describe the common boot processes for this hardware; other boot options are possible.
For more information see Distro Boot with Boot.scr- (Optional with TEBF0808) Insert PCIe Card (detection depends on Linux driver. Only some basic drivers are installed)
- (Optional with TEBF0808) Connect SATA Disc
- (Optional with TEBF0808) Connect Display Port Monitor (List of usable Monitors: https://www.xilinx.com/support/answers/68671.html)
- (Optional with TEBF0808) Connect Network Cable
Power On PCB
Expand title boot process 1. ZynqMP Boot ROM loads FSBL from SD/QSPI into OCM,
2. FSBL init the PS, programs the PL using the bitstream and loads PMU, ATF and U-boot from SD/QSPI into DDR,
3. U-boot loads Linux (image.ub) from SD/QSPI/... into DDR
Linux
- Open Serial Console (e.g. putty)
- Speed: 115200
select COM Port
Info Win OS, see device manager, Linux OS see dmesg |grep tty (UART is *USB1)
Linux Console:
Code Block language bash theme Midnight # password disabled petalinux login: root Password: root
Info Note: Wait until Linux boot finished
You can use Linux shell now.
Code Block language bash theme Midnight theme Midnight i2cdetect -y -r 0 (check I2C 0 Bus, replace 0 with other bus number is also possible) dmesg | grep rtc (RTC checki2cdetect -y -r 0 (check I2C 1 Bus) udhcpc (ETH0 check) lsusb (USB check) lspci (PCIe check)
Option Features
- Webserver to get access to ZynqZynqMP
- insert IP on web browser to start web interface
- init.sh scripts
- add init.sh script on SD, content will be load automatically on startup (template included in "<project folder>\misc\SD")
- Webserver to get access to ZynqZynqMP
Vivado Hardware Manager
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RGPIO Interface (Important: CPLD Firmware REV07 or newer is needed) for Control and Monitoring:
- Set Enable to send Write date over RGPIO interface.
- Important use CPLD Firmware REV07 or newer: https://wiki.trenz-electronic.de/display/PD/TEBF0808+CPLD
- Buttons, LEDs, Status...
- Important use CPLD Firmware REV07 or newer: https://wiki.trenz-electronic.de/display/PD/TEBF0808+CPLD
- Set Enable to send Write date over RGPIO interface.
- Control:
- LEDs: XMOD 2 (without green dot) and HD LED are accessible.
- CAN_S
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System Design - Vivado
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PS Interfaces
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Constrains
Basic module constrains
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set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] set_property BITSTREAM.CONFIG.UNUSEDPIN PULLNONE [current_design] |
Design specific constrain
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#System Controller IP #LED_HD SC0 J3:31 #LED_XMOD SC17 J3:48 #CAN RX SC19 J3:52 B47_L2_P in #CAN TX SC18 J3:50 B47_L2_N out #CAN S SC16 J3:46 B47_L3_N out set_property PACKAGE_PIN J14 [get_ports BASE_sc0] set_property PACKAGE_PIN G13 [get_ports BASE_sc5] set_property PACKAGE_PIN J15 [get_ports BASE_sc6] set_property PACKAGE_PIN K15 [get_ports BASE_sc7] set_property PACKAGE_PIN A15 [get_ports BASE_sc10_io] set_property PACKAGE_PIN B15 [get_ports BASE_sc11] set_property PACKAGE_PIN C13 [get_ports BASE_sc12] set_property PACKAGE_PIN C14 [get_ports BASE_sc13] set_property PACKAGE_PIN E13 [get_ports BASE_sc14] set_property PACKAGE_PIN E14 [get_ports BASE_sc15] #CAN S SC16 J3:46 B47_L3_N out #HDIO_SC1 K14 #HDIO_SC2 H13 #HDIO_SC3 H14 #HDIO_SC4 F13 #HDIO_SC0 J14 set_property PACKAGE_PIN A13J14 [get_ports BASE_sc16]sc0] #HDIO_SC5 G13 set_property PACKAGE_PIN B13G13 [get_ports BASE_sc17sc5] #HDIO_SC6 J15 set_property PACKAGE_PIN A14J15 [get_ports BASE_sc18]sc6] #HDIO_SC7 K15 set_property PACKAGE_PIN B14K15 [get_ports BASE_sc19sc7] #HDIO_SC10 A15 set_property IOSTANDARDPACKAGE_PIN LVCMOS18A15 [get_ports BASE_sc0]sc10_io] #HDIO_SC11 B15 set_property IOSTANDARDPACKAGE_PIN LVCMOS18B15 [get_ports BASE_sc5sc11] #HDIO_SC12 C13 set_property IOSTANDARDPACKAGE_PIN LVCMOS18C13 [get_ports BASE_sc6]sc12] #HDIO_SC13 C14 set_property IOSTANDARDPACKAGE_PIN LVCMOS18C14 [get_ports BASE_sc7sc13] #HDIO_SC14 E13 set_property IOSTANDARDPACKAGE_PIN LVCMOS18E13 [get_ports BASE_sc10_io]sc14] #HDIO_SC15 E14 set_property IOSTANDARDPACKAGE_PIN LVCMOS18E14 [get_ports BASE_sc11sc15] #HDIO_SC16 A13 set_property IOSTANDARDPACKAGE_PIN LVCMOS18A13 [get_ports BASE_sc12]sc16] #HDIO_SC17 B13 set_property IOSTANDARDPACKAGE_PIN LVCMOS18B13 [get_ports BASE_sc13sc17] #HDIO_SC18 A14 set_property IOSTANDARDPACKAGE_PIN LVCMOS18A14 [get_ports BASE_sc14]sc18] #HDIO_SC19 B14 set_property IOSTANDARDPACKAGE_PIN LVCMOS18B14 [get_ports BASE_sc15sc19] set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc16sc0] set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc17sc5] set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc18sc6] set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc19sc7] # PLL #setset_property PACKAGE_PINIOSTANDARD AH6LVCMOS18 [get_ports {si570BASE_clk_p[0]}sc10_io] #setset_property IOSTANDARD LVDSLVCMOS18 [get_ports {si570_clk_p[0]}BASE_sc11] #setset_property IOSTANDARD LVDSLVCMOS18 [get_ports {si570_clk_n[0]}] # Clocks #setBASE_sc12] set_property PACKAGE_PINIOSTANDARD J8LVCMOS18 [get_ports {B229_CLK1_clk_p[0]}BASE_sc13] #setset_property PACKAGE_PINIOSTANDARD F25LVCMOS18 [get_ports {B128_CLK0_clk_p[0]}] # SFP #setBASE_sc14] set_property PACKAGE_PINIOSTANDARD G8LVCMOS18 [get_ports {B230_CLK0_clk_p}] # B230_RX3_P #setBASE_sc15] set_property PACKAGE_PINIOSTANDARD A4LVCMOS18 [get_ports {SFP1BASE_rxp}sc16] # B230_TX3_P #set_property PACKAGE_PIN A8set_property IOSTANDARD LVCMOS18 [get_ports {SFP1BASE_txp}sc17] # B230_RX2_P #set_property PACKAGE_PIN B2set_property IOSTANDARD LVCMOS18 [get_ports {SFP2BASE_rxp}sc18] # B230_TX2_P #setset_property PACKAGE_PINIOSTANDARD B6LVCMOS18 [get_ports {SFP2BASE_txp}sc19] # Audio Codec #LRCLK J3:49 B47_L9_N #BCLK J3:51 B47_L9_P #DAC_SDATA J3:53 B47_L7_N #ADC_SDATA J3:55 B47_L7_P #LRCLK G14 set_property PACKAGE_PIN G14 [get_ports LRCLKI2S_lrclk ] #BCLK G15 set_property PACKAGE_PIN G15 [get_ports BCLKI2S_bclk ] #DAC_SDATA E15 set_property PACKAGE_PIN E15 [get_ports DACI2S_sdin ] #ADC_SDATA ]F15 set_property PACKAGE_PIN F15 [get_ports ADCI2S_SDATAsdout ] set_property IOSTANDARD LVCMOS18 [get_ports LRCLK I2S_lrclk ] set_property IOSTANDARD LVCMOS18 [get_ports BCLKI2S_bclk ] set_property IOSTANDARD LVCMOS18 [get_ports DACI2S_SDATAsdin ] set_property IOSTANDARD LVCMOS18 [get_ports ADCI2S_SDATAsdout ] |
Software Design - Vitis
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---------------------------------------------------------- FPGA Example | ||||
----------------------------------------------------------FPGA Example scuMCS Firmware to configure SI5338 and Reset System. srec_spi_bootloaderTE modified 20202023.2 SREC Bootloader to load app or second bootloader from flash into DDR Descriptions:
xilisf_v5_11TE modified 2020.2 xilisf_v5_11 Changed default Flash type to 5.xilisf_v5_11TE modified 2023.2 xilisf_v5_11
---------------------------------------------------------- Zynq Example: ----------------------------------------------------------Zynq Example: fsblTE modified 20202023.2 FSBL General:
Module Specific:
fsbl_flashTE modified 2020.2 FSBL General:
---------------------------------------------------------- ZynqMP Example: ---------------------------------------------------------- zynqmp_fsblTE modified 20202023.2 FSBL General:
Module Specific:
zynqmp_fsbl_flashTE modified 2020.2 FSBL General:
zynqmp_pmufwXilinx default PMU firmware. ---------------------------------------------------------- General Example: ---------------------------------------------------------- hello_te0820Hello TE0820 is a Xilinx Hello World example as endless loop instead of one console output. u-bootU-Boot.elf is generated with PetaLinux. Vitis is used to generate Boot.bin. |
zynqmp_fsbl
TE modified 20202023.2 FSBL
General:
- Modified Files: xfsbl_main.c, xfsbl_hooks.h/.c, xfsbl_board.h/.c (search for 'TE Mod' on source code)
- Add Files: te_xfsbl_hooks.h/.c (for hooks and board)
- General Changes:
- Display FSBL Banner and Device Name
Module Specific:
- Add Files: all TE Files start with te_*
- Si5345 Configuration
- OTG+PCIe Reset over MIO
- I2C MUX for EEPROM MAC
zynqmp_fsbl_flash
TE modified 2020.2 FSBL
General:
- Modified Files: xfsbl_initialisation.c, xfsbl_hw.h, xfsbl_handoff.c, xfsbl_main.c
- General Changes:
- Display FSBL Banner
- Set FSBL Boot Mode to JTAG
- Disable Memory initialisationEEPROM MAC
zynqmp_pmufw
Xilinx default PMU firmware.
hello_te0808
Hello TE0808 is a Xilinx Hello World example as endless loop instead of one console output.
u-boot
U-Boot.elf is generated with PetaLinux. Vitis is used to generate Boot.bin.
Software Design - PetaLinux
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Config
Start with petalinux-config or petalinux-config --get-hw-description
Changes:
- select SD default instead of eMMC:
- CONFIG_SUBSYSTEM_PRIMARY_SD_PSU_SD_1
- _SELECT=y
- add new flash partition for bootscr and sizing
- CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_PART0_SIZE=0xA00000
- CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_PART1_SIZE=0x2000000
- CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_PART2_SIZE=0x40000
- CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_PART3_NAME="bootscr"
- CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_PART3_SIZE=0x80000
- Identification
- CONFIG_SUBSYSTEM_
- HOSTNAME="Trenz"
- CONFIG_SUBSYSTEM_PRODUCT="TE0808_TEBF0808"
U-Boot
Start with petalinux-config -c u-boot
Changes:
- MAC from eeprom together with uboot and device tree settings:
- CONFIG_
- ENV_
- OVERWRITE=y
- CONFIG_
- NVMEM=y
- CONFIG_
- DM_RTC=y (needed for nvmem driver because of bug in uboot)
- Boot Modes:
- CONFIG_
- QSPI_BOOT=y
- CONFIG_
- SD_
- BOOT=
- y
- CONFIG_
- ENV_
- IS_
- IN_FAT is not set
- CONFIG_
- ENV_
- IS_
- IN_NAND is not set
- CONFIG_
- ENV_
- IS_
- IN_
- SPI_FLASH is not set
- CONFIG_
- BOOT_
- SCRIPT_OFFSET=0x2A40000
- Identification
- CONFIG_
- IDENT_
- STRING=" TE0808_TEBF0808"
Change platform-top.h:
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/include/ "system-conf.dtsi" / { chosen { xlnx,eeprom = &eeprom; }; }; /* notes: serdes: https://github.com/Xilinx/linux-xlnx/blob/master/Documentation/devicetree/bindings/phy/phy-zynqmp.txt https://github.com/Xilinx/linux-xlnx/blob/master/include/dt-bindings/phy/phy.h */ /* default */ /* sata */ &sata { phy-names = "sata-phy"; phys = <&lane2 1 0 1 150000000>; }; /* SD */ &sdhci0 { // disable-wp; no-1-8-v; }; &sdhci1 { // disable-wp; no-1-8-v; }; /* USB */ &dwc3_0 { status = "okay"; dr_mode = "host"; snps,usb3_lpm_capable; snps,dis_u3_susphy_quirk; snps,dis_u2_susphy_quirk; phy-names = "usb2-phy","usb3-phy"; phys = <&lane1 4 0 2 100000000>; maximum-speed = "super-speed"; }; /* ETH PHY */ &gem3 { phy-handle = <&phy0>; phy0: phy0@1 { device_type = "ethernet-phy"; reg = <1>; }; }; /* QSPI */ &qspi { #address-cells = <1>; #size-cells = <0>; status = "okay"; flash0: flash@0 { compatible = "jedec,spi-nor"; reg = <0x0>; #address-cells = <1>; #size-cells = <1>; }; }; /* I2C */ &i2c0 { i2cswitch@73 { // u compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x73>; i2c-mux-idle-disconnect; i2c@0 { // MCLK TEBF0808 SI5338A, 570FBB000290DG_unassembled #address-cells = <1>; #size-cells = <0>; reg = <0>; }; i2c@1 { // SFP TEBF0808 PCF8574DWR #address-cells = <1>; #size-cells = <0>; reg = <1>; }; i2c@2 { // PCIe /*------------------ gtr --------------------*/ //https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18841716/Zynq+Ultrascale+MPSOC+Linux+SIOU+driver / { refclk3:psgtr_dp_clock { compatible = "fixed-clock"; #clock-cells = <0x00>; clock-frequency = <27000000>; }; refclk2:psgtr_pcie_usb_clock { compatible = "fixed-clock"; #clock-cells = <0x00>; clock-frequency = <100000000>; }; refclk1:psgtr_sata_clock { compatible = "fixed-clock"; #clock-cells = <0x00>; clock-frequency = <150000000>; }; //refclk0:psgtr_unused_clock { // compatible = "fixed-clock"; // #clock-cells = <0x00>; // clock-frequency = <100000000>; //}; }; &psgtr { clocks = <&refclk1 &refclk2 &refclk3>; /* ref clk instances used per lane */ clock-names = "ref1\0ref2\0ref3"; }; /*------------------ SD --------------------*/ &sdhci0 { // disable-wp; no-1-8-v; }; &sdhci1 { // disable-wp; no-1-8-v; }; /*------------------- USB --------------------*/ &dwc3_0 { status = "okay"; dr_mode = "host"; snps,usb3_lpm_capable; snps,dis_u3_susphy_quirk; snps,dis_u2_susphy_quirk; phy-names = "usb2-phy","usb3-phy"; maximum-speed = "super-speed"; }; /*------------------ ETH PHY --------------------*/ &gem3 { /delete-property/ local-mac-address; phy-handle = <&phy0>; nvmem-cells = <ð0_addr>; nvmem-cell-names = "mac-address"; phy0: phy0@1 { device_type = "ethernet-phy"; reg = <1>; }; }; /*----------------- SATA PHY --------------------*/ &sata { ceva,p0-burst-params = <0x13084a06>; ceva,p0-cominit-params = <0x18401828>; ceva,p0-comwake-params = <0x614080e>; ceva,p0-retry-params = <0x96a43ffc>; ceva,p1-burst-params = <0x13084a06>; ceva,p1-cominit-params = <0x18401828>; ceva,p1-comwake-params = <0x614080e>; ceva,p1-retry-params = <0x96a43ffc>; }; /*-------------------- QSPI ---------------------*/ &qspi { #address-cells = <1>; #size-cells = <0>; reg = <2>status = "okay"; }; i2c@3 { // SFP1 TEBF0808flash0: flash@0 { compatible #address-cells = <1>= "jedec,spi-nor"; #size-cells reg = <0><0x0>; reg #address-cells = <3><1>; #size-cells = }<1>; i2c@4 {// SFP2 TEBF0808 #address-cellsspi-rx-bus-width = <1><4>; #size-cellsspi-tx-bus-width = <0><4>; spi-max-frequency = <90000000>; reg = <4>; }; }; /*------------------ I2C --------------------*/ &i2c0 { i2cswitch@73 }; { // u i2c@5 { // TEBF0808 EEPROM compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x73>; reg = <5> i2c-mux-idle-disconnect; i2c@0 { // MCLK eeprom:TEBF0808 eeprom@50 { SI5338A, 570FBB000290DG_unassembled compatiblereg = "atmel,24c08"<0>; }; i2c@1 { reg = <0x50>; // SFP TEBF0808 PCF8574DWR reg = }<1>; }; i2c@6i2c@2 { // TEBF0808 FMC PCIe #address-cellsreg = <1><2>; }; #size-cells = <0>;i2c@3 { // SFP1 TEBF0808 reg = <6><3>; }; i2c@7i2c@4 { // SFP2 TEBF0808 USB HUB #address-cellsreg = <1><4>; }; i2c@5 { #size-cells = <0>;// TEBF0808 EEPROM reg = <7><5>; }; eeprom: eeprom@50 };{ i2cswitch@77 { // u compatible = "nxpmicrochip,pca954824aa025"; #address-cells = <1>, "atmel,24c02"; #size-cells = <0>; reg = <0x77><0x50>; i2c-mux-idle-disconnect; i2c@0 { // TEBF0808 PMOD P1 #address-cells = <1>; #size-cells = <0><1>; reg = <0>;eth0_addr: eth-mac-addr@FA { }; i2c@1 { //reg i2c= Audio<0xFA Codec0x06>; #address-cells = <1>}; }; #size-cells = <0>; }; regi2c@6 = <1>; /*{ // TEBF0808 FMC adau1761:reg adau1761@38= {<6>; }; compatiblei2c@7 = "adi,adau1761"; { // TEBF0808 USB HUB reg = <0x38><7>; }; }; */ i2cswitch@77 { // u compatible = }"nxp,pca9548"; i2c@2reg { // TEBF0808 Firefly A= <0x77>; #address-cells = <1>i2c-mux-idle-disconnect; i2c@0 { // TEBF0808 #size-cells = <0>;PMOD P1 reg = <2><0>; }; i2c@3i2c@1 { // TEBF0808i2c FireflyAudio BCodec #address-cellsreg = <1>; #size-cells = <0>;/* regadau1761: =adau1761@38 <3>;{ }; i2c@4compatible { //Module PLL Si5338 or SI5345 = "adi,adau1761"; #address-cellsreg = <1><0x38>; #size-cells = <0>}; reg = <4>;*/ }; i2c@5i2c@2 { // TEBF0808 Firefly CPLDA #address-cellsreg = <1><2>; }; #size-cells = <0>; i2c@3 { // TEBF0808 Firefly B reg = <5><3>; }; i2c@6i2c@4 { //TEBF0808 Firefly PCF8574DWRModule PLL Si5338 or SI5345 #address-cellsreg = <1><4>; }; i2c@5 #size-cells = <0>;{ //TEBF0808 CPLD reg = <6><5>; }; i2c@7i2c@6 { // TEBF0808 PMODFirefly P3PCF8574DWR #address-cellsreg = <1><6>; }; i2c@7 #size-cells = <0>;{ // TEBF0808 PMOD P3 reg = <7>; }; }; }; |
FSBL patch
Must be add manually, see template
};
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Kernel
Start with petalinux-config -c kernel
Changes:
- Only needed to fix JTAG Debug issue:
#- CONFIG_CPU_
- FREQ is not set
- Support PCIe memory card
- CONFIG_
- NVME_CORE=y
- CONFIG_
- BLK_
- DEV_
- NVME=y
- # CONFIG_
- NVME_
- MULTIPATH is not set
- # CONFIG_NVME_VERBOSE_ERRORS is not set
- CONFIG_NVME_CORE=y
- CONFIG_BLK_DEV_NVME=y
- # CONFIG_NVME_
- HWMON is not set
- # CONFIG_NVME_
- AUTH is not set
- CONFIG_NVME_TARGET=y
- # CONFIG_NVME_TARGET_
- PASSTHRU is not set
- # CONFIG_NVME_TARGET_
- LOOP is not set
- # CONFIG_NVME_TARGET_
- FC is not set
- # CONFIG_
- CONFIG_NVM_PBLK=y
- CONFIG_NVM_PBLK_DEBUG=y
- NVME_TARGET_TCP is not set
- # CONFIG_NVME_TARGET_AUTH is not set
- CONFIG_SATA_AHCI=y
- CONFIG_SATA_MOBILE_LPM_POLICY=0
Rootfs
Start with petalinux-config -c rootfs
Changes:
:
- For web server app:
- CONFIG_busybox-httpd=y
- For additional test tools only:
- CONFIG_i2c-tools=y
- CONFIG_packagegroup-petalinux-utils=y (util-linux,cpufrequtils,bridge-utils,mtd-utils,usbutils,pciutils,canutils,i2c-tools,smartmontools,e2fsprogs)
- For auto login:
- CONFIG_imagefeature-serial-autologin-root=y
FSBL patch (alternative for vitis fsbl trenz patch)
See "<project folder>\os\petalinux\project-spec\meta-user\recipes-bsp\embeddedsw"
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te_* files are identical to files in "<project folder>\sw_lib\sw_apps\zynqmp_fsbl\src" except for the PLL files (SI5345) which depend on PLL revision. The PLL files may have to be copied again manually into the appropriate petalinux folder "<project folder>\os\petalinux\project-spec\meta-user\recipes-bsp\embeddedsw\fsbl-firmware\git\lib\sw_apps\zynqmp_fsbl\src" |
Applications
See "<project folder>\os\petalinux\project-spec\meta-user\recipes-apps\"
startup
Script App to load init.sh from SD Card if available.
webfwu
Webserver application suitable for Zynq ZynqMP access. Need busybox-httpd
Additional Software
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SI5345
File location "<project folder>/misc/PLL/Si5345_*/Si5345-*.slabtimeproj"
General documentation how you work with these project will be available on Si5345
Appx. A: Change History and Legal Notices
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Document Change History
To get content of older revision go to "Change History" of this page and select older document revision number.
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2021-05-12 | v.44 | John Hartfiel |
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2021-02-05 | v.43 | John Hartfiel |
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2020-11-06 | v.41 | John Hartfiel |
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2020-09-29 | v.40 | John Hartfiel |
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2020-03-25 | v.37 | John Hartfiel |
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2020-02-25 | v.35 | John Hartfiel |
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2020-01-23 | v.34 | John Hartfiel |
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2019-08-09 | v.32 | John Hartfiel |
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2019-05-07 | v.29 | John Hartfiel |
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2018-08-09 | v.27 | John Hartfiel |
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2018-05-25 | v.21 | John Hartfiel |
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2018-04-30 | v.19 | John Hartfiel |
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2018-03-29 | v.18 | John Hartfiel |
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2018-02-08 | v.16 | John Hartfiel |
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2018-01-29 | v.10 | John Hartfiel |
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2018-01-18 | v.8 | John Hartfiel |
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2018-01-17 | v.7 | John Hartfiel |
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2018-01-15 | v.4 | John Hartfiel |
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2017-12-20 | v.2 | John Hartfiel |
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Legal Notices
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