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  • This line was added.
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  • Formatting was changed.


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Design Name is always "TE Series Name" + Design name, for example "TE0720 Test Board"


DateVersionChangesAuthor
20212022-0501-04253.1.610
  • removed zynq_ from zynq_fsbl
ma2021-04
  • u-boot.dtb from QSPI-Boot mode and SD-Boot mode. Is implemented in BOOT.bin
  • corrected Boot Source File in Boot Script-File
ma
2022-01-143.1.9
  • extended notes for microblaze boot process with linux
  • add u.boot.dtb to petalinux notes
  • add dtb to prebuilt content
  • replace 20.2 with 21.2
jh
2021-06-283.1.58
  • added macro "Scroll ignore" for suppression of horizontal dividing lines during .pdf-exportboot process for Microblaze
  • minor typos, formatting
ma
2021-0406-27013.1.4Version Historychanged 7
  • carrier reference note
jh
2021-05-043.1.6
  • removed zynq_ from zynq_fsbl
ma
2021-04-283.1.5
  • added macro "Scroll ignore" for suppression of horizontal dividing lines during .pdf-export
  • minor typos, formatting
ma
2021-04-273.1.4
  • Version History
    • changed from list to table
  • Design flow
    • removed step 5 from Design flow
    • changed link from TE Board Part Files to Vivado Board Part Flow
    • changed cmd shell from picture to codeblock
    • added hidden template for "Copy PetaLinux build image files", depending from hardware
    • added hidden template for "Power on PCB", depending from hardware
  • Usage update of boot process
  • Requirements - Hardware
    • added "*used as reference" for hardware requirements
  • all
    • placed a horizontal separation line under each chapter heading
    • changed title-alignment for tables from left to center
  • all tables
    • added "<project folder>\board_files" in Vivado design sources
ma

3.1.3
  • Design Flow
    • formatting
  • Launch
    • formatting
ma

3.1.2
  • minor typing corrections
  • replaced SDK by Vitis
  • changed from / to \ for windows paths
  • replaced <design name> by <project folder>
  • added "" for path names
  • added boot.src scr description
  • added USB for programming
ma

3.1.1
  • swapped order from prebuilt files
  • minor typing corrections
  • removed Win OS path length from Design flow, added as caution in Design flow
ma

3.1
  • Fix problem with pdf export and side scroll bar
  • update 19.2 to 20.2
  • add prebuilt content option


3.0
  • add fix table of content
  • add table size as macro
  • removed page initial creator


Custom_table_size_100

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Important General Note:

  • Export PDF to download, if vivado revision is changed!

  • Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro

    • Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)
      • Figure template (note: inner scroll ignore/only only with drawIO object):

        Scroll Title
        anchorFigure_xyz
        titleText


        Scroll Ignore

        Create DrawIO object here: Attention if you copy from other page, use


        Scroll Only

        image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed



      • Table template:

        • Layout macro can be use for landscape of large tables
        • Set column width manually (can be used for small tables to fit over whole page) or leave empty (automatically)

      • Scroll Title
        anchorTable_xyz
        titleText

        Scroll Table Layout
        orientationportrait
        sortDirectionASC
        repeatTableHeadersdefault
        style
        widths
        sortByColumn1
        sortEnabledfalse
        cellHighlightingtrue

        ExampleComment
        12



  • ...

Overview

Scroll Ignore
scroll-pdftrue
scroll-officetrue
scroll-chmtrue
scroll-docbooktrue
scroll-eclipsehelptrue
scroll-epubtrue
scroll-htmltrue


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Notes :

Linux with basic periphery of TE0808 StarterKit (TEBF0808 Carrier).

Refer to http://trenz.org/te0808-info for the current online version of this manual and other available documentation.

Key Features

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Notes :

  • Add basic key futures, which can be tested with the design


Excerpt
  • Vitis/Vivado 20202021.2
  • TEBF0808
  • Linux
  • USB
  • ETH
  • MAC from EEPROM
  • PCIe
  • SATA
  • SD
  • I2C
  • RGPIO
  • Display Port (DP)
  • user LED access
  • Modified FSBL for Si5338 Si5345 programming / petalinux patchSpecial FSBL for QSPI Programming

Revision History

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Notes :

  • add every update file on the download
  • add design changes on description


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DateVivadoProject BuiltAuthorsDescription
2021
2022-
05
03-
12
16
2020
2021.2TE0808-StarterKit-vivado_
2020
2021.2-build_
5
11_
20210512133800
20220316082848.zip
TE0808-StarterKit_noprebuilt-vivado_
2020
2021.2-build_
5
11_
20210512133822
20220316082848.zip
John Hartfiel
Manuela Strücker
  • 2021.2 release
  • update board files
boot.scr update
2021-05-122020.2TE0808-StarterKit-vivado_2020.2-build_5_20210512133800.zip
TE0808-StarterKit_noprebuilt-vivado_2020.2-build_5_20210512133822.zip
John Hartfiel
  • update board files
  • boot.scr update to version1 → image.ub on sd, eMMC, USB possible
2021-02-052020.2TE0808-StarterKit-vivado_2020.2-build_1_20210205120058.zip
TE0808-StarterKit_noprebuilt-vivado_2020.2-build_1_20210205120122.zip
John Hartfiel
  • bugfix init.sh script usage
2021-02-052020.2TE0808-StarterKit_noprebuilt-vivado_2020.2-build_1_20210204142828.zip
TE0808-StarterKit-vivado_2020.2-build_1_20210204142713.zip
John Hartfiel
  • 2020.2 update
  • add boot.scr file
  • device tree has change
  • petalinux fsbl patch (betaversion)
2020-09-292019.2TE0808-StarterKit_noprebuilt-vivado_2019.2-build_15_20200928195324.zip
TE0808-StarterKit-vivado_2019.2-build_15_20200928195304.zip
John Hartfiel
  • bugfix 8GB board part files
2020-09-222019.2TE0808-StarterKit_noprebuilt-vivado_2019.2-build_14_20200922071643.zip
TE0808-StarterKit-vivado_2019.2-build_14_20200922071704.zip
John Hartfiel
  • new assembly variants
2020-03-252019.2TE0808-StarterKit_noprebuilt-vivado_2019.2-build_8_20200325083508.zip
TE0808-StarterKit-vivado_2019.2-build_8_20200325083436.zip
John Hartfiel
  • script update
2020-01-222019.2TE0808-StarterKit_noprebuilt-vivado_2019.2-build_3_20200122142340.zip
TE0808-StarterKit-vivado_2019.2-build_3_20200122142318.zip
John Hartfiel
  • 2019.2 update
  • Vitis support
  • FSBL SI programming procedure update 
  • petalinux device tree and u-boot update
2019-08-092018.3TE0808-StarterKit_noprebuilt-vivado_2018.3-build_07_20190809131638.zip
TE0808-StarterKit-vivado_2018.3-build_07_20190809131620.zip
John Hartfiel
  • new assembly variants
  • small fsbl update(supports all GTR disabled now)
2019-05-072018.3TE0808-StarterKit_noprebuilt-vivado_2018.3-build_05_20190507124429.zip
TE0808-StarterKit-vivado_2018.3-build_05_20190507124418.zip
John Hartfiel
  • new assembly variant
  • TE Script update
  • rework of the FSBLs
  • some additional Linux features
  • MAC from EEPROM
  • new assembly variants
  • remove special compiler flags, which was needed in 2018.2
2018-07-112018.2TE0808-StarterKit_noprebuilt-vivado_2018.2-build_02_20180711091558.zip
TE0808-StarterKit-vivado_2018.2-build_02_20180711091049.zip
John Hartfiel
  • small petalinux changes
  • IO renaming
  • PL Design changes
  • additional notes for FSBL generated with Win SDK
  • changed *.bif
2018-05-242017.4TE0808-StarterKit_noprebuilt-vivado_2017.4-build_10_20180524091231.zip
TE0808-StarterKit-vivado_2017.4-build_10_20180524091208.zip
John Hartfiel
  • solved Linux flash issue
2018-03-292017.4TE0808-StarterKit_noprebuilt-vivado_2017.4-build_07_20180329145308.zip
TE0808-StarterKit-vivado_2017.4-build_07_20180329145246.zip
John Hartfiel
  • new assembly variant
2018-02-062017.4TE0808-StarterKit_noprebuilt-vivado_2017.4-build_05_20180206082740.zip
TE0808-StarterKit-vivado_2017.4-build_05_20180206082722.zip
John Hartfiel
  • same clk for both VIO
2018-02-052017.4TE0808-StarterKit_noprebuilt-vivado_2017.4-build_05_20180205083231.zip
TE0808-StarterKit-vivado_2017.4-build_05_20180205083208.zip
John Hartfiel
  • solved  JTAG/Linux problem
2018-01-172017.4TE0808-StarterKit-vivado_2017.4-build_05_20180117094213.zip
TE0808-StarterKit_noprebuilt-vivado_2017.4-build_05_20180117094231.zip
John Hartfiel
  • solved USB problem
  • small board part update
2018-01-152017.4

TE0808-StarterKit-vivado_2017.4-build_03_20180115092306.zip
TE0808-StarterKit_noprebuilt-vivado_2017.4-build_03_20180115092511.zip

John Hartfiel
  • rework board part files
  • rework design
2017-12-182017.2TE0808-StarterKit_noprebuilt-vivado_2017.2-build_07_20171219151749.zip
TE0808-StarterKit-vivado_2017.2-build_07_20171219151728.zip
John Hartfiel
  • initial release


Release Notes and Know Issues

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Notes :
  • add known Design issues and general notes for the current revision
  • do not delete known issue, add fixed version time stamp if issue fixed

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title

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IssuesDescriptionWorkaround/SolutionTo be fixed version
Flash access on LinuxDevice tree is not correct on Linuxadd compatibility to "compatible “jedec,spi-nor”"Solved with 20180524 update
USB UART Terminal is blocked/ SDK Debugging is blockedThis happens only with 2017.4 Linux, when JTAG connection is established on Vivado HW Manager.

Do not use HW Manager connection, or if debugging is necessary:

  1. Boot linux with usb terminal
  2. From the terminal: root root mount ifconfig eth0
  3. Open two new SSH terminals via ethernet: root root , run user application ...
  4. Exit and close the usb terminal
Solved with 20180205 update

Requirements

Software

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Notes :

  • list of software which was used to generate the design
MAC from EEPROM

The MAC address stored in the EEPROM is not read out and initialised correctly during start-up.
This is caused by two I2C expanders each switched to the same EEPROM with the same address
i2cswitch@73 --> i2c@5 --> reg = <0x50> and
i2cswitch@77 --> i2c@4 --> reg = <0x50>

Switching the second I2C expander (i2cswitch@77) to another channel in the fsbl solves the error during the start-up procedure.

Solved
with 20220316 update

QSPI FlashFlash programming is not supported with boot mode QSPI or SD.
If flash programming fails, configure device for JTAG boot mode and try again or use oder Vivado Versions for programming. (Vivado 2020.2 or 2019.2)
--
Flash access on LinuxDevice tree is not correct on Linuxadd compatibility to "compatible “jedec,spi-nor”"Solved with 20180524 update
USB UART Terminal is blocked/ SDK Debugging is blockedThis happens only with 2017.4 Linux, when JTAG connection is established on Vivado HW Manager.

Do not use HW Manager connection, or if debugging is necessary:

  1. Boot linux with usb terminal
  2. From the terminal: root root mount ifconfig eth0
  3. Open two new SSH terminals via ethernet: root root , run user application ...
  4. Exit and close the usb terminal
Solved with 20180205 update


Requirements

Software

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Notes :

  • list of software which was used to generate the design


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SoftwareVersionNote
Vitis
2020
2021.2needed, Vivado is included into Vitis installation
PetaLinux
2020
2021.2needed
SI ClockBuilder Pro---optional


Hardware

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Notes :

  • list of hardware which was used to generate the design
  • mark the module and carrier board, which was used tested with an *

Basic description of TE Board Part Files is available on TE Board Part Files.

Complete List is available on "<project folder>\board_files\*_board_files.csv"

Design supports following modules:


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Module ModelBoard Part Short NamePCB Revision SupportDDRQSPI FlashEMMCOthersNotes
TE0808-ES1          es1_2gb      REV03|REV02 2GB      64MB       NA         NA               Not longer supported by vivado       
TE0808-ES2          es2_2gb      REV04|REV03 2GB      64MB       NA         NA               Not longer supported by vivado                   
TE0808-2ES2         2es2_2gb     REV04|REV03 2GB      64MB       NA         NA               Not longer supported by vivado                
TE0808-04-09EG-1EA  9eg_1e_2gb   REV04       2GB      64MB       NA         NA               NA                                     
TE0808-04-09EG-1EB  9eg_1e_4gb   REV04       4GB      64MB       NA         NA               NA                                     
TE0808-04-09EG-1ED  9eg_1e_4gb   REV04       4GB      64MB       NA         1 mm connectorsNA                                     
TE0808-04-09EG-2IB  9eg_2i_4gb   REV04       4GB      64MB       NA         NA               NA                                     
TE0808-04-15EG-1EB  15eg_1e_4gb  REV04       4GB      64MB       NA         NA               NA                                     
TE0808-04-09EG-1EE  9eg_1e_4gb   REV04       4GB      128MB      NA         NA               NA                                     
TE0808-04-09EG-1EL  9eg_1e_4gb   REV04       4GB      128MB      NA         1 mm connectorsNA                                     
TE0808-04-09EG-
2IE  
2IE*  9eg_2i_4gb   REV04       4GB      128MB      NA         NA               NA                                     
TE0808-04-15EG-1EE  15eg_1e_4gb  REV04       4GB      128MB      NA         NA               NA                                     
TE0808-04-06EG-1EE  6eg_1e_4gb   REV04       4GB      128MB      NA         NA               NA                                     
TE0808-04-06EG-1E3  6eg_1e_4gb   REV04       4GB      128MB      NA         1 mm connectorsNA                                     
TE0808-04-6GI21-L   6eg_2i_4gb   REV04       4GB      128MB      NA         1 mm connectorsNA                                     
TE0808-04-6BI21-A   6eg_1i_4gb   REV04       4GB      128MB      NA         NA               NA                                     
TE0808-04-9GI21-A   9eg_2i_4gb   REV04       4GB      128MB      NA         NA               NA                                     
TE0808-04-9BE21-A   9eg_1e_4gb   REV04       4GB      128MB      NA         NA               NA                                     
TE0808-04-6BE21-L   6eg_1e_4gb   REV04       4GB      128MB      NA         1 mm connectorsNA                                     
TE0808-04-6BE21-A   6eg_1e_4gb   REV04       4GB      128MB      NA         NA               NA                                     
TE0808-04-9BE21-L   9eg_1e_4gb   REV04       4GB      128MB      NA         1 mm connectorsNA                                     
TE0808-04-BBE21-A   15eg_1e_4gb  REV04       4GB      128MB      NA         NA               NA                                     
TE0808-04-6BI21-X   6eg_1i_4gb   REV04       4GB      128MB      NA         NA               U41 replaced with schottky diodes    
TE0808-05-6BE21-L   6eg_1e_4gb   REV05       4GB      128MB      NA         1 mm connectorsNA                                     
TE0808-05-6BE21-A   6eg_1e_4gb   REV05       4GB      128MB      NA         NA               NA                                     
TE0808-05-6BI21-D   6eg_1i_4gb   REV05       4GB      128MB      NA         1 mm connectorsSoC without encryption               
TE0808-05-6BI21-X   6eg_1i_4gb   REV05       4GB      128MB      NA         NA               U41 replaced with schottky diodes    
TE0808-05-6BI41-X   6eg_1i_8gb   REV05       8GB      128MB      NA         NA               U41 replaced with schottky diodes    
TE0808-05-9BE21-A   9eg_1e_4gb   REV05       4GB      128MB      NA         NA               NA                                     
TE0808-05-9BE21-L   9eg_1e_4gb   REV05       4GB      128MB      NA         1 mm connectorsNA                                     
TE0808-05-9BI41-X   9eg_1i_8gb   REV05       8GB      128MB      NA         NA               U41 replaced with schottky diodes    
TE0808-05-9GI21-A   9eg_2i_4gb   REV05       4GB      128MB      NA         NA               NA                                     
TE0808-05-9GI21-C   9eg_2i_4gb   REV05       4GB      128MB      NA         NA               SoC without encryption               
TE0808-05-BBE21-A   15eg_1e_4gb  REV05       4GB      128MB      NA         NA               NA                                     
TE0808-05-BBE21-L   15eg_1e_4gb  REV05       4GB      128MB      NA         1 mm connectorsNA    

Note: Design contains also Board Part Files for TE0808 only configuration, this board part files are not used for this reference design.

Design supports following carriers:

Scroll Title
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Scroll Table LayoutorientationportraitsortDirectionASCrepeatTableHeadersdefaultstylewidthssortByColumn1tableStylingconfluencesortEnabledfalsecellHighlightingtrueCarrier ModelNotesTEBF0808Used as reference carrier. Important: CPLD Firmware REV07 or newer is recommended

Additional HW Requirements:

Scroll Title
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Scroll Table LayoutorientationportraitsortDirectionASCrepeatTableHeadersdefaultstylewidthssortByColumn1sortEnabledfalsecellHighlightingtrueAdditional HardwareNotesDisplay Port Monitor

Optional HW
Not all monitors are supported, also Adapter to other Standard can make trouble.
Design was tested with DELL U2412M

USB KeyboardOptional HW
Can be used to get access to console which is show on Display PortUSB StickOptional HW
USB was tested with USB memory stickSATA DiskOptional HWPCIe CardOptional HWETH cableOptional HW
Ethernet works with DHCP, but can be setup also manuallySD cardwith fat32 partition

Content

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Notes :

  • content of the zip file

For general structure and of the reference design, see Project Delivery - Xilinx devices

Design Sources

TE0808-05-S002

15eg_1e_4gb

REV054GB128MBNANACAO
TE0808-05-S003 15eg_1e_4gbREV054GB128MBNANACAO
TE0808-05-S005 9eg_2i_4gb REV054GB128MBNANACAO
TE0808-05-S004 9eg_2i_4gb REV054GB128MBNANACAO
TE0808-05-6BE21-AK6eg_1e_4gb REV054GB128MBNANANA
TE0808-05-9BE21-LK9eg_1e_4gb REV054GB128MBNA1 mm connectorsNA
TE0808-05-9GI21-AK9eg_2i_4gb REV054GB128MBNANANA
TE0808-05-BBE21-AK15eg_1e_4gbREV054GB128MBNANANA
TE0808-05-S0069eg_2i_4gb REV054GB128MBNANACAO

*used as reference

Note: Design contains also Board Part Files for TE0808 only configuration, this board part files are not used for this reference design.

Design supports following carriers:

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TypeLocationCarrier ModelNotes
Vivado<project folder>\block_design
<project folder>\constraints
<project folder>\ip_lib
<project folder>\board_files
Vivado Project will be generated by TE Scripts
Vitis<project folder>\sw_libAdditional Software Template for Vitis and apps_list.csv with settings automatically for Vitis app generation
PetaLinux<project folder>\os\petalinuxPetaLinux template with current configuration
Additional Sources
TEBF0808*Used as reference carrier. Important: CPLD Firmware REV07 or newer is recommended

*used as reference

Additional HW Requirements:

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TypeLocationAdditional HardwareNotes
SI5345<project folder>/misc/Si5345SI5345 Project with current PLL Configuration
init.sh<project folder>/sd/Additional Initialization Script for Linux
Prebuilt
Display Port Monitor

Optional HW
Not all monitors are supported, also Adapter to other Standard can make trouble.
Design was tested with DELL U2412M

USB KeyboardOptional HW
Can be used to get access to console which is show on Display Port
USB StickOptional HW
USB was tested with USB memory stick
SATA DiskOptional HW
PCIe CardOptional HW
ETH cableOptional HW
Ethernet works with DHCP, but can be setup also manually
SD cardwith fat32 partition

*used as reference

Content

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Notes :

  • prebuilt files
  • Template Table:content of the zip file

For general structure and of the reference design, see Project Delivery - Xilinx devices

Design Sources

PFPrebuilt fileswidths

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Design sources

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File
Type
File-Extension
Location
Description

SREC-File

*.srec

Converted Software Application for MicroBlaze Processor Systems
Notes
BIF-File*.bifFile with description to generate Bin-FileBIN-File*.binFlash Configuration File with Boot-Image (Zynq-FPGAs)BIT-File*.bitFPGA (PL Part) Configuration FileBoot Source*.scr

Distro Boot file

DebugProbes-File*.ltxDefinition File for Vivado/Vivado Labtools Debugging Interface

Debian SD-Image

*.img

Debian Image for SD-Card

Diverse Reports---Report files in different formatsHardware-Platform-Description-File*.xsaExported Vivado hardware description file for Vitis and PetaLinuxLabTools Project-File*.lprVivado Labtools Project File

MCS-File

*.mcs

Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)

MMI-File

*.mmi

File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)

OS-Image*.ubImage with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)Software-Application-File*.elfSoftware Application for Zynq or MicroBlaze Processor Systems
Vivado<project folder>\block_design
<project folder>\constraints
<project folder>\ip_lib
<project folder>\board_files
Vivado Project will be generated by TE Scripts
Vitis<project folder>\sw_libAdditional Software Template for Vitis and apps_list.csv with settings automatically for Vitis app generation
PetaLinux<project folder>\os\petalinuxPetaLinux template with current configuration



Additional Sources

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TypeLocationNotes
SI5345<project folder>/misc/PLL/Si5345_BSI5345 Project with current PLL Configuration
init.sh<project folder>/misc/sd/Additional initialization script for Linux


Prebuilt

(only on ZIP with prebult content)Software-Application
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  • prebuilt files
  • Template Table:

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    • Scroll Table Layout
      orientationportrait
      sortDirectionASC
      repeatTableHeadersdefault
      style
      widths
      sortByColumn1
      sortEnabledfalse
      cellHighlightingtrue

      File

      File-Extension

      Description

      BIF-File*.bifFile with description to generate Bin-File
      BIN-File*.binFlash Configuration File with Boot-Image (Zynq-FPGAs)
      BIT-File*.bitFPGA (PL Part) Configuration File
      Boot
Source
    • Script-File*.scr

      Distro Boot Script file

      DebugProbes-File*.ltxDefinition File for Vivado/Vivado Labtools Debugging Interface

      Debian SD-Image

      *.img

      Debian Image for SD-Card

      Diverse Reports---Report files in different formats
      Device Tree*.dtsDevice tree (2 possible, one for u-boot and one for linux)
      Hardware-Platform-Description-File*.xsaExported Vivado hardware description file for Vitis and PetaLinux
      LabTools Project-File*.lprVivado Labtools Project File
OS
    • MCS-

Image
    • File

      *.

ub
Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)

mcs

Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)

MMI-File

*.

elfSoftware Application for Zynq or MicroBlaze Processor Systems

Download

Reference Design is only usable with the specified Vivado/Vitis/PetaLinux version. Do never use different Versions of Xilinx Software for the same Project.

Page properties
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Reference Design is available on:

Design Flow

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Notes :
  • Basic Design Steps

  • Add/ Remove project specific description

Note

Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first launch.

Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.

See also:

The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.

TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/Vitis GUI. For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality

Note

Caution! Win OS has a 260 character limit for path lengths which can affect the Vivado tools. To avoid this issue, use Virtual Drive or the shortest possible names and directory locations for the reference design (for example "x:\<project folder>")

Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:

Code Block
languagebash
themeMidnight
title_create_win_setup.cmd/_create_linux_setup.sh
------------------------Set design paths----------------------------
-- Run Design with: _create_win_setup
-- Use Design Path: <absolute project path>
--------------------------------------------------------------------
-------------------------TE Reference Design---------------------------
--------------------------------------------------------------------
-- (0)  Module selection guide, project creation...prebuilt export...
-- (1)  Create minimum setup of CMD-Files and exit Batch
-- (2)  Create maximum setup of CMD-Files and exit Batch
-- (3)  (internal only) Dev
-- (4)  (internal only) Prod
-- (c)  Go to CMD-File Generation (Manual setup)
-- (d)  Go to Documentation (Web Documentation)
-- (g)  Install Board Files from Xilinx Board Store (beta)
-- (a)  Start design with unsupported Vivado Version (beta)
-- (x)  Exit Batch (nothing is done!)
----
Select (ex.:'0' for module selection guide):
  • Press 0 and enter to start "Module Selection Guide"
  • Create Project (follow instruction of the product selection guide), settings file will be configured automatically during this process
    1. (optional for manual changes) Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
      Note: Select correct one, see TE Board Part Files
                Important: Use Board Part Files, which ends with *_tebf0808
  • Create hardware description file (.xsa file) for PetaLinux project and export to prebuilt folder

    Code Block
    languagepy
    themeMidnight
    titlerun on Vivado TCL (Script generates design and export files into "<project folder>\prebuilt\hardware\<short name>")
    TE::hw_build_design -export_prebuilt
    Info

    Using Vivado GUI is the same, except file export to prebuilt folder.

  • Create and configure your PetaLinux project with exported .xsa-file, see PetaLinux KICKstart
    • use TE Template from "<project folder>\os\petalinux"
    • use exported .xsa file from "<project folder>\prebuilt\hardware\<short name>" . Note: HW Export from Vivado GUI creates another path as default workspace.

    • The build images are located in the "<plnx-proj-root>/images/linux" directory

  • Configure the boot.scr file as needed, see Distro Boot with Boot.scr

  • Copy PetaLinux build image files to prebuilt folder

    copy u-boot.elf, bl31.elf, image.ub and boot.scr from "<plnx-proj-root>/images/linux" to prebuilt folder

    Info

    "<project folder>\prebuilt\os\petalinux\<ddr size>" or "<project folder>\prebuilt\os\petalinux\<short name>"

    Page properties
    hiddentrue
    idComments

    This step depends on Xilinx Device/Hardware

    for Zynq-7000 series

    • copy u-boot.elf, image.ub and boot.scr from "<plnx-proj-root>/images/linux" to prebuilt folder

    for ZynqMP

    • copy u-boot.elf, bl31.elf, image.ub and boot.scr from "<plnx-proj-root>/images/linux" to prebuilt folder

    for ...

    • ...

    Generate Programming Files with Vitis

    Code Block
    languagepy
    themeMidnight
    titlerun on Vivado TCL (Script generates applications and bootable files, which are defined in "test_board\sw_lib\apps_list.csv")
    TE::sw_run_vitis -all
    TE::sw_run_vitis (optional; Start Vitis from Vivado GUI or start with TE Scripts on Vivado TCL)
    Note

    TCL scripts generate also platform project, this must be done manually in case GUI is used. See Vitis

    Launch

    Scroll Ignore
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    Page properties
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    idComments

    Note:

    • Programming and Startup procedure

    For basic board setup, LEDs... see: TEBF0808 Getting Started

    Programming

    Note

    Check Module and Carrier TRMs for proper HW configuration before you try any design.

    Xilinx documentation for programming and debugging: Vivado/Vitis/SDSoC-Xilinx Software Programming and Debugging

    Get prebuilt boot binaries

  • Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell
  • Press 0 and enter to start "Module Selection Guide"
  • Select assembly version
  • Validate selection
  • Select create and open delivery binary folder

    Info

    Note: Folder "<project folder>\_binaries_<Article Name>" with subfolder "boot_<app name>" for different applications will be generated

    QSPI-Boot mode

    Option for Boot.bin on QSPI Flash and image.ub and boot.scr on SD or USB.

  • Connect JTAG and power on carrier with module
  • Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"
      • mmi

        File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)

        OS-Image*.ubImage with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)
        Software-Application-File*.elfSoftware Application for Zynq or MicroBlaze Processor Systems

        SREC-File

        *.srec

        Converted Software Application for MicroBlaze Processor Systems





    Scroll Title
    anchorTable_PF
    title-alignmentcenter
    titlePrebuilt files (only on ZIP with prebult content)

    Scroll Table Layout
    orientationportrait
    sortDirectionASC
    repeatTableHeadersdefault
    style
    widths
    sortByColumn1
    sortEnabledfalse
    cellHighlightingtrue

    File

    File-Extension

    Description

    BIF-File*.bifFile with description to generate Bin-File
    BIN-File*.binFlash Configuration File with Boot-Image (Zynq-FPGAs)
    BIT-File*.bitFPGA (PL Part) Configuration File
    Boot Script-File*.scr

    Distro Boot Script file

    DebugProbes-File*.ltxDefinition File for Vivado/Vivado Labtools Debugging Interface
    Diverse Reports---Report files in different formats
    Device Tree*.dtsDevice tree (2 possible, one for u-boot and one for linux)
    Hardware-Platform-Description-File*.xsaExported Vivado hardware description file for Vitis and PetaLinux
    LabTools Project-File*.lprVivado Labtools Project File
    OS-Image*.ubImage with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)
    Software-Application-File*.elfSoftware Application for Zynq or MicroBlaze Processor Systems


    Download

    Reference Design is only usable with the specified Vivado/Vitis/PetaLinux version. Do never use different Versions of Xilinx Software for the same Project.

    Page properties
    hiddentrue
    idComments
    Reference Design is available on:

    Design Flow

    Scroll Ignore
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    scroll-docbooktrue
    scroll-eclipsehelptrue
    scroll-epubtrue
    scroll-htmltrue


    Page properties
    hiddentrue
    idComments
    Notes :
    • Basic Design Steps

    • Add/ Remove project specific description


    Note

    Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first launch.

    Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.

    See also:

    The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.

    TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/Vitis GUI. For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality

    Note

    Caution! Win OS has a 260 character limit for path lengths which can affect the Vivado tools. To avoid this issue, use Virtual Drive or the shortest possible names and directory locations for the reference design (for example "x:\<project folder>")

    1. Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:

      Code Block
      languagebash
      themeMidnight
      title_create_win_setup.cmd/_create_linux_setup.sh
      ------------------------Set design paths----------------------------
      -- Run Design with: _create_win_setup
      -- Use Design Path: <absolute project path>
      --------------------------------------------------------------------
      -------------------------TE Reference Design---------------------------
      --------------------------------------------------------------------
      -- (0)  Module selection guide, project creation...prebuilt export...
      -- (1)  Create minimum setup of CMD-Files and exit Batch
      -- (2)  Create maximum setup of CMD-Files and exit Batch
      -- (3)  (internal only) Dev
      -- (4)  (internal only) Prod
      -- (c)  Go to CMD-File Generation (Manual setup)
      -- (d)  Go to Documentation (Web Documentation)
      -- (g)  Install Board Files from Xilinx Board Store (beta)
      -- (a)  Start design with unsupported Vivado Version (beta)
      -- (x)  Exit Batch (nothing is done!)
      ----
      Select (ex.:'0' for module selection guide):


    2. Press 0 and enter to start "Module Selection Guide"
    3. Create project and follow instructions of the product selection guide, settings file will be configured automatically during this process.
      • optional for manual changes: Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"

        Note

        Note: Select correct one, see also Vivado Board Part Flow

        Important: Use Board Part Files, which ends with *_tebf0808


    4. Create hardware description file (.xsa file) for PetaLinux project and export to prebuilt folder

      Code Block
      languagepy
      themeMidnight
      titlerun on Vivado TCL (Script programs BOOT.bin on QSPI flash)
      TE::pr_program_flash -swapp u-boot
      TE::pr_program_flash -swapp hello_te0808 (optional)
      Note

      To program with Vitis/Vivado GUI, use special FSBL (zynqmp_fsbl_flash) on setup

    5. Copy image.ub and boot.scr on SD or USB
      • use files from "<project folder>\_binaries_<Article Name>\boot_linux" from generated binary folder,see: Get prebuilt boot binaries
      • or use prebuilt file location, see "<project folder>\prebuilt\file_location.txt"
    6. Set Boot Mode to QSPI-Boot and insert SD or USB.
      • Depends on Carrier, see carrier TRM.
      • TEBF0808 change automatically the Boot Mode to SD, if SD is inserted, optional CPLD Firmware without Boot Mode changing for microSD Slot is available on the download area

    SD-Boot mode

    1. Copy image.ub, boot.src and Boot.bin on SD
      • use files from "<project folder>\_binaries_<Article Name>\boot_linux" from generated binary folder, see: Get prebuilt boot binaries
      • or use prebuilt file location, see "<project folder>\prebuilt\file_location.txt"
    2. Set Boot Mode to SD-Boot.
      • Depends on Carrier, see carrier TRM.
    3. Insert SD-Card in SD-Slot.

    JTAG

    Not used on this Example.

    Usage

  • Prepare HW like described on section Programming
  • Connect UART USB (most cases same as JTAG)
  • Select SD Card as Boot Mode (or QSPI - depending on step 1)

    Info

    Note: See TRM of the Carrier, which is used.

    Tip

    Starting with Petalinux version 2020.1, the industry standard "Distro-Boot" boot flow for U-Boot was introduced, which significantly expands the possibilities of the boot process and has the primary goal of making booting much more standardised and predictable.
    The boot options described above describe the common boot processes for this hardware; other boot options are possible.
    For more information see Distro Boot with Boot.scr

  • (Optional) Insert PCIe Card (detection depends on Linux driver. Only some basic drivers are installed)
  • (Optional) Connect SATA Disc
  • (Optional) Connect Display Port Monitor (List of usable Monitors: https://www.xilinx.com/support/answers/68671.html)
  • (Optional) Connect Network Cable
  • Power On PCB

    Expand
    titleboot process

    1. ZynqMP Boot ROM loads FSBL from SD/QSPI into OCM,

    2. FSBL init the PS, programs the PL using the bitstream and loads PMU, ATF and U-boot from SD/QSPI into DDR,

    3. U-boot loads Linux (image.ub) from SD/QSPI/... into DDR

    Linux

    Open Serial Console (e.g. putty)
  • Speed: 115200
  • select COM Port

    Info

    Win OS, see device manager, Linux OS see dmesg |grep tty (UART is *USB1)

    Linux Console:

    Code Block
    languagebash
    themeMidnight
    petalinux login: root
    Password: root
    Info

    Note: Wait until Linux boot finished

    You can use Linux shell now.

    Code Block
    languagebash
    themeMidnight
    i2cdetect -y -r 0	(check I2C 1 Bus)
    udhcpc				(ETH0 check)
    lsusb				(USB check)
    lspci               (PCIe check)
  • Option Features

    • Webserver to get access to Zynq
      • insert IP on web browser to start web interface
    • init.sh scripts
      • add init.sh script on SD, content will be load automatically on startup (template included in "<project folder>\misc\SD")
  • Vivado Hardware Manager

    Page properties
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    Note:

    • Add picture of HW Manager

    • add notes for the signal either groups or topics, for example:

      Control:

      • add controllable IOs with short notes..

      Monitoring:

      • add short notes for signals which will be monitored only
      • SI5338 CLKs:
        • Set radix from VIO signals to unsigned integer. Note: Frequency Counter is inaccurate and displayed unit is Hz
        • expected CLK Frequency...
    Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder).
    Control:LEDs: XMOD 2 (without green dot) and HD LED are accessible.
  • CAN_S
  • Scroll Title
    anchorFigure_VHM
    title-alignmentcenter
    titleVivado Hardware Manager

    Image Removed

    Image Removed

    System Design - Vivado

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    Note:

    • Description of Block Design, Constrains... BD Pictures from Export...

    Block Design

    Scroll Title
    anchorFigure_BD
    title-alignmentcenter
    titleBlock Design
    Image Removed

    PS Interfaces

    Page properties
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    Note:

    • optional for Zynq / ZynqMP only

    • add basic PS configuration
    Activated interfaces: Scroll Title
    anchorTable_PSI
    title-alignmentcenter
    titlePS Interfaces
    Scroll Table LayoutorientationportraitsortDirectionASCrepeatTableHeadersdefaultstylewidthssortByColumn1sortEnabledfalsecellHighlightingtrueTypeNoteDDRQSPIMIOSD0MIOSD1MIOCAN0EMIOI2C0MIOPJTAG0MIOUART0MIOGPIO0MIOSWDT0..1TTC0..3GEM3MIOUSB0MIO/GTPPCIeMIO/GTPSATAGTPDisplay PortEMIO/GTP

    Constrains

    Basic module constrains

    Code Block
    languageruby
    title_i_bitgen.xdc
    set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
    set_property BITSTREAM.CONFIG.UNUSEDPIN PULLNONE [current_design]

    Design specific constrain

    Code Block
    languageruby
    title_i_io.xdc
    #System Controller IP #LED_HD SC0 J3:31 #LED_XMOD SC17 J3:48 #CAN RX SC19 J3:52 B47_L2_P in #CAN TX SC18 J3:50 B47_L2_N out #CAN S SC16 J3:46 B47_L3_N out set_property PACKAGE_PIN J14 [get_ports BASE_sc0] set_property PACKAGE_PIN G13 [get_ports BASE_sc5] set_property PACKAGE_PIN J15 [get_ports BASE_sc6] set_property PACKAGE_PIN K15 [get_ports BASE_sc7] set_property PACKAGE_PIN A15 [get_ports BASE_sc10_io] set_property PACKAGE_PIN B15 [get_ports BASE_sc11] set_property PACKAGE_PIN C13 [get_ports BASE_sc12] set_property PACKAGE_PIN C14 [get_ports BASE_sc13] set_property PACKAGE_PIN E13 [get_ports BASE_sc14] set_property PACKAGE_PIN E14 [get_ports BASE_sc15] set_property PACKAGE_PIN A13 [get_ports BASE_sc16] set_property PACKAGE_PIN B13 [get_ports BASE_sc17] set_property PACKAGE_PIN A14 [get_ports BASE_sc18] set_property PACKAGE_PIN B14 [get_ports BASE_sc19] set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc0] set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc5] set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc6] set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc7] set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc10_io] set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc11] set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc12] set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc13] set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc14
    1. generates design and export files into "<project folder>\prebuilt\hardware\<short name>")
      TE::hw_build_design -export_prebuilt


      Info

      Using Vivado GUI is the same, except file export to prebuilt folder.


    2. Create and configure your PetaLinux project with exported .xsa-file, see PetaLinux KICKstart
      • use TE Template from "<project folder>\os\petalinux"
      • use exported .xsa file from "<project folder>\prebuilt\hardware\<short name>" . Note: HW Export from Vivado GUI creates another path as default workspace.

      • The build images are located in the "<plnx-proj-root>/images/linux" directory

    3. Configure the boot.scr file as needed, see Distro Boot with Boot.scr

    4. Copy PetaLinux build image files to prebuilt folder
        • copy u-boot.elf, u-boot.dtb, system.dtb, bl31.elf, image.ub and boot.scr from "<plnx-proj-root>/images/linux" to prebuilt folder
        Info

        "<project folder>\prebuilt\os\petalinux\<ddr size>" or "<project folder>\prebuilt\os\petalinux\<short name>"


        Page properties
        hiddentrue
        idComments

        This step depends on Xilinx Device/Hardware

        for Zynq-7000 series

        • copy u-boot.elf, u-boot.dtb, system.dtb, image.ub and boot.scr from "<plnx-proj-root>/images/linux" to prebuilt folder

        for ZynqMP

        • copy u-boot.elf, u-boot.dtb, system.dtb, bl31.elf, image.ub and boot.scr from "<plnx-proj-root>/images/linux" to prebuilt folder

        for ...

        • ...


    5. Generate Programming Files with Vitis

      Code Block
      languagepy
      themeMidnight
      titlerun on Vivado TCL (Script generates applications and bootable files, which are defined in "test_board\sw_lib\apps_list.csv")
      TE::sw_run_vitis -all
      TE::sw_run_vitis (optional; Start Vitis from Vivado GUI or start with TE Scripts on Vivado TCL)


      Note

      TCL scripts generate also platform project, this must be done manually in case GUI is used. See Vitis


    Launch

    Scroll Ignore
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    scroll-epubtrue
    scroll-htmltrue


    Page properties
    hiddentrue
    idComments

    Note:

    • Programming and Startup procedure

    For basic board setup, LEDs... see: TEBF0808 Getting Started

    Programming

    Note

    Check Module and Carrier TRMs for proper HW configuration before you try any design.

    Xilinx documentation for programming and debugging: Vivado/Vitis/SDSoC-Xilinx Software Programming and Debugging

    Get prebuilt boot binaries

    1. Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell
    2. Press 0 and enter to start "Module Selection Guide"
      1. Select assembly version
      2. Validate selection
      3. Select create and open delivery binary folder

        Info

        Note: Folder "<project folder>\_binaries_<Article Name>" with subfolder "boot_<app name>" for different applications will be generated


    QSPI-Boot mode

    Option for Boot.bin on QSPI Flash.

    1. Connect JTAG and power on carrier with module
    2. Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"

      Code Block
      languagepy
      themeMidnight
      titlerun on Vivado TCL (Script programs BOOT.bin on QSPI flash)
      TE::pr_program_flash -swapp hello_te0808


    3. Set Boot Mode to QSPI-Boot
      • Depends on Carrier, see carrier TRM.
      • TEBF0808 change automatically the Boot Mode to SD, if SD is inserted, optional CPLD Firmware without Boot Mode changing for microSD Slot is available on the download area

    SD-Boot mode

    1. Copy image.ub, boot.scr and Boot.bin on SD
      • use files from "<project folder>\_binaries_<Article Name>\boot_linux" from generated binary folder, see: Get prebuilt boot binaries
      • or use prebuilt file location, see "<project folder>\prebuilt\file_location.txt"
    2. Set Boot Mode to SD-Boot.
      • Depends on Carrier, see carrier TRM.
    3. Insert SD-Card in SD-Slot.

    JTAG

    Not used on this Example.

    Usage

    1. Prepare HW like described on section Programming
    2. Connect UART USB (most cases same as JTAG)
    3. Select SD Card as Boot Mode (or QSPI - depending on step 1)

      Info

      Note: See TRM of the Carrier, which is used.


      Tip

      Starting with Petalinux version 2020.1, the industry standard "Distro-Boot" boot flow for U-Boot was introduced, which significantly expands the possibilities of the boot process and has the primary goal of making booting much more standardised and predictable.
      The boot options described above describe the common boot processes for this hardware; other boot options are possible.
      For more information see Distro Boot with Boot.scr


    4. (Optional with TEBF0808) Insert PCIe Card (detection depends on Linux driver. Only some basic drivers are installed)
    5. (Optional with TEBF0808) Connect SATA Disc
    6. (Optional with TEBF0808) Connect Display Port Monitor (List of usable Monitors: https://www.xilinx.com/support/answers/68671.html)
    7. (Optional with TEBF0808) Connect Network Cable
    8. Power On PCB

      Expand
      titleboot process

      1. ZynqMP Boot ROM loads FSBL from SD/QSPI into OCM,

      2. FSBL init the PS, programs the PL using the bitstream and loads PMU, ATF and U-boot from SD/QSPI into DDR,

      3. U-boot loads Linux (image.ub) from SD/QSPI/... into DDR


    Linux

    1. Open Serial Console (e.g. putty)
      • Speed: 115200
      • select COM Port

        Info

        Win OS, see device manager, Linux OS see dmesg |grep tty (UART is *USB1)


    2. Linux Console:

      Code Block
      languagebash
      themeMidnight
      # password default disabled with 2021.2 petalinux release
      petalinux login: root
      Password: root


      Info

      Note: Wait until Linux boot finished


    3. You can use Linux shell now.

      Code Block
      languagebash
      themeMidnight
      i2cdetect -y -r 0	(check I2C 0 Bus, replace 0 with other bus number is also possible)
      dmesg | grep rtc	(RTC check)
      udhcpc				(ETH0 check)
      lsusb				(USB check)
      lspci               (PCIe check)


    4. Option Features

      • Webserver to get access to ZynqMP
        • insert IP on web browser to start web interface
      • init.sh scripts
        • add init.sh script on SD, content will be load automatically on startup (template included in "<project folder>\misc\SD")

    Vivado Hardware Manager

    Page properties
    hiddentrue
    idComments

    Note:

    • Add picture of HW Manager

    • add notes for the signal either groups or topics, for example:

      Control:

      • add controllable IOs with short notes..

      Monitoring:

      • add short notes for signals which will be monitored only
      • SI5338 CLKs:
        • Set radix from VIO signals to unsigned integer. Note: Frequency Counter is inaccurate and displayed unit is Hz
        • expected CLK Frequency...
    Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder).
    • Control:
      • LEDs: XMOD 2 (without green dot) and HD LED are accessible.
      • CAN_S
    Scroll Title
    anchorFigure_VHM
    title-alignmentcenter
    titleVivado Hardware Manager


    Image Added

    Image Added


    System Design - Vivado

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    Page properties
    hiddentrue
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    Note:

    • Description of Block Design, Constrains... BD Pictures from Export...

    Block Design

    Scroll Title
    anchorFigure_BD
    title-alignmentcenter
    titleBlock Design
    Image Added


    PS Interfaces

    Page properties
    hiddentrue
    idComments

    Note:

    • optional for Zynq / ZynqMP only

    • add basic PS configuration
    Activated interfaces:


    Scroll Title
    anchorTable_PSI
    title-alignmentcenter
    titlePS Interfaces

    Scroll Table Layout
    orientationportrait
    sortDirectionASC
    repeatTableHeadersdefault
    style
    widths
    sortByColumn1
    sortEnabledfalse
    cellHighlightingtrue

    TypeNote
    DDR
    QSPIMIO
    SD0MIO
    SD1MIO
    CAN0EMIO
    I2C0MIO
    PJTAG0MIO
    UART0MIO
    GPIO0MIO
    SWDT0..1
    TTC0..3
    GEM3MIO
    USB0MIO/GTP
    PCIeMIO/GTP
    SATAGTP
    Display PortEMIO/GTP


    Constrains

    Basic module constrains

    Code Block
    languageruby
    title_i_bitgen.xdc
    set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
    set_property BITSTREAM.CONFIG.UNUSEDPIN PULLNONE [current_design]

    Design specific constrain

    Code Block
    languageruby
    title_i_io.xdc
    #System Controller IP
      #LED_HD SC0 J3:31
      #LED_XMOD SC17 J3:48 
      #CAN RX SC19 J3:52 B47_L2_P in
      #CAN TX SC18 J3:50 B47_L2_N out 
      #CAN S  SC16 J3:46 B47_L3_N out
    #HDIO_SC1    K14
    #HDIO_SC2    H13
    #HDIO_SC3    H14
    #HDIO_SC4    F13
    
    
    
    #HDIO_SC0    J14
    set_property PACKAGE_PIN J14 [get_ports BASE_sc0]
    #HDIO_SC5    G13
    set_property PACKAGE_PIN G13 [get_ports BASE_sc5]
    #HDIO_SC6    J15
    set_property PACKAGE_PIN J15 [get_ports BASE_sc6]
    #HDIO_SC7    K15
    set_property PACKAGE_PIN K15 [get_ports BASE_sc7]
    #HDIO_SC10   A15
    set_property PACKAGE_PIN A15 [get_ports BASE_sc10_io]
    #HDIO_SC11   B15
    set_property PACKAGE_PIN B15 [get_ports BASE_sc11]
    #HDIO_SC12   C13
    set_property PACKAGE_PIN C13 [get_ports BASE_sc12]
    #HDIO_SC13   C14
    set_property PACKAGE_PIN C14 [get_ports BASE_sc13]
    #HDIO_SC14   E13
    set_property PACKAGE_PIN E13 [get_ports BASE_sc14]
    #HDIO_SC15   E14
    set_property PACKAGE_PIN E14 [get_ports BASE_sc15]
    #HDIO_SC16   A13
    set_property PACKAGE_PIN A13 [get_ports BASE_sc16]
    #HDIO_SC17   B13
    set_property PACKAGE_PIN B13 [get_ports BASE_sc17]
    #HDIO_SC18   A14
    set_property PACKAGE_PIN A14 [get_ports BASE_sc18]
    #HDIO_SC19   B14
    set_property PACKAGE_PIN B14 [get_ports BASE_sc19]
    set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc15sc0]
    set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc16sc5]
    set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc17sc6]
    set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc18sc7]
    set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc10_sc19io]
    
    # PLL
    #setset_property PACKAGE_PINIOSTANDARD AH6LVCMOS18 [get_ports {si570_clk_p[0]}BASE_sc11]
    #setset_property IOSTANDARD LVDSLVCMOS18 [get_ports {si570_clk_p[0]}BASE_sc12]
    #setset_property IOSTANDARD LVDSLVCMOS18 [get_ports {si570_clk_n[0]}]
    # Clocks
    #setBASE_sc13]
    set_property PACKAGE_PINIOSTANDARD J8LVCMOS18 [get_ports {B229_CLK1_clk_p[0]}BASE_sc14]
    #setset_property PACKAGE_PINIOSTANDARD F25LVCMOS18 [get_ports {B128_CLK0_clk_p[0]}]
    # SFP 
    #set_property PACKAGE_PIN G8BASE_sc15]
    set_property IOSTANDARD LVCMOS18 [get_ports {B230_CLK0_clk_p}]
    # B230_RX3_P
    #setBASE_sc16]
    set_property PACKAGE_PINIOSTANDARD A4LVCMOS18 [get_ports {SFP1BASE_rxp}sc17]
    # B230_TX3_P
    #setset_property PACKAGE_PINIOSTANDARD A8LVCMOS18 [get_ports {SFP1BASE_txp}sc18]
    # B230_RX2_P
    #setset_property PACKAGE_PINIOSTANDARD B2LVCMOS18 [get_ports {SFP2BASE_rxp}]
    # B230_TX2_P
    #set_property PACKAGE_PIN B6 [get_ports {SFP2_txp}]sc19]
    
    
    # Audio Codec
    #LRCLK		          J3J3:49 B47_L9_N
    #BCLK        		    J3:51 B47_L9_P
    #DAC_SDATA    	J3:53 B47_L7_N
    #ADC_SDATA    	J3:55 B47_L7_P
    
    #LRCLK G14
    set_property PACKAGE_PIN G14 [get_ports LRCLKI2S_lrclk ]
    #BCLK G15
    set_property PACKAGE_PIN G15 [get_ports BCLKI2S_bclk ]
    #DAC_SDATA E15
    set_property PACKAGE_PIN E15 [get_ports DAC I2S_sdin ]
    #ADC_SDATA ]F15
    set_property PACKAGE_PIN F15 [get_ports ADCI2S_SDATAsdout ]
    set_property IOSTANDARD LVCMOS18 [get_ports LRCLKI2S_lrclk ]
    set_property IOSTANDARD LVCMOS18 [get_ports BCLKI2S_bclk ]
    set_property IOSTANDARD LVCMOS18 [get_ports DACI2S_SDATAsdin ]
    set_property IOSTANDARD LVCMOS18 [get_ports ADCI2S_SDATAsdout ]

    Software Design - Vitis

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    Note:
    • optional chapter separate

    • sections for different apps

    For Vitis project creation, follow instructions from:

    Vitis

    Application

    Page properties
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    ----------------------------------------------------------

    FPGA Example

    scu

    MCS Firmware to configure SI5338 and Reset System.

    srec_spi_bootloader

    TE modified 20202021.2 SREC

    Bootloader to load app or second bootloader from flash into DDR

    Descriptions:

    • Modified Files: blconfig.h, bootloader.c
    • Changes:
      • Add some console outputs and changed bootloader read address.
      • Add bugfix for 2018.2 qspi flash

    xilisf_v5_11

    TE modified 20202021.2 xilisf_v5_11

    • Changed default Flash type to 5.

    ----------------------------------------------------------

    Zynq Example:

    fsbl

    TE modified 20202021.2 FSBL

    General:

    • Modified Files: main.c, fsbl_hooks.h/.c (search for 'TE Mod' on source code)
    • Add Files: te_fsbl_hooks.h/.c (for hooks and board)

    • General Changes: 
      • Display FSBL Banner and Device ID

    Module Specific:

    • Add Files: all TE Files start with te_*
      • READ MAC from EEPROM and make Address accessible by UBOOT (need copy defines on uboot platform-top.h)
      • CPLD access
      • Read CPLD Firmware and SoC Type
      • Configure Marvell PHY

    fsbl_flash

    TE modified 20202021.2 FSBL

    General:

    • Modified Files: main.c
    • General Changes:
      • Display FSBL Banner
      • Set FSBL Boot Mode to JTAG
      • Disable Memory initialisation

    ZynqMP Example:

    ----------------------------------------------------------

    zynqmp_fsbl

    TE modified 20202021.2 FSBL

    General:

    • Modified Files: xfsbl_main.c, xfsbl_hooks.h/.c, xfsbl_board.h/.c (search for 'TE Mod' on source code)
    • Add Files: te_xfsbl_hooks.h/.c (for hooks and board)
    • General Changes: 
      • Display FSBL Banner and Device Name

    Module Specific:

    • Add Files: all TE Files start with te_*
      • Si5338 Configuration
      • ETH+OTG Reset over MIO

    zynqmp_fsbl_flash

    TE modified 20202021.2 FSBL

    General:

    • Modified Files: xfsbl_initialisation.c, xfsbl_hw.h, xfsbl_handoff.c, xfsbl_main.c
    • General Changes:
      • Display FSBL Banner
      • Set FSBL Boot Mode to JTAG
      • Disable Memory initialisation


    zynqmp_pmufw

    Xilinx default PMU firmware.

    ----------------------------------------------------------

    General Example:

    hello_te0820

    Hello TE0820 is a Xilinx Hello World example as endless loop instead of one console output.

    u-boot

    U-Boot.elf is generated with PetaLinux. Vitis is used to generate Boot.bin.

    Template location: "<project folder>\sw_lib\sw_apps\"

    zynqmp_fsbl

    TE modified 20202021.2 FSBL

    General:

    • Modified Files: xfsbl_main.c, xfsbl_hooks.h/.c, xfsbl_board.h/.c (search for 'TE Mod' on source code)
    • Add Files: te_xfsbl_hooks.h/.c (for hooks and board)
    • General Changes: 
      • Display FSBL Banner and Device Name


    Module Specific:

    • Add Files: all TE Files start with te_*
      • Si5345 Configuration
      • OTG+PCIe Reset over MIO
      • I2C MUX for EEPROM MAC

    zynqmp_fsbl_flash

    TE modified 20202021.2 FSBL

    General:

    • Modified Files: xfsbl_initialisation.c, xfsbl_hw.h, xfsbl_handoff.c, xfsbl_main.c
    • General Changes:
      • Display FSBL Banner
      • Set FSBL Boot Mode to JTAG
      • Disable Memory initialisation

    zynqmp_pmufw

    Xilinx default PMU firmware.

    hello_te0808

    Hello TE0808 is a Xilinx Hello World example as endless loop instead of one console output.

    u-boot

    U-Boot.elf is generated with PetaLinux. Vitis is used to generate Boot.bin.

    Software Design -  PetaLinux

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    Note:
    • optional chapter separate

    • sections for linux

    • Add "No changes." or "Activate: and add List"

    For PetaLinux installation and project creation, follow instructions from:

    Config

    Start with petalinux-config or petalinux-config --get-hw-description

    Changes:

    • CONFIG_SUBSYSTEM_PRIMARY_SD_PSU_SD_1_SELECT=y
    • CONFIG_SUBSYSTEM_ETHERNET_PSU_ETHERNET_3_MAC=""

    U-Boot

    Start with petalinux-config -c u-boot

    Changes:

    • CONFIG_I2C_EEPROM=y
    • CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET=0xFA
    • CONFIG_SYS_I2C_EEPROM_ADDR=0x50
    • CONFIG_SYS_I2C_EEPROM_BUS=2
    • CONFIG_SYS_EEPROM_SIZE=256
    • CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=0
    • CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=0
    • CONFIG_SYS_I2C_EEPROM_ADDR_LEN=1
    • CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW=0
    • CONFIG_SD_BOOT=y

    Change platform-top.h:

    Code Block
    languagejs

    Device Tree

    Code Block
    languagejs
    /include/ "system-conf.dtsi" / { chosen { xlnx,eeprom = &eeprom; }; }; /* notes: serdes: https://github.com/Xilinx/linux-xlnx/blob/master/Documentation/devicetree/bindings/phy/phy-zynqmp.txt https://github.com/Xilinx/linux-xlnx/blob/master/include/dt-bindings/phy/phy.h */ /* default */ /* sata */ &sata { phy-names = "sata-phy"; phys = <&lane2 1 0 1 150000000>; }; /* SD */ &sdhci0 { // disable-wp; no-1-8-v; }; &sdhci1 { // disable-wp; no-1-8-v; }; /* USB */
    • .h, xfsbl_handoff.c, xfsbl_main.c
    • General Changes:
      • Display FSBL Banner
      • Set FSBL Boot Mode to JTAG
      • Disable Memory initialisation

    zynqmp_pmufw

    Xilinx default PMU firmware.

    hello_te0808

    Hello TE0808 is a Xilinx Hello World example as endless loop instead of one console output.

    u-boot

    U-Boot.elf is generated with PetaLinux. Vitis is used to generate Boot.bin.

    Software Design -  PetaLinux

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    Note:
    • optional chapter separate

    • sections for linux

    • Add "No changes." or "Activate: and add List"

    For PetaLinux installation and project creation, follow instructions from:

    Config

    Start with petalinux-config or petalinux-config --get-hw-description

    Changes:

    • select SD default instead of eMMC:
      • CONFIG_SUBSYSTEM_PRIMARY_SD_PSU_SD_1_SELECT=y
    • generate u-boot.dtb:
      • CONFIG_SUBSYSTEM_UBOOT_EXT_DTB=y
    • add new flash partition for bootscr and sizing
      • CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_PART0_SIZE=0xA00000
      • CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_PART2_SIZE=0x2000000
      • CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_PART3_NAME="bootscr"
      • CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_PART3_SIZE=0x80000

    U-Boot

    Start with petalinux-config -c u-boot

    Changes:

    • MAC from eeprom together with uboot and device tree settings:
      • CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET=0xFA
      • CONFIG_ENV_OVERWRITE=y
      • CONFIG_SYS_I2C_EEPROM_ADDR=0x50
      • CONFIG_SYS_I2C_EEPROM_BUS=7
    • Boot Modes:
      • CONFIG_QSPI_BOOT=y
      • CONFIG_SD_BOOT=y
      • # CONFIG_ENV_IS_IN_NAND is not set
      • CONFIG_BOOT_SCRIPT_OFFSET=0x2A40000

    Change platform-top.h:

    Code Block
    languagejs
    #no changes

    Device Tree

    Code Block
    languagejs
    titleproject-spec\meta-user\recipes-bsp\device-tree\files\system-user.dtsi
    /include/ "system-conf.dtsi"
    / {
      chosen {
        xlnx,eeprom = &eeprom;
      };
    };
    
    
    /*------------------ gtr --------------------*/
    
    //https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18841716/Zynq+Ultrascale+MPSOC+Linux+SIOU+driver
     
    / {
      refclk3:psgtr_dp_clock {
              compatible = "fixed-clock";
              #clock-cells = <0x00>;
              clock-frequency = <27000000>;
      };
       
       refclk2:psgtr_pcie_usb_clock {
               compatible = "fixed-clock";
               #clock-cells = <0x00>;
               clock-frequency = <100000000>;
       };
        
      refclk1:psgtr_sata_clock {
              compatible = "fixed-clock";
              #clock-cells = <0x00>;
              clock-frequency = <150000000>;
      };
        
      //refclk0:psgtr_unused_clock {
      //        compatible = "fixed-clock";
      //        #clock-cells = <0x00>;
      //        clock-frequency = <100000000>;
      //};
    };
     
    &psgtr {
      clocks = <&refclk1 &refclk2 &refclk3>;
      /* ref clk instances used per lane */
      clock-names = "ref1\0ref2\0ref3";
    };
     
     
     
    /*------------------ SD --------------------*/
    &sdhci0 {
        // disable-wp;
        no-1-8-v;
     
    };
     
    &sdhci1 {
        // disable-wp;
        no-1-8-v;
     
    };
     
     
    /*------------------ USB --------------------*/
    &dwc3_0 {
        status = "okay";
        dr_mode = "host";
        snps,usb3_lpm_capable;
        snps,dis_u3_susphy_quirk;
        snps,dis_u2_susphy_quirk;
        phy-names = "usb2-phy","usb3-phy";
        maximum-speed = "super-speed";
    };
    
    
    /*------------------ ETH PHY --------------------*/
    &gem3 {
        phy-handle = <&phy0>;
        phy0: phy0@1 {
            device_type = "ethernet-phy";
            reg = <1>;
        };
    };
     
    
    /*------------------ QSPI --------------------*/
    &qspi {
        #address-cells = <1>;
        #size-cells = <0>;
        status = "okay";
        flash0: flash@0 {
            compatible = "jedec,spi-nor";
            reg = <0x0>;
            #address-cells = <1>;
            #size-cells = <1>;
        };
    };
    
    
    /*------------------ I2C --------------------*/
    &i2c0 {
        i2cswitch@73 { // u
            compatible = "nxp,pca9548";
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <0x73>;
            i2c-mux-idle-disconnect;
            i2c@0 { // MCLK TEBF0808 SI5338A, 570FBB000290DG_unassembled
                #address-cells = <1>;
                #size-cells = <0>;
                reg = <0>;
            };
            i2c@1 { // SFP TEBF0808 PCF8574DWR
                #address-cells = <1>;
                #size-cells = <0>;
                reg = <1>;
            };
            i2c@2 { // PCIe
                #address-cells = <1>;
                #size-cells = <0>;
                reg = <2>;
            };
            i2c@3 { // SFP1 TEBF0808
                #address-cells = <1>;
                #size-cells = <0>;
                reg = <3>;
            };
            i2c@4 {// SFP2 TEBF0808
                #address-cells = <1>;
                #size-cells = <0>;
                reg = <4>;
            };
            i2c@5 { // TEBF0808 EEPROM
                #address-cells = <1>;
                #size-cells = <0>;
                reg = <5>;
                eeprom: eeprom@50 {
                    compatible = "atmel,24c08";
                    reg = <0x50>;
                  };
            };
            i2c@6 { // TEBF0808 FMC 
                #address-cells = <1>;
                #size-cells = <0>;
                reg = <6>;
            };
            i2c@7 { // TEBF0808 USB HUB
                #address-cells = <1>;
                #size-cells = <0>;
                reg = <7>;
            };
        };
        i2cswitch@77 { // u
            compatible = "nxp,pca9548";
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <0x77>;
            i2c-mux-idle-disconnect;
            i2c@0 { // TEBF0808 PMOD P1
                #address-cells = <1>;
                #size-cells = <0>;
                reg = <0>;
            };
            i2c@1 { // i2c Audio Codec
                #address-cells = <1>;
                #size-cells = <0>;
                reg = <1>;
                /*
                adau1761: adau1761@38 {
                    compatible = "adi,adau1761";
                    reg = <0x38>;
                };
                */
            };
            i2c@2 { // TEBF0808 Firefly A
                #address-cells = <1>;
                #size-cells = <0>;
                reg = <2>;
            };
            i2c@3 { // TEBF0808 Firefly B
                #address-cells = <1>;
                #size-cells = <0>;
                reg = <3>;
            };
            i2c@4 { //Module PLL Si5338 or SI5345
                #address-cells = <1>;
                #size-cells = <0>;
                reg = <4>;
            };
            i2c@5 { //TEBF0808 CPLD
                #address-cells = <1>;
                #size-cells = <0>;
                reg = <5>;
            };
            i2c@6 { //TEBF0808 Firefly PCF8574DWR
                #address-cells = <1>;
                #size-cells = <0>;
                reg = <6>;
            };
            i2c@7 { // TEBF0808 PMOD P3
                #address-cells = <1>;
                #size-cells = <0>;
                reg = <7>;
            };
        };
    };


    Code Block
    languagejs
    titleproject-spec\meta-user\recipes-bsp\uboot-device-tree\files\system-user.dtsi
    /include/ "system-conf.dtsi"
    / {
      chosen {
        xlnx,eeprom = &eeprom;
      };
    };
    
    
    /*------------------ gtr --------------------*/
    
    //https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18841716/Zynq+Ultrascale+MPSOC+Linux+SIOU+driver
     
    / {
      refclk3:psgtr_dp_clock {
              compatible = "fixed-clock";
              #clock-cells = <0x00>;
              clock-frequency = <27000000>;
      };
       
       refclk2:psgtr_pcie_usb_clock {
               compatible = "fixed-clock";
               #clock-cells = <0x00>;
               clock-frequency = <100000000>;
       };
        
      refclk1:psgtr_sata_clock {
              compatible = "fixed-clock";
              #clock-cells = <0x00>;
              clock-frequency = <150000000>;
      };
        
      //refclk0:psgtr_unused_clock {
      //        compatible = "fixed-clock";
      //        #clock-cells = <0x00>;
      //        clock-frequency = <100000000>;
      //};
    };
     
    &psgtr {
      clocks = <&refclk1 &refclk2 &refclk3>;
      /* ref clk instances used per lane */
      clock-names = "ref1\0ref2\0ref3";
    };
     
     
     
    /*------------------ SD --------------------*/
    &sdhci0 {
        // disable-wp;
        no-1-8-v;
     
    };
     
    &sdhci1 {
        // disable-wp;
        no-1-8-v;
     
    };
     
     
    /*------------------ USB --------------------*/
    &dwc3_0 {
        status = "okay";
        dr_mode = "host";
        snps,usb3_lpm_capable;
        snps,dis_u3_susphy_quirk;
        snps,dis_u2_susphy_quirk;
        phy-names = "usb2-phy","usb3-phy";
        phys = <&lane1 4 0 2 100000000>;
        maximum-speed = "super-speed";
    };
    
    
    /* ETH PHY */
    *------------------ ETH PHY --------------------*/
    &gem3 {
    	    phy-handle = <&phy0>;
    	    phy0: phy0@1 {
    		        device_type = "ethernet-phy";
    		        reg = <1>;
    	    };
    };
     
    
    /*------------------ QSPI --------------------*/
    
    &qspi {
        #address-cells = <1>;
        #size-cells = <0>;
        status = "okay";
        flash0: flash@0 {
            compatible = "jedec,spi-nor";
            reg = <0x0>;
            #address-cells = <1>;
            #size-cells = <1>;
        };
    };
    };
    
    /* I2C */
    
    
    
    /*------------------ I2C --------------------*/
    &i2c0 {
        i2cswitch@73 { // u
            compatible = "nxp,pca9548";
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <0x73>;
            i2c-mux-idle-disconnect;
            i2c@0 { // MCLK TEBF0808 SI5338A, 570FBB000290DG_unassembled
                #address-cells = <1>;
                #size-cells = <0>;
                reg = <0>;
            };
            i2c@1 { // SFP TEBF0808 PCF8574DWR
                #address-cells = <1>;
                #size-cells = <0>;
                reg = <1>;
            };
            i2c@2 { // PCIe
                #address-cells = <1>;
                #size-cells = <0>;
                reg = <2>;
            };
            i2c@3 { // SFP1 TEBF0808
                #address-cells = <1>;
                #size-cells = <0>;
                reg = <3>;
            };
            i2c@4 {// SFP2 TEBF0808
                #address-cells = <1>;
                #size-cells = <0>;
                reg = <4>;
            };
            i2c@5 { // TEBF0808 EEPROM
                #address-cells = <1>;
                #size-cells = <0>;
                reg = <5>;
                eeprom: eeprom@50 {
    	                compatible = "atmel,24c08";
    	                reg = <0x50>;
    	              };
            };
            i2c@6 { // TEBF0808 FMC  
                #address-cells = <1>;
                #size-cells = <0>;
                reg = <6>;
            };
            i2c@7 { // TEBF0808 USB HUB
                #address-cells = <1>;
                #size-cells = <0>;
                reg = <7>;
            };
        };
        i2cswitch@77 { // u
            compatible = "nxp,pca9548";
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <0x77>;
            i2c-mux-idle-disconnect;
            i2c@0 { // TEBF0808 PMOD P1
                #address-cells = <1>;
                #size-cells = <0>;
                reg = <0>;
            };
            i2c@1 { // i2c Audio Codec
                #address-cells = <1>;
                #size-cells = <0>;
                reg = <1>;
    			            /*
                adau1761: adau1761@38 {
                    compatible = "adi,adau1761";
                    reg = <0x38>;
                };
    			            */
            };
            i2c@2 { // TEBF0808 Firefly A
                #address-cells = <1>;
                #size-cells = <0>;
                reg = <2>;
            };
            i2c@3 { // TEBF0808 Firefly B
                #address-cells = <1>;
                #size-cells = <0>;
                reg = <3>;
            };
            i2c@4 { //Module PLL Si5338 or SI5345
                #address-cells = <1>;
                #size-cells = <0>;
                reg = <4>;
            };
            i2c@5 { //TEBF0808 CPLD
                #address-cells = <1>;
                #size-cells = <0>;
                reg = <5>;
            };
            i2c@6 { //TEBF0808 Firefly PCF8574DWR
                #address-cells = <1>;
                #size-cells = <0>;
                reg = <6>;
            };
            i2c@7 { // TEBF0808 PMOD P3
                #address-cells = <1>;
                #size-cells = <0>;
                reg = <7>;
            };
        };
    };
    
    
    
    
    

    FSBL patch

    Must be add manually, see template

    Kernel

    Start with petalinux-config -c kernel

    Changes:

    • Only needed to fix JTAG Debug issue:
      • # CONFIG_CPU_IDLE is not set
      • # CONFIG_CPU_FREQ is not set
      • CONFIG_EDAC_CORTEX_ARM64=y
    • # CONFIG_CPU_IDLE is not set
    • # CONFIG_CPU_FREQ is not setSupport PCIe memory card
      • CONFIG_NVME_CORE=y
      • CONFIG_BLK_DEV_NVME=y
      • # CONFIG_NVME_MULTIPATH is not set
      • # CONFIG_NVME_HWMON is not set
      • # CONFIG_NVME_TCP is not set
      • CONFIG_NVME_TARGET=y
      • # CONFIG_NVME_TARGET_
      LOOP
      • PASSTHRU is not set
      • # CONFIG_NVME_TARGET_
      FC
      • LOOP is not set
      • # CONFIG_NVME_TARGET_
      TCP
      • FC is not set
      • # CONFIG
      _NVM=y
      • _NVME_TARGET_TCP is not set
      • CONFIG_
      NVM
      • SATA_
      PBLK
      • AHCI=y
      • CONFIG_SATA_
      NVM
      • MOBILE_
      PBLK
      • LPM_
      DEBUG
      • POLICY=
      y
      • 0
      • CONFIG_
      EDAC_CORTEX_ARM64
      • NVM=y
      • CONFIG_
      SATA
      • NVM_
      AHCI
      • PBLK=y
      • CONFIG_
      SATA
      • NVM_
      MOBILE
      • PBLK_
      LPM_POLICY
      • DEBUG=
      0
      • y

    Rootfs

    Start with petalinux-config -c rootfs

    Changes:

    • For web server app:
      • CONFIG_
      i2c
      • busybox-
      tools
      • httpd=y
    • For additional test tools only:
      • CONFIG_
      busybox
      • i2c-
      httpd
      • tools=y
      (for web server app)
      • CONFIG_packagegroup-petalinux-utils=y    (util-linux,cpufrequtils,bridge-utils,mtd-utils,usbutils,pciutils,canutils,i2c-tools,smartmontools,e2fsprogs)

    Applications

    See "<project folder>\os\petalinux\project-spec\meta-user\recipes-apps\"

    startup

    Script App to load init.sh from SD Card if available.

    webfwu

    Webserver application suitable for Zynq ZynqMP access. Need busybox-httpd

    Additional Software

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    Note:
    • Add description for other Software, for example SI CLK Builder ...
    • SI5338 and SI5345 also Link to:

    SI5345

    File location "<project folder>/misc/PLL/Si5345_B/Si5345-*.slabtimeproj"

    General documentation how you work with these project will be available on Si5345

    Appx. A: Change History and Legal Notices

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    Document Change History

    To get content of older revision go to "Change History" of this page and select older document revision number.

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    Description

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    infoTypeModified by
    typeFlat

    • typo
    2022-03.16v.48Manuela Strücker
    • 2021.2 release
    • update board files
    2022-02-03v.47John Hartfiel
    • Typo correction on key features section
    2021-07-15v.46Manuela Strücker
    • Document Style update
    2021-05-12v.44John Hartfiel
    • update board files
    • update design
    2021-02-05v.43John Hartfiel
    • 2020.2 release
    • document style update
    2020-11-06v.41John Hartfiel
    • typo bugfix  for programming part
    2020-09-29v.40John Hartfiel
    • new assembly variants
    2020-03-25v.37John Hartfiel
    • script update
    2020-02-25v.35John Hartfiel
    • Update requirement section
    2020-01-23v.34John Hartfiel
    • new assembly variants
    • Release 2019.2
    2019-08-09v.32John Hartfiel
    • new assembly variants
    • small FSBL update
    • minor document style update
    2019-05-07v.29John Hartfiel
    • Release 2018.3
    2018-08-09v.27John Hartfiel
    • Release 2018.2

    2018-05-25

    v.21John Hartfiel
    • Solved known issues

    2018-04-30

    v.19John Hartfiel
    • Update known issues

    2018-03-29

    v.18John Hartfiel
    • New assembly variant
    2018-02-08v.16John Hartfiel
    • Solved known issues
    2018-01-29v.10John Hartfiel
    • Update known issues
    2018-01-18v.8John Hartfiel
    • Update documentation only
    2018-01-17v.7John Hartfiel
    • Update design
    2018-01-15v.4John Hartfiel
    • Release 2017.4
    2017-12-20v.2John Hartfiel
    • Release 2017.2

    All

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    typeFlat



    Legal Notices

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    IN:Legal Notices



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