Versions Compared

Key

  • This line was added.
  • This line was removed.
  • Formatting was changed.

...

Scroll Only (inline)
Refer to http://trenz.org/max1000-info for the current online version of this manual and other available documentation.

Key Features

  • Intel Cyclone 10LP 10CL025 MAX 10 10M08 FPGA SoC

  • 8 MByte SDRAM
  • 8 MByte QSPI Flash memory

  • ST Microelectronics LIS3DH 3-axis accelerometer
  • JTAG and UART over Micro USB2 connector
  • 1x6 pin header for JTAG access to FPGA SoC
  • 1x PMOD header providing 8 GPIOs
  • 2x 14-pin headers (2,54 mm pitch) providing 22 GPIOs with 7 analog inputs as alternative function

  • 1x 3-pin header providing 2 analog inputs or 1 GPIO
  • 8x user LEDs

  • 1x user push button
  • 5.0V single power supply with on-board voltage regulators
  • Size: 61.5 x 25 mm

...

Scroll Title
anchorFigure_1
titleFigure 1: TEI0003-02 block diagram
Scroll Ignore

draw.io Diagram
borderfalse
viewerToolbartrue
fitWindowfalse
diagramNameTEI0001 block diagram
simpleViewerfalse
width
linksauto
tbstylehidden
lboxtrue
diagramWidth641
revision67

Scroll Only

Main Components

...

Optionally 1x6 male pin header J4 can be fitted on board for access to the JTAG interface between FTDI and FPGA on board. The pin assignment of header J4 is shown on table below:

JTAG SignalPin on Header J4Note
TCK3-
TDI5-
TDO4-
TMS6-
JTAGEN2leave floating when use JTAG interface, otherwise signals on FPGA are GPIOs

Table 4: optional JTAG pin header

...

Serial Memory U5 PinSignal Schematic NameConnected toNotes
Pin 1, CSF_CSFPGA bank 8, pin B3
chip select
Pin 6, CLKF_CLKFPGA bank 18, pin A3clock
Pin 5, SI/IO0F_DIFPGA bank 18, pin A2data in / out
Pin 7, HOLD/IO3NSTATUS

FPGA bank 18, pin C4

data in / out, configuration dual-purpose pin of FPGA
Pin 3, WP/IO2DEVCLRNFPGA bank 8, pin B9data in / out, configuration dual-purpose pin of FPGA
Pin 2, SO/IO1F_DOFPGA bank 8, pin B2data in / out

...

FTDI Chip U3 PinSignal Schematic NameConnected toNotes
Pin 12, ADBUS0TCKFPGA bank 11B, pin H3G2
JTAG interface
Pin 13, ADBUS1TDIFPGA bank 11B, pin H4F5
Pin 14, ADBUS2TDOFPGA bank 11B, pin J4F6
Pin 15, ADBUS3TMS

FPGA bank 11B, pin J5G1

Pin 32, BDBUS0BDBUS0FPGA bank 8, pin A4user configurable
Pin 33, BDBUS1BDBUS1FPGA bank 8, pin B4
user configurable
Pin 34, BDBUS2BDBUS2FPGA bank 8, pin B5user configurable
Pin 35, BDBUS3BDBUS3FPGA bank 8, pin A6user configurable
Pin 37, BDBUS4BDBUS4FPGA bank 8, pin B6
user configurable
Pin 38, BDBUS5BDBUS5FPGA bank 8, pin A7user configurable

...

 Date

Revision

ContributorsDescription

Page info
modified-date
modified-date
dateFormatyyyy-MM-dd

Page info
infoTypeCurrent version
dateFormatyyyy-MM-dd
typeFlat

Ali Naseri
  • small corrections

2018-06-29

v.17


Ali Naseri

  • First TRM release

...