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Refer to http://trenz.org/max1000-info for the current online version of this manual and other available documentation. |
Key Features
Intel Cyclone 10LP 10CL025 MAX 10 10M08 FPGA SoC
- 8 MByte SDRAM
8 MByte QSPI Flash memory
- ST Microelectronics LIS3DH 3-axis accelerometer
- JTAG and UART over Micro USB2 connector
- 1x6 pin header for JTAG access to FPGA SoC
- 1x PMOD header providing 8 GPIOs
2x 14-pin headers (2,54 mm pitch) providing 22 GPIOs with 7 analog inputs as alternative function
- 1x 3-pin header providing 2 analog inputs or 1 GPIO
8x user LEDs
- 1x user push button
- 5.0V single power supply with on-board voltage regulators
- Size: 61.5 x 25 mm
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Optionally 1x6 male pin header J4 can be fitted on board for access to the JTAG interface between FTDI and FPGA on board. The pin assignment of header J4 is shown on table below:
| JTAG Signal | Pin on Header J4 | Note |
|---|---|---|
| TCK | 3 | - |
| TDI | 5 | - |
| TDO | 4 | - |
| TMS | 6 | - |
| JTAGEN | 2 | leave floating when use JTAG interface, otherwise signals on FPGA are GPIOs |
Table 4: optional JTAG pin header
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| Serial Memory U5 Pin | Signal Schematic Name | Connected to | Notes |
|---|---|---|---|
| Pin 1, CS | F_CS | FPGA bank 8, pin B3 | chip select |
| Pin 6, CLK | F_CLK | FPGA bank 18, pin A3 | clock |
| Pin 5, SI/IO0 | F_DI | FPGA bank 18, pin A2 | data in / out |
| Pin 7, HOLD/IO3 | NSTATUS | FPGA bank 18, pin C4 | data in / out, configuration dual-purpose pin of FPGA |
| Pin 3, WP/IO2 | DEVCLRN | FPGA bank 8, pin B9 | data in / out, configuration dual-purpose pin of FPGA |
| Pin 2, SO/IO1 | F_DO | FPGA bank 8, pin B2 | data in / out |
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| FTDI Chip U3 Pin | Signal Schematic Name | Connected to | Notes |
|---|---|---|---|
| Pin 12, ADBUS0 | TCK | FPGA bank 11B, pin H3G2 | JTAG interface |
| Pin 13, ADBUS1 | TDI | FPGA bank 11B, pin H4F5 | |
| Pin 14, ADBUS2 | TDO | FPGA bank 11B, pin J4F6 | |
| Pin 15, ADBUS3 | TMS | FPGA bank 11B, pin J5G1 | |
| Pin 32, BDBUS0 | BDBUS0 | FPGA bank 8, pin A4 | user configurable |
| Pin 33, BDBUS1 | BDBUS1 | FPGA bank 8, pin B4 | user configurable |
| Pin 34, BDBUS2 | BDBUS2 | FPGA bank 8, pin B5 | user configurable |
| Pin 35, BDBUS3 | BDBUS3 | FPGA bank 8, pin A6 | user configurable |
| Pin 37, BDBUS4 | BDBUS4 | FPGA bank 8, pin B6 | user configurable |
| Pin 38, BDBUS5 | BDBUS5 | FPGA bank 8, pin A7 | user configurable |
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| Date | Revision | Contributors | Description | ||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
| Ali Naseri |
| ||||||||||||||||
2018-06-29 | v.17 | Ali Naseri |
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