Versions Compared

Key

  • This line was added.
  • This line was removed.
  • Formatting was changed.

...

BankConnector DesignatorI/O Signal CountBank VoltageNotes
2J14 I/O's3.3V-
J68 I/O'sPmod connector
5J12 I/O's3.3V-
J29 I/O's2 I/O's of bank 5 can be pulled-up to 3.3V (4K7 resistors)
1AJ17x analog inputs or GPIO's, 1x Analog reference voltage (AREF)3.3Vanalog pins usable as GPIO's as alternative function

J31x analog inputs or GPIO, 1x dedicated analog input
1BJ4JTAG interface and 'JTAGEN' signal (5 I/O's)3.3VJTAG enable signal (JTAGEN) on pin J4-2, switch between user I/O pins and JTAG pin functions

Table 2: General overview of single ended I/O signals connected to pin headers and connectors

FPGA I/O banks

Table below contains the signals and interfaces of the FPGA banks connected to pins and peripherals of the board:

BankI/O's CountConnected toNotes
241x14 pin header, J1user GPIO's
8Pmod connector, J6user GPIO's
1clock oscillator, U712.0000 MHz reference clock input
1optional clock oscillator, U6oscillator not fitted, footprints available for Microchip MEMS oscillator
591x14 pin header, J22 I/O's (D11, D12) of bank 5 can be pulled-up to 3.3V (4K7 resistors) with 1 I/O (D12_R) of same Bank and 1 I/O (D11_R) of bank 6
6188 MByte SDRAM 166MHz, U216bit SDRAM memory interface
3228 MByte SDRAM 166MHz, U216bit SDRAM memory interface
6LIS3DH 3-axis accelerometer, U44 I/O's for SPI interface, 2 interrupt lines
1A81x14 pin headers J17 analog inputs or GPIO's, 1 pin analog reference voltage input
2pin headers J11 analog inputs or GPIO, 1 dedicated analog input
1B5pin header J44 I/O's JTAG interface and 1x 'JTAGEN' signal to switch the JTAG pins to user GPIO's if drive this pin to GND
88LEDs D2 ... D9Red user LEDs
6QSPI Flash memory, U56 pins Quad SPI interface, 2 of them pulled up as configuration pins during initialization
6FTDI FT2232H JTAG/UART Adapter, U36 pins configurable as GPIO/UART or other serial interfaces
1Red LED, D10Configuration DONE Led (ON when configuration in progress, OFF when configuration is done)
1User button S2user configurable
1Reset button S1 and pin J2-10low active reset line for FPGA reconfiguration

Table 3: General overview of FPGA I/O banks

JTAG Interface

Primary JTAG access to the FPGA SoC device U1 is provided through Micro USB2 B connector J9. The JTAG interface is created by the FTDI FT2232H USB2 to JTAG/UART adapter IC U3. 

...

SDRAM I/O Signals

Signal Schematic Name

Connected toNotes
Address inputs

A0 ... A13

bank 3-
Bank address inputs

BA0 / BA1

bank 3

-
Data input/output

DQ0 ... DQ15

bank 6

-
Data mask

DQM0 ... DQM1

bank 6

-
ClockCLKbank 3
Control Signals

CS

bank 3

Chip select

CKE

bank 3

Clock enable

RAS

bank 3

Row Address Strobe

CAS

bank 3

Column Address Strobe

WEbank 3Write Enable

Table 6: 16bit SDRAM memory interface

FTDI FT2232H Chip

The FTDI chip U3 converts signals from USB2 to a variety of standard serial and parallel interfaces. Refer to the FTDI data sheet to get information about the capacity of the FT2232H chip.
FTDI FT2232H chip is used in MPPSE mode for JTAG, 6 I/O's of Channel B are routed to FPGA bank 8 of the FPGA SoC and are usable for example as GPIOs, UART or other standard interfaces.

...

FTDI Chip U3 PinSignal Schematic NameConnected toNotes
Pin 12, ADBUS0TCKFPGA bank 11B, pin H3G2
JTAG interface
Pin 13, ADBUS1TDIFPGA bank 11B, pin H4F5
Pin 14, ADBUS2TDOFPGA bank 11B, pin J4F6
Pin 15, ADBUS3TMS

FPGA bank 11B, pin J5G1

Pin 32, BDBUS0BDBUS0FPGA bank 8, pin A4user configurable
Pin 33, BDBUS1BDBUS1FPGA bank 8, pin B4
user configurable
Pin 34, BDBUS2BDBUS2FPGA bank 8, pin B5user configurable
Pin 35, BDBUS3BDBUS3FPGA bank 8, pin A6user configurable
Pin 37, BDBUS4BDBUS4FPGA bank 8, pin B6
user configurable
Pin 38, BDBUS5BDBUS5FPGA bank 8, pin A7user configurable

Table 7: FTDI chip interfaces and pins

3-Axis Accelerometer

On the TEI0001 FPGA board there is a 3-axis accelerometer present. This accelerometer provided by ST Microelectronics LIS3DH and offers many function to detect motion and has also a temperature sensor integrated. It also has a FIFO buffer for storing output data. The sensor is connected to the FPGA through SPI interface and two interrupt lines.

Accelerometer U4 PinSignal Schematic NameConnected toNotes
Pin 11, INT1SEN_INT1FPGA bank 3, pin J5
Interrupt lines
Pin 9, INT2SEN_INT2FPGA bank 3, pin L4
Pin 6, SDA/SDI/SDOSEN_SDIFPGA bank 3, pin J7SPI interface


Pin 7, SDO/SA0SEN_SDO

FPGA bank 3, pin K5

Pin 4, SCL/SPCSEN_SPCFPGA bank 3, pin J6
Pin 8, CSSEN_CSFPGA bank 3, pin L5
Pin 13, ADC3ADC35VSense 5V input voltage

Table 8: 3-axis accelerometer interfaces and pins

System Clock Oscillator

The FPGA SoC module has following reference clocking signals provided by on-board oscillators:

...

LEDColorSignal Schematic NameFPGANotes
D1Green--Indicating 3.3V board supply voltage
D2Red'LED1'bank 8, pin A8user
D3Red'LED2'bank 8, pin A9user
D4Red'LED3'bank 8, pin A11user
D5Red'LED4'bank 8, pin A10user
D6Red'LED5'bank 8, pin B10user
D7Red'LED6'bank 8, pin C9user
D8Red'LED7'bank 8, pin C10user
D9Red'LED8'bank 8, pin D8user
D10Red'CONF_DONE'bank 8, pin C5indication configuration is DONE when LED is off

Table 10: LEDs of the module

Push Buttons

The FPGA module is equipped with two push buttons S1 and S2:

ButtonSignal Schematic NameFPGANotes
S1'USER_BTN'bank 8, pin E6user configurable
S2'RESET'bank 8, pin E7FPGA reset

Table 11: Push buttons of the module

Connectors

All connectors are are for 100mil headers, all connector locations are in 100mil (2.54mm) grid. The module's PCB provides footprints to mount and solder optional pin headers, if those are not factory-fitted on module.

...

FPGADesignTypical Power, 25C ambient
Intel MAX 10 10M08 FPGA SoCNot configuredTBD*

Table 12: Module power consumption

*TBD - To Be Determined.

Actual power consumption depends on the FPGA design and ambient temperature.

...

Connector DesignatorVCC / VCCIO Schematic NameVoltageDirectionPinsNotes
J25V5.0VOutPin 14-
VIN5.0VInPin 13-
3.3V3.3VOutPin 12-
J6

3.3V

3.3V

OutPin 6, 12-
J9

USB_VBUS

5.0VInPin 1-

Table 13: Connector power pin description

Bank Voltages

Bank

Voltage

Voltage Range

23.3Vall bank voltages fixed
33.3V
53.3V
63.3V
1A3.3V
1B3.3V
83.3V

Table 14: FPGA SoC VCCO bank voltages

...

Parameter

MinMax

Units

Reference document

VIN supply voltage (5.0V nominal)

-0.3

6.0

V

EP53A7HQI datasheet
I/O Input voltage for FPGA I/O bank-0.54.12VIntel MAX 10 datasheet

Storage Temperature

-40

+90

°C

LED R6C-AL1M2VY/3T datasheet

Table 15: Absolute maximum ratings

Recommended Operating Conditions

ParameterMinMaxUnitsReference document
VIN supply voltage (5.0V nominal)4.755.25Vsame as USB-VBUS specification
I/O Input voltage for FPGA I/O bank–0.53.6VIntel MAX 10 datasheet
Operating temperature range0+70

°C

Winbond datasheet W9864G6GT

Table 16: Recommended operating conditions

Note
Please check Intel MAX 10 datasheet  for complete list of absolute maximum and recommended operating ratings for the FPGA device.

...

DateRevision

Notes

PCNDocumentation Link
-03Current available revision-TEI0001-03
-

02

First Production Release

-TEI0001-02
-01Prototypes-TEI0001-01

Table 17: Module hardware revision history

Hardware revision number is printed on the PCB board together with the module model number separated by the dash.

Scroll Title
anchorFigure_5
titleFigure 5: Module hardware revision number

...

 Date

Revision

ContributorsDescription

Page info
modified-date
modified-date
dateFormatyyyy-MM-dd

Page info
infoTypeCurrent version
dateFormatyyyy-MM-dd
typeFlat

Ali Naseri
  • small corrections

2018-06-29

v.17


Ali Naseri

  • First TRM release

Table 18: Document change history

Disclaimer

Include Page
IN:Legal Notices
IN:Legal Notices