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By default the configuration mode pins of the FPGA are set to load the FPGA design from the serial configuration memory , hence the FPGA is configured from serial configuration memory at system start-up. The JTAG interface of the module is provided for storing the initial FPGA configuration data to the serial configuration memory.
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Table 2: General overview of single ended I/O signals connected to pin headers and connectors
FPGA I/O banks
| BankVCCIO | I/O's Count | Connected to | Notes | |
|---|---|---|---|---|
| 13.3V | 6 | LIS3DH digital motion sensor, U4 | SPI interface, 2 interrupt lines | |
| 4 | 1x6 pin header, J4 | JTAG interface | ||
| 4 | 2 MByte serial configuration memory, U5 | FPGA configuration memory with active serial (AS) x1 interface | ||
| 1 | J2-10, push button S1 | low active reset input | ||
| 2 | 3.3V | 9 | 1x14 pin header, J2 | GPIOs (2 I/O's of bank 2 can be pulled-up to 3.3V (4K7 resistors) with 2 I/O's of same Bank or pins can be shared) |
| 3 | 3.3V | 8 | LEDs D2 ... D9 | 8 x red user LEDs |
| 8 | FTDI FT2232H JTAG/UART Adapter, U3 | configurable as GPIO/UART or other serial interfaces | ||
| 1 | push button S2 | user button | ||
| 43.3V | 10 | pin headers J1, J3 | GPIOs | |
| 5 | 3.3V | 6 | pin headers J1 | GPIOs |
| 6 | 3.3V | 8 | Pmod connector J6 | GPIOs |
| 1 | Red LED, D10 | Configuration DONE Led (ON when configuration in progress, OFF when configuration is done) | ||
| 73.3V | 19 | 8 Mbyte SDRAM 166MHz, U2 | 16bit SD-RAM memory interface | |
| 83.3V | 21 | 8 Mbyte SDRAM 166MHz, U2 | 16bit SD-RAM memory interface
Table 3: General overview of FPGA I/O banks
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On the TEI0003 FPGA board there is a 3-axis accelerometer present. This accelerometer provided by ST Microelectronics LIS3DH and offers many function to detect motion and has also a temperature sensor integrated. It also has a FIFO buffer for storing output data. The sensor is connected to the FPGA through SPI interface and two interrupt lines.
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Table 18: Document change history
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