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Template Revision

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3.1

Design Name always "TE Series Name" + Design name, for example "TE0720 Test Board"

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  • Change List 3.0 to 3.1
    • Fix problem with pdf export and side scroll bar
    • update 19.2 to 20.2
    • add prebuilt content option
  • Change List 2.9 to 3.0
    • add fix table of content
    • add table size as macro
    • removed page initial creator

Custom_table_size_100

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Important General Note:

  • Export PDF to download, if vivado revision is changed!

  • Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro

    • Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)
      • Figure template (note: inner scroll ignore/only only with drawIO object):

        Scroll Title
        anchorFigure_xyz
        titleText


        Scroll Ignore

        Create DrawIO object here: Attention if you copy from other page, use


        Scroll Only

        image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed



      • Table template:

        • Layout macro can be use for landscape of large tables
        • Set column width manually(can be used for small tables to fit over whole page) or leave empty (automatically)

      • Scroll Title
        anchorTable_xyz
        titleText

        Scroll Table Layout
        orientationportrait
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        ExampleComment
        12



  • ...

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Table of contents

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outlinetrue

Overview

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Notes :

Linux with basic periphery of TE0807 Starterkit (TEBF0808 Carrier).

Refer to http://trenz.org/te0807-info for the current online version of this manual and other available documentation.

Key Features

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Notes :

  • Add basic key futures, which can be tested with the design


Excerpt
  • Vitis/Vivado 2019.2
  • TEBF0808
  • Linux
  • USB
  • ETH
  • MAC from EEPROM
  • PCIe
  • SATA
  • SD
  • I2C
  • RGPIO
  • DP
  • user LED access
  • Modified FSBL for Si5338 programming / petalinux patch
  • Special FSBL for QSPI Programming

Revision History

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Notes :

  • add every update file on the download
  • add design changes on description


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titleDesign Revision History

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DateVivadoProject BuiltAuthorsDescription

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2021-

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02-

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08

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2020.2TE0807-StarterKit_noprebuilt-vivado_

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2020.2-build_

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1_

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20210208094502.zip
TE0807-StarterKit-vivado_

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2020.2-build_

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1_

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20210208093620.zipJohn Hartfiel

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  • 2020.2 update

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  • add boot.scr file
  • device tree has change
  • petalinuxx fsbl patch (betaversion)
2020-10-062019.2TE0807-StarterKit_noprebuilt-vivado_

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2019.

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2-build_

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15_

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20201006122416.zip
TE0807-StarterKit

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-vivado_

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2019.

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2-build_

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15_

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20201006122402.zipJohn Hartfiel

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  • new assembly variants

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2020-03-252019.2TE0807-StarterKit_noprebuilt-vivado_

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2019.2-build_

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8_

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20200325082944.zip
TE0807-StarterKit-vivado_

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2019.2-build_

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8_

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20200325082924.zipJohn Hartfiel

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  • new assembly variant

...

  • script update
2020-02-192019.2TE0807-StarterKit_noprebuilt-vivado_

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2019.2-build_

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5_

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20200219124225.zip
TE0807-StarterKit-vivado_

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2019.2-build_

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5_

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20200219124212.zipJohn Hartfiel

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  • small petalinux changes
  • IO renaming
  • PL Design changes
  • additional notes for FSBL generated with Win SDK
  • changed *.bif
  • add missing linux Boot.bin
  • small update for  SI configuration (FSBL)
2020-01-272019.2TE0807-StarterKit_noprebuilt-vivado_

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2019.

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2-build_

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4_

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20200127075822.zip
TE0807-StarterKit-vivado_

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2019.

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2-build_

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4_

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20200127075809.zipJohn Hartfiel

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  • solved Linux Flash issue
  • 2019.2 update
  • Vitis support
  • FSBL SI programming procedure update 
  • petalinux device tree and u-boot update
2019-05-222018.3TE0807-StarterKit

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-vivado_

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2018.

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3-build_

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06_

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20190522132448.zip
TE0807-StarterKit_noprebuilt-vivado_

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2018.

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3-build_

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06_

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20190522132504.zipJohn Hartfiel

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  • same CLK for VIO
  • TE Script update
  • rework of the FSBLs
  • some additional Linux features
  • MAC from EEPROM
  • new assembly variants
  • remove special compiler flags, which was needed in 2018.2
  • ES2 prebuilt files are not included
2019-02-072018.2TE0807-StarterKit_noprebuilt-vivado_2018.2-build_04_20190207111631.zip
TE0807-StarterKit

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-vivado_

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2018.

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2-build_

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04_

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20190207111616.zipJohn Hartfiel

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  • new assembly variant
2018-

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09-

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04

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2018.

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2TE0807-StarterKit_noprebuilt-vivado_

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2018.

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2-build_

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03_

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20180904122245.zip
TE0807-StarterKit-vivado_

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2018.

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2-build_

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03_

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Do not use HW Manager connection, or if debugging is nessecary:

  1. Boot linux with usb terminal
  2. From the terminal: root root mount ifconfig eth0
  3. Open two new SSH terminals via ethernet: root root , run user application ...
  4. Exit and close the usb terminal

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Requirements

Software

20180904121600.zipJohn Hartfiel

...

  • initial release

Release Notes and Know Issues

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Notes :
  • add known Design issues and general notes for the current revision
  • do not delete known issue, add fixed version time stamp if  issue fixed

...

anchorTable_KI
titleKnown Issues
  • small petalinux changes
  • IO renaming
  • PL Design changes
  • additional notes for FSBL generated with Win SDK
  • changed *.bif
2018-05-242017.4TE0807-StarterKit_noprebuilt-vivado_2017.4-build_10_20180524150124.zip
TE0807-StarterKit-vivado_2017.4-build_10_20180524150106.zip
John Hartfiel
  • solved Linux Flash issue
2018-02-062017.4TE0807-StarterKit_noprebuilt-vivado_2017.4-build_05_20180206082637.zip
TE0807-StarterKit-vivado_2017.4-build_05_20180206082621.zip
John Hartfiel
  • same CLK for VIO
2018-02-052017.4TE0807-StarterKit-vivado_2017.4-build_05_20180205101252.zip
TE0807-StarterKit_noprebuilt-vivado_2017.4-build_05_20180205101306.zip
John Hartfiel
  • solved JTAG/Linux issue
2018-01-182017.4TE0807-StarterKit_noprebuilt-vivado_2017.4-build_05_20180118152938.zip
TE0807-StarterKit-vivado_2017.4-build_05_20180118152922.zip
John Hartfiel
  • initial release


Release Notes and Know Issues

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Notes :

    ...

    • add known Design issues and general notes for the current revision
    • do not delete known issue, add fixed version time stamp if  issue fixed


    Scroll Title
    anchorTable_

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    KI
    title

    ...

    Known Issues

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    Issues

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    Description

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    Workaround/SolutionTo be fixed version
    Flash access on LinuxDevice tree is not correct on Linuxadd compatibility to "compatible “jedec,spi-nor”"Solved with 20180524 update
    USB UART Terminal is blocked / SDK Debugging is blockedThis happens only with 2017.4 Linux , when JTAG connection is established on Vivado HW Manager.

    Do not use HW Manager connection, or if debugging is nessecary:

    1. Boot linux with usb terminal
    2. From the terminal: root root mount ifconfig eth0
    3. Open two new SSH terminals via ethernet: root root , run user application ...
    4. Exit and close the usb terminal
    Solved with 20180205 update


    Requirements

    Software

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    Notes :

    • list of software which was used to generate the design

    Basic description of TE Board Part Files is available on TE Board Part Files.

    Complete List is available on <design name>/board_files/*_board_files.csv

    Design supports following modules:


    Scroll Title
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    SW
    title

    ...

    Software

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    SoftwareVersionNote
    Vitis2020.2needed, Vivado is included into Vitis installation
    PetaLinux2020.2needed
    SI ClockBuilder Pro---optional


    Hardware

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    Notes :

    • list of software which was used to generate the design

    Basic description of TE Board Part Files is available on TE Board Part Files.

    Complete List is available on <design name>/board_files/*_board_files.csv

    Design supports following modules:

    Scroll Title
    anchorTable_HWM
    titleHardware Modules

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    Module ModelBoard Part Short NamePCB Revision SupportDDRQSPI FlashEMMCOthersNotes
    TE0807-01-07EV-ES   es2_2gb      REV01    2GB      64MB       NA         NA     Not longer supported by vivado
    TE0807-02-07EV-1E   7ev_1e_4gb   REV02    4GB      

    ...

    128MB      NA         NA     NA                               
    TE0807-02-

    ...

    07EV-

    ...

    1EK  

    ...

    7ev_

    ...

    1e_4gb   REV02    4GB      128MB       NA         NA     

    ...

    with heat sink                 
    TE0807-02-

    ...

    4BE21-A   

    ...

    4eg_

    ...

    1e_4gb   REV02    4GB      128MB      NA         NA     NA                               
    TE0807-02-

    ...

    7DE21-A   

    ...

    7ev_

    ...

    1e_4gb   REV02    4GB      128MB      NA         NA     NA                               
    TE0807-02-

    ...

    7DI21-

    ...

    C   7ev_1i_4gb   REV02    4GB      

    ...

    128MB      NA         NA     

    ...

    without encryption             
    TE0807-02-

    ...

    7DI21-

    ...

    A   7ev_

    ...

    1i_4gb   REV02    4GB      128MB      NA         NA     

    ...

    Note: Design contains also Board Part Files for TE0807 only configuration, this boart part files are not used for this reference design.

    Design supports following carriers:

    ...

    anchorTable_HWC
    titleHardware Carrier

    ...

    Additional HW Requirements:

    ...

    anchorTable_AHW
    titleAdditional Hardware

    ...

    Content

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    Notes :

    • content of the zip file

    For general structure and of the reference design, see Project Delivery - Xilinx devices

    Design Sources

    ...

    anchorTable_DS
    titleDesign sources

    ...

    Additional Sources

    ...

    anchorTable_ADS
    titleAdditional design sources

    ...

    Prebuilt

    ...

    hiddentrue
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    Notes :

    ...

    anchorTable_PF
    titlePrebuilt files

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    File

    ...

    File-Extension

    ...

    Description

    ...

    Debian SD-Image

    ...

    *.img

    ...

    Debian Image for SD-Card

    ...

    MCS-File

    ...

    *.mcs

    ...

    Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)

    ...

    MMI-File

    ...

    *.mmi

    ...

    File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)

    ...

    SREC-File

    ...

    *.srec

    ...

    Converted Software Application for MicroBlaze Processor Systems

    ...

    NA                               
    TE0807-02-4AI21-A   4cg_1i_4gb   REV02    4GB      128MB      NA         NA     NA                               
    TE0807-02-5AI21-A   5cg_1i_4gb   REV02    4GB      128MB      NA         NA     NA                               
    TE0807-02-7AI21-A   7cg_1i_4gb   REV02    4GB      128MB      NA         NA     NA                               
    TE0807-02-7DI24-A   7ev_1i_4gb   REV02    4GB      512MB      NA         NA     NA                               
    TE0807-02-7DE21-AK  7ev_1e_4gb   REV02    4GB      128MB      NA         NA     with heat sink                 
    TE0807-02-4AI21-X   4cg_1i_4gb   REV02    4GB      128MB      NA         NA     U41 replaced with diode        
    TE0807-02-4BE21-AK  4eg_1e_4gb   REV02    4GB      128MB      NA         NA     with heat sink                 
    TE0807-02-7DI21-AK   7ev_1i_4gb   REV02    4GB      128MB      NA         NA     with heat sink                 
    TE0807-02-5DI21-A   5ev_1i_4gb   REV02    4GB      128MB      NA         NA     NA                               
    TE0807-02-7NE21-A   7ev_3e_4gb   REV02    4GB      128MB      NA         NA     NA                               
    TE0807-03-5DI21-A   5ev_1i_4gb   REV03    4GB      128MB      NA         NA     NA                               
    TE0807-03-7NE21-A   7ev_3e_4gb   REV03    4GB      128MB      NA         NA     NA                               
    TE0807-03-4AI21-X   4cg_1i_4gb   REV03    4GB      128MB      NA         NA     U41 replaced with diode        
    TE0807-03-4AI21-A   4cg_1i_4gb   REV03    4GB      128MB      NA         NA     NA                               
    TE0807-03-4AI21-C   4cg_1i_4gb   REV03    4GB      128MB      NA         NA     without encryption             
    TE0807-03-4BE21-A   4eg_1e_4gb   REV03    4GB      128MB      NA         NA     NA                               
    TE0807-03-5AI21-A   5cg_1i_4gb   REV03    4GB      128MB      NA         NA     NA                               
    TE0807-03-7AI21-A   7cg_1i_4gb   REV03    4GB      128MB      NA         NA     NA                               
    TE0807-03-7DE21-A   7ev_1e_4gb   REV03    4GB      128MB      NA         NA     NA                               
    TE0807-03-7DE21-AK  7ev_1e_4gb   REV03    4GB      128MB      NA         NA     with heat sink                 
    TE0807-03-7DI21-A   7ev_1i_4gb   REV03    4GB      128MB      NA         NA     NA                               
    TE0807-03-7DI21-C   7ev_1i_4gb   REV03    4GB      128MB      NA         NA     without encryption             
    TE0807-03-7DI24-A   7ev_1i_4gb   REV03    4GB      512MB      NA         NA     NA    


    Note: Design contains also Board Part Files for TE0807 only configuration, this boart part files are not used for this reference design.

    Design supports following carriers:

    Scroll Title
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    titleHardware Carrier

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    File

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    File-Extension

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    Description

    ...

    Download

    ...

    Carrier ModelNotes
    TEBF0808Used as reference carrier. Important: CPLD Firmware REV07 or newer is recommended


    Additional HW Requirements:

    Scroll Title
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    titleAdditional Hardware

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    Additional HardwareNotes
    DP Monitor

    Optional HW
    Not all monitors are supported, also Adapter to other  Standard can make drouble.
    Design was testet with  DELL U2412M

    USB KeyboardOptional HW
    Can be used to get access to console which is show on DP
    USB StickOptional HW
    USB was tested with USB memory stick
    Sata DiskOptional HW
    PCIe CardOptional HW
    ETH cableOptional HW
    Ethernet works with DHCP, but can be setup also manually
    SD cardwith fat32 partiton


    Content

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    ...

    Reference Design is available on:

    Design Flow

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    Notes :
    • Basic Design Steps

    • Add/ Remove project specific description

    Note

    Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first lunch.

    Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.

    See also:

    The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.

    TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/SDK GUI.  For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality

    1. _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
      Image Removed
    2. Press 0 and enter to start "Module Selection Guide"
    3. (optional Win OS) Generate Virtual Drive or use short directory  for the reference design (for example x:\<design name>)
    4. Create Project (follow instruction of the product selection guide), settings file will be configured automatically during this process
      1. (optional for manual changes) Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
        Note: Select correct one, see TE Board Part Files
                  Important: Use Board Part Files, which ends with *_tebf0808
    5. Create XSA and export to prebuilt folder
      1. Run on Vivado TCL: TE::hw_build_design -export_prebuilt
        Note: Script generate design and export files into \prebuilt\hardware\<short dir>. Use GUI is the same, except file export to prebuilt folder
    6. Create Linux (bl31.elf, uboot.elf and image.ub) with exported XSA
      1. HDF is exported to "prebuilt\hardware\<short name>"
        Note: HW Export from Vivado GUI create another path as default workspace.
      2. Create Linux images on VM, see PetaLinux KICKstart
        1. Use TE Template from /os/petalinux
    7. Add Linux files (bl31.elf, uboot.elf and image.ub) to prebuilt folder
      1. prebuilt\os\petalinux\<ddr size>" or "prebuilt\os\petalinux\<short name>"
    8. Generate Programming Files with Vitis
      1. Run on Vivado TCL: TE::sw_run_vitis -all
        Note: Scripts generate applications and bootable files, which are defined in "sw_lib\apps_list.csv"
      2. (alternative) Start SDK with Vivado GUI or start with TE Scripts on Vivado TCL: TE::sw_run_vitis
        Note:  TCL scripts generate also platform project, this must be done manuelly in case GUI is used. See Vitis

    Launch

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    Note:

    • Programming and Startup procedure

    For basic board setup, LEDs... see: TEBF0808 Getting Started

    Programming

    Note

    Check Module and Carrier TRMs for proper HW configuration before you try any design.

    Xilinx documentation for programming and debugging: Vivado/SDK/SDSoC-Xilinx Software Programming and Debugging

    Get prebuilt boot binaries

    1. _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell
    2. Press 0 and enter to start "Module Selection Guide"
      1. Select assembly version
      2. Validate selection
      3. Select Create and open delivery binary folder
        Note: Folder (<project foler>/_binaries_<Artikel Name>) with subfolder (boot_<app name>) for different applications will be generated

    QSPI

    Optional for Boot.bin on QSPI Flash and image.ub on SD.

    1. Connect JTAG and power on carrier with module
    2. Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"
    3. Type on Vivado TCL Console: TE::pr_program_flash_binfile -swapp u-boot
      Note: To program with SDK/Vivado GUI, use special FSBL (zynqmp_fsbl_flash) on setup
               optional "TE::pr_program_flash_binfile -swapp hello_te0803" possible
    4. Copy image.ub on SD-Card
      1. use files from (<project foler>/_binaries_<Articel Name>)/boot_linux from generated binary folder,see: Get prebuilt boot binaries
      2. or use prebuilt file location, see <design_name>/prebuilt/readme_file_location.txt
    5. Set Boot Mode to QSPI-Boot and insered SD.
      1. Depends on Carrier, see carrier TRM.
      2. TEBF0808 change automatically the Boot Mode to SD, if SD is insered, optional CPLD Firmware without Boot Mode changing for mircoSD Slot is available on the download area

    SD

    1. Copy image.ub and Boot.bin on SD-Card.
      • use files from (<project foler>/_binaries_<Articel Name>)/boot_linux from generated binary folder,see: Get prebuilt boot binaries
      • or use prebuilt file location, see <design_name>/prebuilt/readme_file_location.txt
    2. Set Boot Mode to SD-Boot.
      • Depends on Carrier, see carrier TRM.
    3. Insert SD-Card in SD-Slot.

    JTAG

    Not used on this Example.

    Usage

    1. Prepare HW like described on section 70156402
    2. Connect UART USB (JTAG XMOD)
    3. Select SD Card as Boot Mode (or QSPI - depending on step 1)
      Note: See TRM of the Carrier, which is used.
    4. (Optional) Insert PCIe Card (detection depends on Linux driver. Only some basic drivers are installed)
    5. (Optional) Connect Sata Disc
    6. (Optional) Connect DisplayPort Monitor (List of usable Monitors: https://www.xilinx.com/support/answers/68671.html)
    7. (Optional) Connect Network Cable
    8. Power On PCB
      Note: 1. ZynqMP Boot ROM loads PMU Firmware and  FSBL from SD into OCM, 2. FSBL loads ATF(bl31.elf) and U-boot from SD/QSPI into DDR, 3. U-boot load Linux from SD into DDR.

    Linux

    1. Open Serial Console (e.g. putty)
      1. Speed: 115200
      2. COM Port: Win OS, see device manager, Linux OS see  dmesg |grep tty  (UART is *USB1)
    2. Linux Console:
      Note: Wait until Linux boot finished For Linux Login use:
      1. User Name: root
      2. Password: root
    3. You can use Linux shell now.
      1. I2C 0 Bus type: i2cdetect -y -r 0
      2. ETH0 works with udhcpc
      3. USB type  "lsusb" or connect USB device
      4. PCIe type "lspci"
    4. Option Features
      1. Webserver to get access to Zynq
        1. insert IP on web browser to start web interface
      2. init.sh scripts
        1. add init.sh script on SD, content will be load automatically on startup (template included in ./misc/SD)

    Vivado Hardware Manager

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    Note:

    • Add picture of HW Manager

    • add notes for the signal either groups or topics, for example:

      Control:

      • add controllable IOs with short notes..

      Monitoring:

      • add short notes for signals which will be monitored only

      SI5338_CLK0 Counter: 

      Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder).Set radix from VIO signals to unsigned integer.Note: Frequency Counter is inaccurate and displayed unit is Hz

    Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder).

    ...

    anchorFigure_VHM
    titleVivado Hardware Manager

    ...

    Image Removed

    ...

    Image Removed

    System Design - Vivado

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    Note:

    • Description of Block Design, Constrains... BD Pictures from Export...

    Block Design

    Scroll Title
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    titleBlock Design
    Image Removed

    PS Interfaces

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    Note:

    • optional for Zynq / ZynqMP only

    • add basic PS configuration

    Activated interfaces:

    ...

    anchorTable_PSI
    titlePS Interfaces

    ...

    Constrains

    Basic module constrains

    Code Block
    languageruby
    title_i_bitgen.xdc
    set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
    set_property BITSTREAM.CONFIG.UNUSEDPIN PULLNONE [current_design]

    Design specific constrain

    ...

    languageruby
    title_i_io.xdc

    ...

    Notes :

    • content of the zip file

    For general structure and of the reference design, see Project Delivery - Xilinx devices

    Design Sources

    Scroll Title
    anchorTable_DS
    titleDesign sources

    Scroll Table Layout
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    TypeLocationNotes
    Vivado<design name>/block_design
    <design name>/constraints
    <design name>/ip_lib
    Vivado Project will be generated by TE Scripts
    Vitis<design name>/sw_libAdditional Software Template for Vitis and apps_list.csv with settings automatically for Vitis app generation
    PetaLinux<design name>/os/petalinuxPetaLinux template with current configuration


    Additional Sources

    Scroll Title
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    titleAdditional design sources

    Scroll Table Layout
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    TypeLocationNotes
    SI5345<design name>/misc/Si5345SI5345 Project with current PLL Configuration
    init.sh<design name>/sd/Additional Initialization Script for Linux


    Prebuilt

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    • prebuilt files
    • Template Table:

      • Scroll Title
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        titlePrebuilt files

        Scroll Table Layout
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        style
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        File

        File-Extension

        Description

        BIF-File*.bifFile with description to generate Bin-File
        BIN-File*.binFlash Configuration File with Boot-Image (Zynq-FPGAs)
        BIT-File*.bitFPGA (PL Part) Configuration File
        Boot Source*.scr

        Distro Boot file

        DebugProbes-File*.ltxDefinition File for Vivado/Vivado Labtools Debugging Interface

        Debian SD-Image

        *.img

        Debian Image for SD-Card

        Diverse Reports---Report files in different formats
        Hardware-Platform-Specification-Files*.xsaExported Vivado Hardware Specification for Vitis and PetaLinux
        LabTools Project-File*.lprVivado Labtools Project File

        MCS-File

        *.mcs

        Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)

        MMI-File

        *.mmi

        File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)

        OS-Image*.ubImage with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)
        Software-Application-File*.elfSoftware Application for Zynq or MicroBlaze Processor Systems

        SREC-File

        *.srec

        Converted Software Application for MicroBlaze Processor Systems




    Scroll Title
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    titlePrebuilt files (only on ZIP with prebult content)

    Scroll Table Layout
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    File

    File-Extension

    Description

    BIF-File*.bifFile with description to generate Bin-File
    BIN-File*.binFlash Configuration File with Boot-Image (Zynq-FPGAs)
    BIT-File*.bitFPGA (PL Part) Configuration File
    Boot Source*.scr

    Distro Boot file

    DebugProbes-File*.ltxDefinition File for Vivado/Vivado Labtools Debugging Interface
    Diverse Reports---Report files in different formats
    Hardware-Platform-Specification-Files*.xsaExported Vivado Hardware Specification for Vitis and PetaLinux
    LabTools Project-File*.lprVivado Labtools Project File
    OS-Image*.ubImage with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)
    Software-Application-File*.elfSoftware Application for Zynq or MicroBlaze Processor Systems


    Download

    Reference Design is only usable with the specified Vivado/SDK/PetaLinux/SDx version. Do never use different Versions of Xilinx Software for the same Project.

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    Reference Design is available on:

    Design Flow

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    • Basic Design Steps

    • Add/ Remove project specific description


    Note

    Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first lunch.


    Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.

    See also:

    The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.

    TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/SDK GUI.  For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality


    1. _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
      Image Added
    2. Press 0 and enter to start "Module Selection Guide"
    3. (optional Win OS) Generate Virtual Drive or use short directory  for the reference design (for example x:\<design name>)
    4. Create Project (follow instruction of the product selection guide), settings file will be configured automatically during this process
      1. (optional for manual changes) Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
        Note: Select correct one, see TE Board Part Files
                  Important: Use Board Part Files, which ends with *_tebf0808
    5. Create XSA and export to prebuilt folder
      1. Run on Vivado TCL: TE::hw_build_design -export_prebuilt
        Note: Script generate design and export files into \prebuilt\hardware\<short dir>. Use GUI is the same, except file export to prebuilt folder
    6. Create Linux (bl31.elf, uboot.elf, image.ub, boot.src, bl31.elf) with exported XSA
      1. HDF is exported to "prebuilt\hardware\<short name>"
        Note: HW Export from Vivado GUI create another path as default workspace.
      2. Create Linux images on VM, see PetaLinux KICKstart
        1. Use TE Template from /os/petalinux
    7. Add Linux files (bl31.elf, uboot.elf and image.ub) to prebuilt folder
      1. prebuilt\os\petalinux\<ddr size>" or "prebuilt\os\petalinux\<short name>"
    8. Generate Programming Files with Vitis
      1. Run on Vivado TCL: TE::sw_run_vitis -all
        Note: Scripts generate applications and bootable files, which are defined in "sw_lib\apps_list.csv"
      2. (alternative) Start SDK with Vivado GUI or start with TE Scripts on Vivado TCL: TE::sw_run_vitis
        Note:  TCL scripts generate also platform project, this must be done manuelly in case GUI is used. See Vitis

    Launch

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    Note:

    • Programming and Startup procedure

    For basic board setup, LEDs... see: TEBF0808 Getting Started

    Programming

    Note

    Check Module and Carrier TRMs for proper HW configuration before you try any design.

    Xilinx documentation for programming and debugging: Vivado/SDK/SDSoC-Xilinx Software Programming and Debugging

    Get prebuilt boot binaries

    1. _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell
    2. Press 0 and enter to start "Module Selection Guide"
      1. Select assembly version
      2. Validate selection
      3. Select Create and open delivery binary folder
        Note: Folder (<project foler>/_binaries_<Artikel Name>) with subfolder (boot_<app name>) for different applications will be generated

    QSPI

    Optional for Boot.bin on QSPI Flash and image.ub on SD.

    1. Connect JTAG and power on carrier with module
    2. Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"
    3. Type on Vivado TCL Console: TE::pr_program_flash_binfile -swapp u-boot
      Note: To program with SDK/Vivado GUI, use special FSBL (zynqmp_fsbl_flash) on setup
               optional "TE::pr_program_flash_binfile -swapp hello_te0803" possible
    4. Copy image.ub on SD-Card
      1. use files from (<project foler>/_binaries_<Articel Name>)/boot_linux from generated binary folder,see: Get prebuilt boot binaries
      2. or use prebuilt file location, see <design_name>/prebuilt/readme_file_location.txt
    5. Set Boot Mode to QSPI-Boot and insered SD.
      1. Depends on Carrier, see carrier TRM.
      2. TEBF0808 change automatically the Boot Mode to SD, if SD is insered, optional CPLD Firmware without Boot Mode changing for mircoSD Slot is available on the download area

    SD

    1. Copy image.ub and Boot.bin on SD-Card.
      • use files from (<project foler>/_binaries_<Articel Name>)/boot_linux from generated binary folder,see: Get prebuilt boot binaries
      • or use prebuilt file location, see <design_name>/prebuilt/readme_file_location.txt
    2. Set Boot Mode to SD-Boot.
      • Depends on Carrier, see carrier TRM.
    3. Insert SD-Card in SD-Slot.

    JTAG

    Not used on this Example.

    Usage

    1. Prepare HW like described on section 70156402
    2. Connect UART USB (JTAG XMOD)
    3. Select SD Card as Boot Mode (or QSPI - depending on step 1)
      Note: See TRM of the Carrier, which is used.
    4. (Optional) Insert PCIe Card (detection depends on Linux driver. Only some basic drivers are installed)
    5. (Optional) Connect Sata Disc
    6. (Optional) Connect DisplayPort Monitor (List of usable Monitors: https://www.xilinx.com/support/answers/68671.html)
    7. (Optional) Connect Network Cable
    8. Power On PCB
      Note: 1. ZynqMP Boot ROM loads PMU Firmware and  FSBL from SD into OCM, 2. FSBL loads ATF(bl31.elf) and U-boot from SD/QSPI into DDR, 3. U-boot load Linux from SD into DDR.

    Linux

    1. Open Serial Console (e.g. putty)
      1. Speed: 115200
      2. COM Port: Win OS, see device manager, Linux OS see  dmesg |grep tty  (UART is *USB1)
    2. Linux Console:
      Note: Wait until Linux boot finished For Linux Login use:
      1. User Name: root
      2. Password: root
    3. You can use Linux shell now.
      1. I2C 0 Bus type: i2cdetect -y -r 0
      2. ETH0 works with udhcpc
      3. USB type  "lsusb" or connect USB device
      4. PCIe type "lspci"
    4. Option Features
      1. Webserver to get access to Zynq
        1. insert IP on web browser to start web interface
      2. init.sh scripts
        1. add init.sh script on SD, content will be load automatically on startup (template included in ./misc/SD)

    Vivado Hardware Manager

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    Note:

    • Add picture of HW Manager

    • add notes for the signal either groups or topics, for example:

      Control:

      • add controllable IOs with short notes..

      Monitoring:

      • add short notes for signals which will be monitored only

      SI5338_CLK0 Counter: 

      Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder).Set radix from VIO signals to unsigned integer.Note: Frequency Counter is inaccurate and displayed unit is Hz

    Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder).

    • Control:
      • LEDs: XMOD 2(without green dot) and HD LED are accessible.
      • CAN_S
    Scroll Title
    anchorFigure_VHM
    titleVivado Hardware Manager


    Image Added

    Image Added


    System Design - Vivado

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    Note:

    • Description of Block Design, Constrains... BD Pictures from Export...

    Block Design

    Scroll Title
    anchorFigure_BD
    titleBlock Design
    Image Added

    PS Interfaces

    Page properties
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    Note:

    • optional for Zynq / ZynqMP only

    • add basic PS configuration

    Activated interfaces:

    Scroll Title
    anchorTable_PSI
    titlePS Interfaces

    Scroll Table Layout
    orientationportrait
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    style
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    sortEnabledfalse
    cellHighlightingtrue

    TypeNote
    DDR
    QSPIMIO
    SD0MIO
    SD1MIO
    CAN0EMIO
    I2C0MIO
    PJTAG0MIO
    UART0MIO
    GPIO0MIO
    SWDT0..1
    TTC0..3
    GEM3MIO
    USB0MIO/GTP
    PCIeMIO/GTP
    SATAGTP
    DisplayPortEMIO/GTP


    Constrains

    Basic module constrains

    Code Block
    languageruby
    title_i_bitgen.xdc
    set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
    set_property BITSTREAM.CONFIG.UNUSEDPIN PULLNONE [current_design]

    Design specific constrain

    Code Block
    languageruby
    title_i_io.xdc
    #System Controller IP
    
    #J3:31 LED_HD
    set_property PACKAGE_PIN K11 [get_ports BASE_sc0]
    #J3:41
    set_property PACKAGE_PIN E14 [get_ports BASE_sc5]
    #J3:45
    set_property PACKAGE_PIN C12 [get_ports BASE_sc6]
    #J3:47
    set_property PACKAGE_PIN D12 [get_ports BASE_sc7]
    #J3:32
    set_property PACKAGE_PIN J12 [get_ports BASE_sc10_io]
    #J3:34
    set_property PACKAGE_PIN K13 [get_ports BASE_sc11]
    #J3:36
    set_property PACKAGE_PIN A13 [get_ports BASE_sc12]
    #J3:38
    set_property PACKAGE_PIN A14 [get_ports BASE_sc13]
    #J3:40
    set_property PACKAGE_PIN E12 [get_ports BASE_sc14]
    #J3:42
    set_property PACKAGE_PIN F12 [get_ports BASE_sc15]
    #J3:46 CAN S
    set_property PACKAGE_PIN A12 [get_ports BASE_sc16]
    #J3:48 LED_XMOD
    set_property PACKAGE_PIN B12 [get_ports BASE_sc17]
    #J3:50 CAN TX 
    set_property PACKAGE_PIN B14 [get_ports BASE_sc18]
    #J3:52 CAN RX 
    set_property PACKAGE_PIN C14 [get_ports BASE_sc19]
    
    set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc0]
    set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc5]
    set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc6]
    set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc7]
    set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc10_io]
    set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc11]
    set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc12]
    set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc13]
    set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc14]
    set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc15]
    set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc16]
    set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc17]
    set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc18]
    set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc19]
    
    # PLL
    #J4:74
    #set_property PACKAGE_PIN AF15 [get_ports {si570_clk_p[0]}]
    #set_property IOSTANDARD LVDS [get_ports {si570_clk_p[0]}]
    #set_property IOSTANDARD LVDS [get_ports {si570_clk_n[0]}]
    
    
    
    # Audio Codec
    #LRCLK        J3:49 B47_L9_N
    #BCLK        J3:51 B47_L9_P
    #DAC_SDATA    J3:53 B47_L7_N
    #ADC_SDATA    J3:55 B47_L7_P
    set_property PACKAGE_PIN G14 [get_ports LRCLK ]
    set_property PACKAGE_PIN H14 [get_ports BCLK ]
    set_property PACKAGE_PIN C13 [get_ports DAC_SDATA ]
    set_property PACKAGE_PIN D14 [get_ports ADC_SDATA ]
    set_property IOSTANDARD LVCMOS18 [get_ports LRCLK ]
    set_property IOSTANDARD LVCMOS18 [get_ports BCLK ]
    set_property IOSTANDARD LVCMOS18 [get_ports DAC_SDATA ]
    set_property IOSTANDARD LVCMOS18 [get_ports ADC_SDATA ]
    
    

    Software Design - Vitis

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    Note:
    • optional chapter separate

    • sections for different apps

    For SDK project creation, follow instructions from:

    Vitis

    Application

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    ----------------------------------------------------------

    FPGA Example

    scu

    MCS Firmware to configure SI5338 and Reset System.

    srec_spi_bootloader

    TE modified

    ...

    2020.2 SREC

    Bootloader to load app or second bootloader from flash into DDR

    Descriptions:

    • Modified Files: blconfig.h, bootloader.c
    • Changes:
      • Add some console outputs and changed bootloader read address.
      • Add bugfix for 2018.2 qspi flash

    xilisf_v5_11

    TE modified

    ...

    2020.2 xilisf_v5_11

    • Changed default Flash type to 5.

    ----------------------------------------------------------

    Zynq Example:

    zynq_fsbl

    TE modified

    ...

    2020.2 FSBL

    General:

    • Modified Files:main.c, fsbl_hooks.h/.c (search for 'TE Mod' on source code)
    • Add Files: te_fsbl_hooks.h/.c(for hooks and board)\n\

    • General Changes: 
      • Display FSBL Banner and Device ID

    Module Specific:

    • Add Files: all TE Files start with te_*
      • READ MAC from EEPROM and make Address accessible by UBOOT (need copy defines on uboot  platform-top.h)
      • CPLD access
      • Read CPLD Firmware and SoC Type
      • Configure Marvell PHY

    zynq_fsbl_flash

    TE modified

    ...

    2020.2 FSBL

    General:

    • Modified Files: main.c
    • General Changes:
      •  Display FSBL Banner
      • Set FSBL Boot Mode to JTAG
      • Disable Memory initialisation

    ZynqMP Example:

    ----------------------------------------------------------

    zynqmp_fsbl

    TE modified

    ...

    2020.2 FSBL

    General:

    • Modified Files: xfsbl_main.c, xfsbl_hooks.h/.c, xfsbl_board.h/.c(search for 'TE Mod' on source code)
    • Add Files:  te_xfsbl_hooks.h/.c (for hooks and board)\n\
    • General Changes: 
      • Display FSBL Banner and Device Name

    Module Specific:

    • Add Files: all TE Files start with te_*
      • Si5338 Configuration
      • ETH+OTG Reset over MIO

    zynqmp_fsbl_flash

    TE modified

    ...

    2020.2 FSBL

    General:

    • Modified Files: xfsbl_initialisation.c, xfsbl_hw.h, xfsbl_handoff.c, xfsbl_main.c
    • General Changes:
      •  Display FSBL Banner
      • Set FSBL Boot Mode to JTAG
      • Disable Memory initialisation


    zynqmp_pmufw

    Xilinx default PMU firmware.

    ----------------------------------------------------------

    General Example:

    hello_te0820

    Hello TE0820 is a Xilinx Hello World example as endless loop instead of one console output.

    u-boot

    U-Boot.elf is generated with PetaLinux. SDK/HSI is used to generate Boot.bin.

    SDK template in ./sw_lib/sw_apps/ available.

    zynqmp_fsbl

    TE modified

    ...

    2020.2 FSBL

    General:

    • Modified Files: xfsbl_main.c, xfsbl_hooks.h/.c, xfsbl_board.h/.c(search for 'TE Mod' on source code)
    • Add Files:  te_xfsbl_hooks.h/.c (for hooks and board)\n\
    • General Changes: 
      • Display FSBL Banner and Device Name

    Module Specific:

    • Add Files: all TE Files start with te_*
      • Si5345 Configuration
      • OTG+PCIe Reset over MIO
      • I2C MUX for EEPROM MAC

    zynqmp_fsbl_flash

    TE modified

    ...

    2020.2 FSBL

    General:

    • Modified Files: xfsbl_initialisation.c, xfsbl_hw.h, xfsbl_handoff.c, xfsbl_main.c
    • General Changes:
      •  Display FSBL Banner
      • Set FSBL Boot Mode to JTAG
      • Disable Memory initialisation

    zynqmp_pmufw

    Xilinx default PMU firmware.

    hello_te0807

    Hello TE0807 is a Xilinx Hello World example as endless loop instead of one console output.

    u-boot

    U-Boot.elf is generated with PetaLinux. SDK/HSI is used to generate Boot.bin.

    Software Design -  PetaLinux

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    Note:
    • optional chapter separate

    • sections for linux

    • Add "No changes." or "Activate: and add List"

    For PetaLinux installation and  project creation, follow instructions from:

    Config

    Start with petalinux-config or petalinux-config --get-hw-description

    Activate:

    • CONFIG_SUBSYSTEM_PRIMARY_SD_PSU_SD_1_SELECT=y
    • CONFIG_SUBSYSTEM_ETHERNET_PSU_ETHERNET_3_MAC=""

    U-Boot

    Start with petalinux-config -c

    ...

    Changes:

    ...

    CONFIG_ENV_IS_NOWHERE=y

    ...

    u-boot

    Changes:

    • CONFIG_I2C_EEPROM=y
    • CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET=0xFA
    • CONFIG_SYS_I2C_EEPROM_ADDR=0x50
    • CONFIG_SYS_I2C_EEPROM_BUS=2
    • CONFIG_SYS_EEPROM_SIZE=256
    • CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=0
    • CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=0
    • CONFIG_SYS_I2C_EEPROM_ADDR_LEN=1
    • CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW=0
    • CONFIG_SD_BOOT=y

    Change platform-top.h:

    Code Block
    languagejs

    Device Tree

    Code Block
    languagejs
    /include/ "system-conf.dtsi"
    / {
      chosen {
        xlnx,eeprom = &eeprom;
      };
    };
    
    /* notes:
    serdes: // PHY TYP see: dt-bindings/phy/phy.h
    */
    
    /* default *

    ...

    /
    
    &sata {
    phy-names = "sata-phy";
    phys = <&lane2 1  0 1 150000000>;
    };
    
    /* SD */
    &sdhci0 {
    	// disable-wp;
    	no-1-8-v;
    
    };
    
    &sdhci1 {
    	// disable-wp;
    	no-1-8-v;
    
    };
    
    
    /* USB  */
    
    
    &dwc3_0 {
        status = "okay";
        dr_mode = "host";
        snps,usb3_lpm_capable;
        snps,dis_u3_susphy_quirk;
        snps,dis_u2_susphy_quirk;
        phy-names = "usb2-phy","usb3-phy";
        phys = <&lane1 4 0 2 100000000>;
        maximum-speed = "super-speed";
    };
    
    /* ETH PHY */
    
    &gem3 {
    	phy-handle = <&phy0>;
    	phy0: phy0@1 {
    		device_type = "ethernet-phy";
    		reg = <1>;
    	};
    };
    
    /* QSPI */
    
    &qspi {
        #address-cells = <1>;
        #size-cells = <0>;
        status = "okay";
        flash0: flash@0 {
            compatible = "jedec,spi-nor";
            reg = <0x0>;
            #address-cells = <1>;
            #size-cells = <1>;
        };
    };
    
    /* I2C */
    
    &i2c0 {
        i2cswitch@73 { // u
            compatible = "nxp,pca9548";
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <0x73>;
            i2c-mux-idle-disconnect;
            i2c@0 { // MCLK TEBF0808 SI5338A, 570FBB000290DG_unassembled
                #address-cells = <1>;
                #size-cells = <0>;
                reg = <0>;
            };
            i2c@1 { // SFP TEBF0808 PCF8574DWR
                #address-cells = <1>;
                #size-cells = <0>;
                reg = <1>;
            };
            i2c@2 { // PCIe
                #address-cells = <1>;
                #size-cells = <0>;
                reg = <2>;
            };
            i2c@3 { // SFP1 TEBF0808
                #address-cells = <1>;
                #size-cells = <0>;
                reg = <3>;
            };
            i2c@4 {// SFP2 TEBF0808
                #address-cells = <1>;
                #size-cells = <0>;
                reg = <4>;
            };
            i2c@5 { // TEBF0808 EEPROM
                #address-cells = <1>;
                #size-cells = <0>;
                reg = <5>;
                eeprom: eeprom@50 {
    	            compatible = "atmel,24c08";
    	            reg = <0x50>;
    	          };
            };
            i2c@6 { // TEBF0808 FMC  
                #address-cells = <1>;
                #size-cells = <0>;
                reg = <6>;
            };
            i2c@7 { // TEBF0808 USB HUB
                #address-cells = <1>;
                #size-cells = <0>;
                reg = <7>;
            };
        };
        i2cswitch@77 { // u
            compatible = "nxp,pca9548";
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <0x77>;
            i2c-mux-idle-disconnect;
            i2c@0 { // TEBF0808 PMOD P1
                #address-cells = <1>;
                #size-cells = <0>;
                reg = <0>;
            };
            i2c@1 { // i2c Audio Codec
                #address-cells = <1>;
                #size-cells = <0>;
                reg = <1>;
    			/*
                adau1761: adau1761@38 {
                    compatible = "adi,adau1761";
                    reg = <0x38>;
                };
    			*/
            };
            i2c@2 { // TEBF0808 Firefly A
                #address-cells = <1>;
                #size-cells = <0>;
                reg = <2>;
            };
            i2c@3 { // TEBF0808 Firefly B
                #address-cells = <1>;
                #size-cells = <0>;
                reg = <3>;
            };
            i2c@4 { //Module PLL Si5338 or SI5345
                #address-cells = <1>;
                #size-cells = <0>;
                reg = <4>;
            };
            i2c@5 { //TEBF0808 CPLD
                #address-cells = <1>;
                #size-cells = <0>;
                reg = <5>;
            };
            i2c@6 { //TEBF0808 

    ...

    Firefly PCF8574DWR
                #address-cells = <1>;
                #size-cells = <0>;
                reg = <6>;
            };
            i2c@7 { // TEBF0808 PMOD P3
                #address-cells = <1>;
                #size-cells = <0>;
                reg = 

    ...

    <7>;
            };
        

    ...

    Kernel

    Start with petalinux-config -c kernel

    Changes:

    ...

    CONFIG_CPU_IDLE is not set (only needed to fix JTAG Debug issue)

    ...

    CONFIG_CPU_FREQ is not set (only needed to fix JTAG Debug issue)

    ...

    };
    };
    

    FSBL patch

    Must be add manually, see template

    Kernel

    Start with petalinux-config -c kernel

    Changes:

    • # CONFIG_CPU_IDLE is not set
    • # CONFIG_CPU_FREQ is not set
    • CONFIG_EDAC_CORTEX_ARM64=y
    • # CONFIG_CPU_IDLE is not set
    • # CONFIG_CPU_FREQ is not set
    • CONFIG_NVME_CORE=y
    • CONFIG_BLK_DEV_NVME=y
    • # CONFIG_NVME_MULTIPATH is not set
    • # CONFIG_NVME_TCP is not set
    • CONFIG_NVME_TARGET=y
    • # CONFIG_NVME_TARGET_LOOP is not set
    • # CONFIG_NVME_TARGET_FC is not set
    • # CONFIG_NVME_TARGET_TCP is not set
    • CONFIG_NVM=y
    • CONFIG_NVM_PBLK=y
    • CONFIG_NVM_PBLK_DEBUG=y
    • CONFIG_EDAC_CORTEX_ARM64=y
    • CONFIG_SATA_AHCI=y
    • CONFIG_SATA_MOBILE_LPM_POLICY=0

    Rootfs

    Start with petalinux-config -c rootfs

    Changes:

    • CONFIG_i2c-tools=y
    • CONFIG_busybox-httpd=y (for web server app)
    • CONFIG_packagegroup-petalinux-utils(util-linux,cpufrequtils,bridge-utils,mtd-utils,usbutils,pciutils,canutils,i2c-tools,smartmontools,e2fsprogs)

    Applications

    See: \os\petalinux\project-spec\meta-user\recipes-apps\

    startup

    Script App to load init.sh from SD Card if available.

    webfwu

    Webserver application accemble for Zynq access. Need busybox-httpd

    Additional Software

    Page properties
    hiddentrue
    idComments
    Note:
    • Add description for other Software, for example SI CLK Builder ...
    • SI5338 and SI5345 also Link to:

    SI5345

    File location <design name>/misc/Si5345/Si5345-*.slabtimeproj

    General documentation how you work with these project will be available on Si5345

    Appx. A: Change History and Legal Notices

    Document Change History

    To get content of older revision  got to "Change History"  of this page and select older document revision number.

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    • It's semi automatically, so do following
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      • Metadata is only used of compatibility of older exports


    Scroll Title
    anchorTable_dch
    titleDocument change history.

    Scroll Table Layout
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    sortDirectionASC
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    DateDocument Revision

    Authors

    Description

    Page info

    ...

    infoTypeModified date
    dateFormatyyyy-MM-dd
    typeFlat

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    ...

    Current version
    prefixv.
    typeFlat

    Page info
    infoTypeModified by
    typeFlat

    • 2020.2 release
    • document style update
    2020-10-06v.21John Hartfiel
    • new assembly variants
    2020-03-25v.20John Hartfiel
    • script update
    2020-02-25v.19John Hartfiel
    • Update requiroment section
    2020-02-19v.18John Hartfiel
    • Design update
    2020-01-27v.17John Hartfiel
    • new assembly variants
    • Release 2019.2

    ...

    2019-05-22v.16John Hartfiel
    • Release 2018.3

    2019-09-04

    v.13John Hartfiel
    • Release 2018.2

    2018-07-20

    v.12John Hartfiel
    • Design update

    2018-04-30

    v.10John Hartfiel
    • Update known issues

    2018-02-08

    v.9John Hartfiel
    • Design update
    2018-01-29v.4John Hartfiel
    • Update known issues
    2018-01-18v.3John Hartfiel
    • Release 2017.4

    All

    Page info
    infoType

    ...

    Modified users
    type

    ...

    Flat



    Legal Notices

    Include Page
    IN:Legal Notices
    IN:Legal Notices



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    .wiki-content .columnLayout .cell.aside {
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