Page History
Template Revision 2.7 - on construction
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Important General Note:
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Export PDF to download, if vivado revision is changed!
Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro
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Figure template (note: inner scroll ignore/only only with drawIO object):
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Create DrawIO object here: Attention if you copy from other page, use |
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image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed |
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Table template:
- Layout macro can be use for landscape of large tables
- Set column width manually(can be used for small tables to fit over whole page) or leave empty (automatically)
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Table of contents
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Overview
Linux with basic periphery of TE0808 Starterkit (TEBF0808 Carrier).
Refer to http://trenz.org/te0803-info for the current online version of this manual and other available documentation.
Key Features
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Revision History
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Notes :
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Notes :
short description of the design
Short Link of "Scroll only" macro:
Use short link the Wiki Resource page, for example: http://trenz.org/te0720-info
List of available short links: https://wiki.trenz-electronic.de/display/CON/Redirects
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- 2019.2 update
- Vitis support
- FSBL SI programming procedure update
- petalinux device tree and u-boot update
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- new assembly variant
- TE Script update
- rework of the FSBLs
- SI5338 CLKBuilder Pro Project
- some additional Linux features
- MAC from EEPROM
- new assembly variants
- remove special compiler flags, which was needed in 2018.2
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- new assembly variant
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- new assembly variant
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- correction on FSBL
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TE0803-Starterkit_noprebuilt-vivado_2018.2-build_02_20180713085800.zip
TE0803-Starterkit-vivado_2018.2-build_02_20180713085740.zip
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- small petalinux changes
- IO renaming
- PL Design changes
- additional notes for FSBL generated with Win SDK
- changed *.bif
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- new assembly variant
- solved Linux flash issue
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- bugfix TE0803-01-04EG board part file
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- new assembly variant
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- same CLK for both VIO
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- initial release
Release Notes and Know Issues
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Do not use HW Manager connection, or if debugging is nessecary:
- Boot linux with usb terminal
- From the terminal: root root mount ifconfig eth0
- Open two new SSH terminals via ethernet: root root , run user application ...
- Exit and close the usb terminal
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Requirements
Software
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Hardware
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Basic description of TE Board Part Files is available on TE Board Part Files.
Complete List is available on <design name>/board_files/*_board_files.csv
Design supports following modules:
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Note: Design contains also Board Part Files for TE0808 only configuration, this boart part files are not used for this reference design.
Design supports following carriers:
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| title | Hardware Carrier |
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Additional HW Requirements:
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Optional HW
Not all monitors are supported, also Adapter to other Standard can make drouble.
Design was testet with DELL U2412M
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Content
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For general structure and of the reference design, see Project Delivery - Xilinx devices
Design Sources
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Additional Sources
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Prebuilt
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File
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File-Extension
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Description
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Debian SD-Image
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*.img
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Debian Image for SD-Card
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MCS-File
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*.mcs
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Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)
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MMI-File
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*.mmi
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File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)
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SREC-File
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*.srec
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Converted Software Application for MicroBlaze Processor Systems
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File
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Description
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Download
Reference Design is only usable with the specified Vivado/SDK/PetaLinux/SDx version. Do never use different Versions of Xilinx Software for the same Project.
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Reference Design is available on:
Design Flow
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Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first lunch. |
Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.
See also:
The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.
TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/SDK GUI. For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality
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- Use TE Template from /os/petalinux
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- Depends on Carrier, see carrier TRM.
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JTAG
Not used on this Example.
Usage
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- I2C 0 Bus type: i2cdetect -y -r 0
- ETH0 works with udhcpc
- USB type "lsusb" or connect USB device
- PCIe type "lspci"
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System Design - Vivado
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Block Design
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PS Interfaces
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Activated interfaces:
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Constrains
Basic module constrains
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set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLNONE [current_design] |
Design specific constrain
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# system controller ip
#LED_HD SC0 J3:31
#LED_XMOD SC17 J3:48
#CAN RX SC19 J3:52 B26_L11_P
#CAN TX SC18 J3:50 B26_L11_N
#CAN S SC16 J3:46 B26_L1_N
set_property PACKAGE_PIN G14 [get_ports BASE_sc0]
set_property PACKAGE_PIN D15 [get_ports BASE_sc5]
set_property PACKAGE_PIN H13 [get_ports BASE_sc6]
set_property PACKAGE_PIN H14 [get_ports BASE_sc7]
set_property PACKAGE_PIN A13 [get_ports BASE_sc10_io]
set_property PACKAGE_PIN B13 [get_ports BASE_sc11]
set_property PACKAGE_PIN A14 [get_ports BASE_sc12]
set_property PACKAGE_PIN B14 [get_ports BASE_sc13]
set_property PACKAGE_PIN F13 [get_ports BASE_sc14]
set_property PACKAGE_PIN G13 [get_ports BASE_sc15]
set_property PACKAGE_PIN A15 [get_ports BASE_sc16]
set_property PACKAGE_PIN B15 [get_ports BASE_sc17]
set_property PACKAGE_PIN J14 [get_ports BASE_sc18]
set_property PACKAGE_PIN K14 [get_ports BASE_sc19 ]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc0]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc5]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc6]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc7]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc10_io]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc11]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc12]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc13]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc14]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc15]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc16]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc17]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc18]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc19]
# Audio Codec
#LRCLK |
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CONFIG_ENV_IS_NOWHERE=y
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Changes:
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CONFIG_CPU_IDLE is not set (only needed to fix JTAG Debug issue)
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Overview
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