Versions Compared

Key

  • This line was added.
  • This line was removed.
  • Formatting was changed.
HTML
<!--
Template Revision 1.3
Basic Notes
 - export PDF to download, if vivado revision is changed!
 - Template is for different design and SDSoC and examples, remove unused or wrong description!
 -->
Scroll Only (inline)
Online version of this manual and other related documents can be found at https://wiki.trenz-electronic.de/display/PD/Trenz+Electronic+Documentation
Scroll pdf ignore

Table of contents

Table of Contents
outlinetrue

Overview

HTML
<!--
General Design description
 -->

Key Features

HTML
<!--
Add Basic Key Features of the design (should be tested)
 -->
Excerpt
  • PetaLinux
  • SD
  • ETH
  • USB
  • I2C
  • RTC
  • Special FSBL for QSPI programming

Revision History

HTML
<!--
- Add changes from design
- Export PDF to download, if vivado revision is changed!
  -->

...

Release Notes and Know Issues

HTML
<!--
- add known Design issues and general Notes for the current revision
 -->

...

Requirements

Software

HTML
<!--
Add needed external Software
   -->

...

Hardware

HTML
<!--
Hardware Support
   -->

Basic description of TE Board Part Files is available on TE Board Part Files.

Complete List is available on <design name>/board_files/*_board_files.csv

Design supports following modules:

...

Design supports following carriers:

...

Additional HW Requirements:

...

Content

HTML
<!--
Remove unused content
  -->

For general structure and of the reference design, see Project Delivery

Design Sources

...

Additional Sources

...

Prebuilt

HTML
<!-- 

<table width="100%">
<tr> <th>File                                 </th> <th>File-Extension</th>  <th>Description                                                                              </th> </tr>
<tr> <td>BIF-File                             </td> <td>*.bif         </td>  <td>File with description to generate Bin-File                                               </td> </tr>
<tr> <td>BIN-File                             </td> <td>*.bin         </td>  <td>Flash Configuration File with Boot-Image (Zynq-FPGAs)                                    </td> </tr>
<tr> <td>BIT-File                             </td> <td>*.bit         </td>  <td>FPGA Configuration File                                                                  </td> </tr>
<tr> <td>DebugProbes-File                     </td> <td>*.ltx         </td>  <td>Definition File for Vivado/Vivado Labtools Debugging Interface                           </td> </tr>
<tr> <td>Debian SD-Image                      </td> <td>*.img         </td>  <td>Debian Image for SD-Card                                                                </td> </tr>
<tr> <td>Diverse Reports                      </td> <td>  ---         </td>  <td>Report files in different formats                                                        </td> </tr>
<tr> <td>Hardware-Platform-Specification-Files</td> <td>*.hdf         </td>  <td>Exported Vivado Hardware Specification for SDK/HSI                                       </td> </tr>
<tr> <td>LabTools Project-File                </td> <td>*.lpr         </td>  <td>Vivado Labtools Project File                                                             </td> </tr>
<tr> <td>MCS-File                             </td> <td>*.mcs         </td>  <td>Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)                  </td> </tr>
<tr> <td>MMI-File                             </td> <td>*.mmi         </td>  <td>File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only) </td> </tr>
<tr> <td>OS-Image                             </td> <td>*.ub          </td>  <td>Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)             </td> </tr>
<tr> <td>Software-Application-File            </td> <td>*.elf         </td>  <td>Software Application for Zynq or MicroBlaze Processor Systems                            </td> </tr>
<tr> <td>SREC-File                            </td> <td>*.srec        </td>  <td>Converted Software Application for MicroBlaze Processor Systems                          </td> </tr>    
</table>
-->

...

File

...

File-Extension

...

Description

...

Download

Reference Design is only usable with the specified Vivado/SDK/PetaLinux/SDx version. Do never use different Versions of Xilinx Software for the same Project.

HTML
<!--
Add correct path:https://shop.trenz-electronic.de/en/Download/?path=Trenz_Electronic/TE0803/Reference_Design/2017.1/Starterkit
  -->

Reference Design is available on:

Design Flow

HTML
<!--
Basic Design Steps
Add/ Remove project specific 
  -->
Note

Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first lunch.

Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.

See also:

The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.

TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/SDK GUI.  For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality

 

  1. _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
    Image Removed
  2. Press 0 and enter for minimum setup
  3. (optional Win OS) Generate Virtual Drive or use short directory  for the reference design (for example x:\<design name>)
  4. Create Project
    1. Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
      Note: Select correct one, see TE Board Part Files
  5. Create HDF and export to prebuilt folder
    1. Run on Vivado TCL: TE::hw_build_design -export_prebuilt
      Note: Script generate design and export files into \prebuilt\hardware\<short dir>. Use GUI is the same, except file export to prebuilt folder
  6. Create Linux (uboot.elf and image.ub) with exported HDF
    1. HDF is exported to "prebuilt\hardware\<short name>"
      Note: HW Export from Vivado GUI create another path as default workspace.
    2. Create Linux images on VM, see PetaLinux KICKstart
      1. Use TE Template from /os/petalinux
        Note: run init_config.sh before you start petalinux config. This will set correct temporary path variable.
  7. Add Linux files (uboot.elf and image.ub) to prebuilt folder
    1. "prebuilt\os\petalinux\default" or "prebuilt\os\petalinux\<short name>"
      Notes: Scripts select "prebuilt\os\petalinux\<short name>", if exist, otherwise "prebuilt\os\petalinux\default"
  8. Generate Programming Files with HSI/SDK
    1. Run on Vivado TCL: TE::sw_run_hsi
      Note: Scripts generate applications and bootable files, which are defined in "sw_lib\apps_list.csv"
    2. (alternative) Start SDK with Vivado GUI or start with TE Scripts on Vivado TCL: TE::sw_run_sdk
      Note: See SDK Projects
Note

Since Vivado 2017.4 FSBL is needed to program QSPI. (2017.2 works without FSBL). Xilinx mini-uboot starts with this FSBL configuration but needs QSPI FB CLK enabled on PS. On TE0726, this MIO is used for UART, so special design is need to generate this FSBL.

This reference design contains a prebuilt FSBL for QSPI programming (zynqmp_fsbl_flash), so there is normally no need to regenerate this special FSBL. In case of generate this by yourself following steps are needed

  1. Create new default reference design
    1. Open PS and enable QSPI FB CLK
    2. Set UART to MIO 52 .. 53
    3. Create Bitfile
    4. Start SDK with with TE Scripts on Vivado TCL: TE::sw_run_sdk
  2. ON SDK use zynqmp_fsbl_flash template.
    Important "zynqmp_fsbl_flash" FSBL can be only used on QSPI Flash Programming setup on Vivado or SDK Menu!

Launch

Programming

HTML
<!--
Description of Block Design, Constrains...
BD Pictures from Export...
  -->
Note

Check Module and Carrier TRMs for proper HW configuration before you try any design.

Xilinx documentation for programming and debugging: Vivado/SDK/SDSoC-Xilinx Software Programming and Debugging

QSPI

  1. Connect JTAG and power on carrier with module
  2. Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"
  3. Type on Vivado TCL Console: TE::pr_program_flash_binfile -swapp u-boot
    Note: To program with SDK/Vivado GUI, use special FSBL (zynqmp_fsbl_flash) on setup
  4. Copy image.ub on SD-Card
    • For correct prebuilt file location, see <design_name>/prebuilt/readme_file_location.txt
  5. Insert SD-Card

SD

Xilinx Zynq devices in CLG225 package do not support SD Card boot directly from ROM bootloader. Use QSPI for primary boot and SD for secondary boot (uboot)

JTAG

Not used on this Example.

Usage

  1. Prepare HW like described on section Programming
  2. Connect UART USB (most cases same as JTAG)
  3. Insert SD Card with image.ub
  4. Power On PCB
    Note: 1. Zynq Boot ROM loads FSBL from QSPI into OCM, 2. FSBL loads U-boot from QSPI into DDR, 3. U-boot load Linux from SD into DDR

Linux

  1. Open Serial Console (e.g. putty)
    1. Speed: 115200
    2. COM Port: Win OS, see device manager, Linux OS see  dmesg |grep tty  (UART is *USB1)
  2. Linux Console:
    Note: Wait until Linux boot finished For Linux Login use:
    1. User Name: root
    2. Password: root
  3. You can use Linux shell now.
    1. I2C 1 Bus type: i2cdetect -y -r 1
    2. RTC check: dmesg | grep rtc
    3. ETH0 works with udhcpc
    4. USB: insert USB device

System Design - Vivado

HTML
<!--
Description of Block Design, Constrains...
BD Pictures from Export...
  -->

Block Design

Image Removed

PS Interfaces

...

Constrains

Basic module constrains

Code Block
languageruby
title_i_bitgen_common.xdc
#
# Common BITGEN related settings for TE0726
#
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property CFGBVS VCCO [current_design]

set_property BITSTREAM.CONFIG.UNUSEDPIN PULLUP [current_design]

Design specific constrain

Software Design - SDK/HSI

HTML
<!--
optional chapter
separate sections for different apps
  -->

For SDK project creation, follow instructions from:

SDK Projects

Application

zynqmp_fsbl

Xilinx default FSBL

zynqmp_fsbl_flash

TE modified 2017.4 FSBL

Changes:

  • Set FSBL Boot Mode to JTAG
  • Disable Memory initialisation

U-Boot

U-Boot.elf is generated with PetaLinux. SDK/HSI is used to generate Boot.bin.

Hello TE0726

Hello World App in endless loop.

Software Design -  PetaLinux

HTML
<!--
optional chapter
Add "No changes." or "Activate: and add List"
   -->

For PetaLinux installation and  project creation, follow instructions from:

Config

No changes.

U-Boot

No changes.

Device Tree

Code Block
languagejs
/include/ "system-conf.dtsi"
/ {
};


/* USB PHY */

/{
    usb_phy0: usb_phy@0 {
        compatible = "ulpi-phy";
        #phy-cells = <0>;
        reg = <0xe0002000 0x1000>;
        view-port = <0x0170>;
        drv-vbus;
    };
};

&usb0 {
    dr_mode = "host";
    //dr_mode = "peripheral";
    usb-phy = <&usb_phy0>;
};

/* I2C1 */

&i2c1 {
    #address-cells = <1>;
    #size-cells = <0>;

    i2cmux0: i2cmux@70  {
        compatible = "nxp,pca9544";
        #address-cells = <1>;
        #size-cells = <0>;
        reg = <0x70>;


        i2c1@0 {
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <0>;

            id_eeprom@50 {
                compatible = "atmel,24c32";
                reg = <0x50>;
            };

        };
        i2c1@1 {    // Display Interface Connector
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <1>;
        };
        i2c1@2 {    // HDMI Interface Connector
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <2>;
        };
        i2c1@3 {    // Camera Interface Connector
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <3>;
        };
    };

};

Kernel

Activate:

  • CONFIG_XILINX_GMII2RGMII
  • CONFIG_USB_USBNET
  • CONFIG_USB_NET_SMSC95XX
  • CONFIG_USBIP_CORE

Rootfs

Activate:

  • i2c-tools

Applications

startup

Script App to load init.sh from SD Card if available.

See: \os\petalinux\project-spec\meta-user\recipes-apps\startup\files

Additional Software

HTML
<!--
Add Description for other Software, for example SI CLK Builder ...
 -->

No additional software is needed

Appx. A: Change History and Legal Notices

Document Change History

To get content of older revision  got to "Change History"  of this page and select older document revision number.

HTML
<!--
Generate new entry:
1:add new row below first
2:Copy Page Information Macro(date+user) Preview, Page Information Macro Preview
3.Update Metadate =Page Information Macro Preview+1
  -->

...

Legal Notices

...


Page properties
hiddentrue
idComments

Design Name is always "TE Series Name" + Design name, for example "TE0720 Test Board"


DateVersionChangesAuthor
2021-06-283.1.8
  • added boot process for Microblaze
  • minor typos, formatting
ma
2021-06-013.1.7
  • carrier reference note
jh
2021-05-043.1.6
  • removed zynq_ from zynq_fsbl
ma
2021-04-283.1.5
  • added macro "Scroll ignore" for suppression of horizontal dividing lines during .pdf-export
  • minor typos, formatting
ma
2021-04-273.1.4
  • Version History
    • changed from list to table
  • Design flow
    • removed step 5 from Design flow
    • changed link from TE Board Part Files to Vivado Board Part Flow
    • changed cmd shell from picture to codeblock
    • added hidden template for "Copy PetaLinux build image files", depending from hardware
    • added hidden template for "Power on PCB", depending from hardware
  • Usage update of boot process
  • Requirements - Hardware
    • added "*used as reference" for hardware requirements
  • all
    • placed a horizontal separation line under each chapter heading
    • changed title-alignment for tables from left to center
  • all tables
    • added "<project folder>\board_files" in Vivado design sources
ma

3.1.3
  • Design Flow
    • formatting
  • Launch
    • formatting
ma

3.1.2
  • minor typing corrections
  • replaced SDK by Vitis
  • changed from / to \ for windows paths
  • replaced <design name> by <project folder>
  • added "" for path names
  • added boot.src description
  • added USB for programming
ma

3.1.1
  • swapped order from prebuilt files
  • minor typing corrections
  • removed Win OS path length from Design flow, added as caution in Design flow
ma

3.1
  • Fix problem with pdf export and side scroll bar
  • update 19.2 to 20.2
  • add prebuilt content option


3.0
  • add fix table of content
  • add table size as macro
  • removed page initial creator


Custom_table_size_100


Page properties
hiddentrue
idComments

Important General Note:

  • Export PDF to download, if vivado revision is changed!

  • Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro

    • Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)
      • Figure template (note: inner scroll ignore/only only with drawIO object):

        Scroll Title
        anchorFigure_xyz
        titleText


        Scroll Ignore

        Create DrawIO object here: Attention if you copy from other page, use


        Scroll Only

        image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed



      • Table template:

        • Layout macro can be use for landscape of large tables
        • Set column width manually (can be used for small tables to fit over whole page) or leave empty (automatically)

      • Scroll Title
        anchorTable_xyz
        titleText

        Scroll Table Layout
        orientationportrait
        sortDirectionASC
        repeatTableHeadersdefault
        style
        widths
        sortByColumn1
        sortEnabledfalse
        cellHighlightingtrue

        ExampleComment
        12



  • ...



Overview

Scroll Ignore
scroll-pdftrue
scroll-officetrue
scroll-chmtrue
scroll-docbooktrue
scroll-eclipsehelptrue
scroll-epubtrue
scroll-htmltrue


Page properties
hiddentrue
idComments

Notes :

Zynq PS Design with Linux Example.
Refer to http://trenz.org/te0726-info for the current online version of this manual and other available documentation.

Key Features

Page properties
hiddentrue
idComments

Notes :

  • Add basic key futures, which can be tested with the design


Excerpt
  • Vitis/Vivado 2020.2
  • PetaLinux
  • SD
  • ETH
  • USB
  • I2C
  • Special FSBL for QSPI programming

Revision History

Page properties
hiddentrue
idComments

Notes :

  • add every update file on the download
  • add design changes on description


Scroll Title
anchorTable_DRH
title-alignmentcenter
titleDesign Revision History

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
style
widths
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

DateVivadoProject BuiltAuthorsDescription
2021-11-042020.2TE0726-test_board_noprebuilt-vivado_2020.2-build_8_20211104085813.zip
TE0726-test_board-vivado_2020.2-build_8_20211104085759.zip
Mohsen Chamanbaz
  • 0001-QSPI-s25fl127_8-2020_2.patch for restart
  • Added Ethernet interface
2021-08-302020.2

TE0726-test_board_noprebuilt-vivado_2020.2-build_7_20210830095228.zip
TE0726-test_board-vivado_2020.2-build_7_20210830095218.zip

Mohsen Chamanbaz
  • 2020.2 release
  • Without Etherner interface
2020-04-082019.2TE0726-test_board_noprebuilt-vivado_2019.2-build_10_20200408185842.zip
TE0726-test_board-vivado_2019.2-build_10_20200408185804.zip
Mohsen Chamanbaz/John Hartfiel
  • changes FSBL flash
2020-03-252019.2TE0726-test_board_noprebuilt-vivado_2019.2-build_8_20200325080535.zip
TE0726-test_board-vivado_2019.2-build_8_20200325080528.zip
Mohsen Chamanbaz/John Hartfiel
  • script update
2020-02-142019.2TE0726-test_board_noprebuilt-vivado_2019.2-build_5_20200214091531.zip
TE0726-test_board-vivado_2019.2-build_5_20200214091442.zip
Mohsen Chamanbaz
  • Update to 19.2
  • Vitis support
  • prebuilt binary export on selection guide
2019-12-122018.3te0726-test_board_noprebuilt-vivado_2018.3-build_10_20191211160322.zip
te0726-test_board-vivado_2018.3-build_10_20191211160314.zip
Mohsen Chamanbaz
  • FSBL update to18.3
  • additional linux apps
2018-07-132018.2te0726-test_board_noprebuilt-vivado_2018.2-build_02_20180713155548.zip
te0726-test_board-vivado_2018.2-build_02_20180713155535.zip
John Hartfiel
  • Changed SDK Notes on FSBL template fro Flash programming
2018-07-112018.2te0726-test_board_noprebuilt-vivado_2018.2-build_02_20180711113737.zip
te0726-test_board-vivado_2018.2-build_02_20180711113722.zip
John Hartfiel
  • change note for REV01
  • no design changes
2018-02-172017.4te0726-test_board-vivado_2017.4-build_08_20180517084735.zip
te0726-test_board_noprebuilt-vivado_2017.4-build_08_20180517084604.zip
John Hartfiel
  • correction netboot offset for 128MB variant
2018-02-162017.4te0726-test_board-vivado_2017.4-build_06_20180216205357.zip
te0726-test_board_noprebuilt-vivado_2017.4-build_06_20180216205410.zip
John Hartfiel
  • correction PS REFCLK for 01 variant
2018-01-312017.4te0726-test_board-vivado_2017.4-build_05_20180131115412.zip
te0726-test_board_noprebuilt-vivado_2017.4-build_05_20180131115451.zip
John Hartfiel
  • initial release 2017.4


Release Notes and Know Issues

Page properties
hiddentrue
idComments
Notes :
  • add known Design issues and general notes for the current revision
  • do not delete known issue, add fixed version time stamp if  issue fixed


Scroll Title
anchorTable_KI
title-alignmentcenter
titleKnown Issues

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
style
widths
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

IssuesDescriptionWorkaroundTo be fixed version
Flash Programming failed with 19.2Depending on Flash content Flash programming failed with provided fsbl_flash (Xilinx AR# 70548 )2019.2 version
  • Option1:
    • In case Flash is empty, use fsbl_flash on programming GUI 
    • In case Flash is programmed use normal fsbl on programming GUI
  • Option2: use in both case fsbl_flash on programming GUI and Vivado LabTools 2018.3
---
FSBL/ Kernel
Vivado 2020.2
Petalinux does not restart after first bootinguse 0001-QSPI-s25fl127_8-2020_2.patch from
test_board\os\petalinux\project-spec\meta-user\recipes-kernel\linux\linux-xlnx\
---


Requirements

Software

Page properties
hiddentrue
idComments

Notes :

  • list of software which was used to generate the design


Scroll Title
anchorTable_SW
title-alignmentcenter
titleSoftware

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
style
widths
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

SoftwareVersionNote
Vitis2020.2needed, Vivado is included into Vitis installation
PetaLinux2020.2needed


Hardware

Page properties
hiddentrue
idComments

Notes :

  • list of software which was used to generate the design
  • mark the module and carrier board, which was used tested with an *

Basic description of TE Board Part Files is available on TE Board Part Files.

Complete List is available on <design name>/board_files/*_board_files.csv

Design supports following modules:

Scroll Title
anchorTable_HWM
title-alignmentcenter
titleHardware Modules

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
style
widths
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

Module ModelBoard Part Short NamePCB Revision SupportDDRQSPI FlashEMMCOthersNotes
te0726-0101_64MBREV0164MB16MBNANA

NA 

te0726-03rr_128MBREV03,REV02128MB16MBNANALPDDR3, without ETH,USB,Camera,HDMI
te0726-03mm_512MBREV03,REV02512MB16MBNANALPDDR3    
te0726-03-07s-1c7s_512MBREV03,REV02512MB16MBNANALPDDR3    
TE0726-03RJr_128MBREV03,REV02128MB16MBNANALPDDR3, without ETH,USB,Camera,HDMI
TE0726-03-41C74-Qr_128MBREV03,REV02128MB16MBNANALPDDR3,Customised
TE0726-03-41C74-Rr_128MBREV03,REV02128MB16MBNANALPDDR3, without ETH,USB,Camera,HDMI
TE0726-03IMmi_512MBREV03,REV02512MB16MBNANALPDDR3      
TE0726-03-11C64-A7s_512MBREV03,REV02512MB16MBNANALPDDR3      
TE0726-03-41I64-Ami_512MBREV03,REV02512MB16MBNANALPDDR3      
TE0726-03-41C64-A m_512MBREV03,REV02512MB16MBNANALPDDR3   


Design supports following carriers:

Scroll Title
anchorTable_HWC
title-alignmentcenter
titleHardware Carrier

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
style
widths
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

Carrier ModelNotes
---


Additional HW Requirements:

Scroll Title
anchorTable_AHW
title-alignmentcenter
titleAdditional Hardware

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
style
widths
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

Additional HardwareNotes
USB CableConnect to USB2 or better USB3 Hub for proper power over USB


Content

Page properties
hiddentrue
idComments

Notes :

  • content of the zip file

For general structure and of the reference design, see Project Delivery - Xilinx devices

Design Sources

Scroll Title
anchorTable_DS
title-alignmentcenter
titleDesign sources

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
style
widths
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

TypeLocationNotes
Vivado<design name>/block_design
<design name>/constraints
<design name>/ip_lib
Vivado Project will be generated by TE Scripts
Vitis<design name>/sw_libAdditional Software Template for Vitis and apps_list.csv with settings automatically for Vitis app generation
PetaLinux<design name>/os/petalinuxPetaLinux template with current configuration


Additional Sources

Scroll Title
anchorTable_ADS
title-alignmentcenter
titleAdditional design sources

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
style
widths
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

TypeLocationNotes
init.sh<design name>/misc/sd/Additional Initialization Script for Linux


Prebuilt

Page properties
hiddentrue
idComments

Notes :

  • prebuilt files
  • Template Table:

    • Scroll Title
      anchorTable_PF
      title-alignmentcenter
      titlePrebuilt files

      Scroll Table Layout
      orientationportrait
      sortDirectionASC
      repeatTableHeadersdefault
      style
      widths
      sortByColumn1
      sortEnabledfalse
      cellHighlightingtrue

      File

      File-Extension

      Description

      BIF-File*.bifFile with description to generate Bin-File
      BIN-File*.binFlash Configuration File with Boot-Image (Zynq-FPGAs)
      BIT-File*.bitFPGA (PL Part) Configuration File
      Boot Source*.scr

      Distro Boot file

      DebugProbes-File*.ltxDefinition File for Vivado/Vivado Labtools Debugging Interface

      Debian SD-Image

      *.img

      Debian Image for SD-Card

      Diverse Reports---Report files in different formats
      Hardware-Platform-Description-File*.xsaExported Vivado hardware description file for Vitis and PetaLinux
      LabTools Project-File*.lprVivado Labtools Project File

      MCS-File

      *.mcs

      Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)

      MMI-File

      *.mmi

      File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)

      OS-Image*.ubImage with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)
      Software-Application-File*.elfSoftware Application for Zynq or MicroBlaze Processor Systems

      SREC-File

      *.srec

      Converted Software Application for MicroBlaze Processor Systems





Scroll Title
anchorTable_PF
title-alignmentcenter
titlePrebuilt files (only on ZIP with prebult content)

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
style
widths
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

File

File-Extension

Description

BIF-File*.bifFile with description to generate Bin-File
BIN-File*.binFlash Configuration File with Boot-Image (Zynq-FPGAs)
BIT-File*.bitFPGA (PL Part) Configuration File
Diverse Reports---Report files in different formats
Hardware-Platform-Specification-Files*.xsaExported Vivado Hardware Specification for Vitis and PetaLinux
LabTools Project-File*.lprVivado Labtools Project File
OS-Image*.ubImage with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)
Software-Application-File*.elfSoftware Application for Zynq or MicroBlaze Processor Systems


Download

Reference Design is only usable with the specified Vivado/SDK/PetaLinux/SDx version. Do never use different Versions of Xilinx Software for the same Project.

Page properties
hiddentrue
idComments

Reference Design is available on:

Design Flow

Scroll Ignore
scroll-pdftrue
scroll-officetrue
scroll-chmtrue
scroll-docbooktrue
scroll-eclipsehelptrue
scroll-epubtrue
scroll-htmltrue


Page properties
hiddentrue
idComments
Notes :
  • Basic Design Steps

  • Add/ Remove project specific description


Note

Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first lunch.

Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.

See also:

The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.

TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/SDK GUI.  For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality


  1. Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:

    Code Block
    languagebash
    themeMidnight
    title_create_win_setup.cmd/_create_linux_setup.sh
    ------------------------Set design paths----------------------------
    -- Run Design with: _create_win_setup
    -- Use Design Path: <absolute project path>
    --------------------------------------------------------------------
    -------------------------TE Reference Design---------------------------
    --------------------------------------------------------------------
    -- (0)  Module selection guide, project creation...prebuilt export...
    -- (1)  Create minimum setup of CMD-Files and exit Batch
    -- (2)  Create maximum setup of CMD-Files and exit Batch
    -- (3)  (internal only) Dev
    -- (4)  (internal only) Prod
    -- (c)  Go to CMD-File Generation (Manual setup)
    -- (d)  Go to Documentation (Web Documentation)
    -- (g)  Install Board Files from Xilinx Board Store (beta)
    -- (a)  Start design with unsupported Vivado Version (beta)
    -- (x)  Exit Batch (nothing is done!)
    ----
    Select (ex.:'0' for module selection guide):


  2. Press 0 and enter to start "Module Selection Guide"
  3. (optional Win OS) Generate Virtual Drive or use short directory  for the reference design (for example x:\<design name>)
  4. Create Project (follow instruction of the product selection guide), settings file will be configured automatically during this process
    • (optional for manual changes) Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"

      Note

      Note: Select correct one, see also Vivado Board Part Flow


  5. Create hardware description file (.xsa file) for PetaLinux project and export to prebuilt folder

    Code Block
    languagepy
    themeMidnight
    titlerun on Vivado TCL (Script generates design and export files into "<project folder>\prebuilt\hardware\<short name>")
    TE::hw_build_design -export_prebuilt


    Info

    Using Vivado GUI is the same, except file export to prebuilt folder.


  6. Create and configure your PetaLinux project with exported .xsa-file, see PetaLinux KICKstart
    • use TE Template from "<project folder>\os\petalinux"
    • use exported .xsa file from "<project folder>\prebuilt\hardware\<short name>" . Note: HW Export from Vivado GUI creates another path as default workspace.

    • The build images are located in the "<plnx-proj-root>/images/linux" directory

  7. Configure the boot.scr file as needed, see Distro Boot with Boot.scr
  8. Copy PetaLinux build image files to prebuilt folder
    • copy u-boot.elf, image.ub and boot.scr from "<plnx-proj-root>/images/linux" to prebuilt folder

      Info

      "<project folder>\prebuilt\os\petalinux\<ddr size>" or "<project folder>\prebuilt\os\petalinux\<short name>"


      Page properties
      hiddentrue
      idComments

      This step depends on Xilinx Device/Hardware

      for Zynq-7000 series

      • copy u-boot.elf, image.ub and boot.scr from "<plnx-proj-root>/images/linux" to prebuilt folder

      for ZynqMP

      • copy u-boot.elf, bl31.elf, image.ub and boot.scr from "<plnx-proj-root>/images/linux" to prebuilt folder

      for ...

      • ...


  9. Generate Programming Files with Vitis

    Code Block
    languagepy
    themeMidnight
    titlerun on Vivado TCL (Script generates applications and bootable files, which are defined in "test_board\sw_lib\apps_list.csv")
    TE::sw_run_vitis -all
    TE::sw_run_vitis (optional; Start Vitis from Vivado GUI or start with TE Scripts on Vivado TCL)


    Note

    TCL scripts generate also platform project, this must be done manually in case GUI is used. See Vitis


Launch

Scroll Ignore
scroll-pdftrue
scroll-officetrue
scroll-chmtrue
scroll-docbooktrue
scroll-eclipsehelptrue
scroll-epubtrue
scroll-htmltrue


Page properties
hiddentrue
idComments

Note:

  • Programming and Startup procedure

Programming

Note

Check Module and Carrier TRMs for proper HW configuration before you try any design.

Reference Design is also available with prebuilt files. It's recommended to use TE prebuilt files for first launch.

Xilinx documentation for programming and debugging: Vivado/SDK/SDSoC-Xilinx Software Programming and Debugging

Get prebuilt boot binaries

  1. Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell
  2. Press 0 and enter to start "Module Selection Guide"
    1. Select assembly version
    2. Validate selection
    3. Select Create and open delivery binary folder

      Info

      Note: Folder "<project folder>\_binaries_<Article Name>" with subfolder "boot_<app name>" for different applications will be generated


QSPI-Boot mode

      Option for Boot.bin on QSPI Flash and image.ub and boot.scr on SD or USB.

  1. Connect JTAG and power module (TE0726 can be powered via JTAG USB or external)
  2. Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"
  3. Type on Vivado TCL Console: TE::pr_program_flash -swapp u-boot

    Code Block
    languagepy
    themeMidnight
    titlerun on Vivado TCL (Script programs BOOT.bin on QSPI flash)
    TE::pr_program_flash -swapp u-boot
    TE::pr_program_flash -swapp hello_te0820 (optional)


    Note

    To program with Vitis/Vivado GUI, use special FSBL (fsbl_flash) on setup


  4. Copy image.ub and boot.scr on SD or USB
    • use files from (<project foler>/_binaries_<Articel Name>)/boot_linux from generated binary folder,see: Get prebuilt boot binaries
    • or use prebuilt file location, see <design_name>/prebuilt/readme_file_location.txt
    • Important: Do not copy Boot.bin on SD(is not used see SD note), only other files.
  5. Insert SD-Card

SD

Xilinx Zynq devices in CLG225 package do not support SD Card boot directly from ROM bootloader. Use QSPI for primary boot and SD for secondary boot (uboot)

JTAG

Not used on this Example.

Usage

  1. Prepare HW like described on section Programming
  2. Connect UART USB (most cases same as JTAG)
  3. Insert SD Card with image.ub

    Info

    Note: See TRM of the board, which is used.


    Tip

    Starting with Petalinux version 2020.1, the industry standard "Distro-Boot" boot flow for U-Boot was introduced, which significantly expands the possibilities of the boot process and has the primary goal of making booting much more standardised and predictable.
    The boot options described above describe the common boot processes for this hardware; other boot options are possible.
    For more information see Distro Boot with Boot.scr


  4. Power On PCB

    Expand
    titleboot process

    1. Zynq Boot ROM loads FSBL from QSPI into OCM,

    2. FSBL init PS, programs PL using the bitstream and loads U-boot from QSPI into DDR,

    3. U-boot loads Linux (image.ub) from SD/QSPI/... into DDR


    Page properties
    hiddentrue
    idComments

    This step depends on Xilinx Device/Hardware

    for Zynq-7000 series

    1. Zynq Boot ROM loads FSBL from SD/QSPI into OCM,

    2. FSBL init the PS, programs the PL using the bitstream and loads U-boot from SD/QSPI into DDR,

    3. U-boot loads Linux (image.ub) from SD/QSPI/... into DDR


    for ZynqMP???

    1. ZynqMP Boot ROM loads FSBL from SD/QSPI into OCM,

    2. FSBL init the PS, programs the PL using the bitstream and loads PMU, ATF and U-boot from SD/QSPI into DDR,

    3. U-boot loads Linux (image.ub) from SD/QSPI/... into DDR


    for Microblaze

    1. FPGA Loads Bitfile from Flash,

    2. MCS Firmware configure SI5338 and starts Microblaze,

    3. SREC Bootloader from Bitfile Firmware loads U-Boot into DDR (This takes a while),

    4. U-boot loads Linux from QSPI Flash into DDR


    for native FPGA

    ...


Linux

  1. Open Serial Console (e.g. putty)
    1. Speed: 115200
    2. COM Port: Win OS, see device manager, Linux OS see  dmesg |grep tty  (UART is *USB1)

      Info

      Win OS, see device manager, Linux OS see dmesg |grep tty (UART is *USB1)


  2. Linux Console:

    Code Block
    languagebash
    themeMidnight
    petalinux login: root
    Password: root


  3. You can use Linux shell now.

    Code Block
    languagebash
    themeMidnight
    i2cdetect -y -r 0	(check I2C 0 Bus)
    dmesg | grep rtc	(RTC check)
    udhcpc				(ETH0 check)
    lsusb				(USB check)


  4. Option Features
    1. Webserver to get access to Zynq
      • insert IP on web browser to start web interface
    2. init.sh scripts
      • add init.sh script on SD, content will be load automatically on startup (template included in ./misc/SD)


System Design - Vivado

Scroll Ignore
scroll-pdftrue
scroll-officetrue
scroll-chmtrue
scroll-docbooktrue
scroll-eclipsehelptrue
scroll-epubtrue
scroll-htmltrue


Page properties
hiddentrue
idComments

Note:

  • Description of Block Design, Constrains... BD Pictures from Export...

Block Design

Scroll Title
anchorFigure_BD
title-alignmentcenter
titleBlock Design
Image Added


PS Interfaces

Page properties
hiddentrue
idComments

Note:

  • optional for Zynq / ZynqMP only

  • add basic PS configuration


Scroll Title
anchorTable_PSI
titlePS Interfaces

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
style
widths
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

TypeNote
DDR---
QSPIMIO
SD1MIO
I2C1MIO
UART1MIO
GPIOMIO
TTC0..1EMIO
WDTEMIO
USB0MIO, ETH over USB
USB RSTMIO


Constrains

Basic module constrains

Code Block
languageruby
title_i_bitgen_common.xdc
#
# Common BITGEN related settings for TE0726
#
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property CFGBVS VCCO [current_design]

set_property BITSTREAM.CONFIG.UNUSEDPIN PULLUP [current_design]

Design specific constrain

Software Design - Vitis

Scroll Ignore
scroll-pdftrue
scroll-officetrue
scroll-chmtrue
scroll-docbooktrue
scroll-eclipsehelptrue
scroll-epubtrue
scroll-htmltrue


Page properties
hiddentrue
idComments
Note:
  • optional chapter separate

  • sections for different apps

For SDK project creation, follow instructions from:

Vitis

Application

Page properties
hiddentrue
idComments

----------------------------------------------------------

FPGA Example

scu

MCS Firmware to configure SI5338 and Reset System.

srec_spi_bootloader

TE modified 2020.2 SREC

Bootloader to load app or second bootloader from flash into DDR

Descriptions:

  • Modified Files: blconfig.h, bootloader.c
  • Changes:
    • Add some console outputs and changed bootloader read address.
    • Add bugfix for 2018.2 qspi flash

xilisf_v5_11

TE modified 2020.2 xilisf_v5_11

  • Changed default Flash type to 5.

----------------------------------------------------------

Zynq Example:

fsbl

TE modified 2020.2 FSBL

General:

  • Modified Files: main.c, fsbl_hooks.h/.c (search for 'TE Mod' on source code)
  • Add Files: te_fsbl_hooks.h/.c (for hooks and board)

  • General Changes: 
    • Display FSBL Banner and Device ID

Module Specific:

  • Add Files: all TE Files start with te_*
    • READ MAC from EEPROM and make Address accessible by UBOOT (need copy defines on uboot platform-top.h)
    • CPLD access
    • Read CPLD Firmware and SoC Type
    • Configure Marvell PHY

fsbl_flash

TE modified 2020.2 FSBL

General:

  • Modified Files: main.c
  • General Changes:
    • Display FSBL Banner
    • Set FSBL Boot Mode to JTAG
    • Disable Memory initialisation

ZynqMP Example:

----------------------------------------------------------

zynqmp_fsbl

TE modified 2020.2 FSBL

General:

  • Modified Files: xfsbl_main.c, xfsbl_hooks.h/.c, xfsbl_board.h/.c (search for 'TE Mod' on source code)
  • Add Files: te_xfsbl_hooks.h/.c (for hooks and board)
  • General Changes: 
    • Display FSBL Banner and Device Name

Module Specific:

  • Add Files: all TE Files start with te_*
    • Si5338 Configuration
    • ETH+OTG Reset over MIO

zynqmp_fsbl_flash

TE modified 2020.2 FSBL

General:

  • Modified Files: xfsbl_initialisation.c, xfsbl_hw.h, xfsbl_handoff.c, xfsbl_main.c
  • General Changes:
    • Display FSBL Banner
    • Set FSBL Boot Mode to JTAG
    • Disable Memory initialisation


zynqmp_pmufw

Xilinx default PMU firmware.

----------------------------------------------------------

General Example:

hello_te0820

Hello TE0820 is a Xilinx Hello World example as endless loop instead of one console output.

u-boot

U-Boot.elf is generated with PetaLinux. Vitis is used to generate Boot.bin.


Template location: ./sw_lib/sw_apps/

zynq_fsbl

TE modified 2020.2 FSBL

General:

  • Modified Files:main.c, fsbl_hooks.h/.c (search for 'TE Mod' on source code)
  • Add Files: te_fsbl_hooks.h/.c(for hooks and board)\n\

  • General Changes: 
    • Display FSBL Banner and Device ID

Module Specific:

  • ---

zynq_fsbl_flash

TE modified 2020.2 FSBL

General:

  • Modified Files: main.c
  • General Changes:
    •  Display FSBL Banner
    • Set FSBL Boot Mode to JTAG
    • Disable Memory initialisation

hello_te0726

Hello TE0726 is a Xilinx Hello World example as endless loop instead of one console output.

u-boot

U-Boot.elf is generated with PetaLinux. SDK/HSI is used to generate Boot.bin.

Software Design -  PetaLinux

Scroll Ignore
scroll-pdftrue
scroll-officetrue
scroll-chmtrue
scroll-docbooktrue
scroll-eclipsehelptrue
scroll-epubtrue
scroll-htmltrue


Page properties
hiddentrue
idComments
Note:
  • optional chapter separate

  • sections for linux

  • Add "No changes." or "Activate: and add List"

For PetaLinux installation and  project creation, follow instructions from:

Config

Start with petalinux-config or petalinux-config --get-hw-description

Changes:

For 512MB variant:

  • No changes

For 64MB variant only:

  • CONFIG_SUBSYSTEM_AUTOCONFIG_U__BOOT = y
  • CONFIG_SUBSYSTEM_NETBOOT_OFFSET = 0x2000000

For 128MB variant only:

  • CONFIG_SUBSYSTEM_AUTOCONFIG_U__BOOT = y
  • CONFIG_SUBSYSTEM_NETBOOT_OFFSET = 0x4000000

U-Boot

Start with petalinux-config -c u-boot

Changes:

  • CONFIG_ENV_IS_NOWHERE=y

  • # CONFIG_ENV_IS_IN_SPI_FLASH is not set

Change platform-top.h:

Device Tree

Code Block
languagejs
/include/ "system-conf.dtsi"
/ {
};
 
 
/* USB PHY */
 
/{
    usb_phy0: usb_phy@0 {
        compatible = "ulpi-phy";
        #phy-cells = <0>;
        reg = <0xe0002000 0x1000>;
        view-port = <0x0170>;
        drv-vbus;
    };
};
 
&usb0 {
    dr_mode = "host";
    //dr_mode = "peripheral";
    usb-phy = <&usb_phy0>;
};
 
/* I2C1 */
 
&i2c1 {
    #address-cells = <1>;
    #size-cells = <0>;
 
    i2cmux0: i2cmux@70  {
        compatible = "nxp,pca9544";
        #address-cells = <1>;
        #size-cells = <0>;
        reg = <0x70>;
 
 
        i2c1@0 {
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <0>;
 
            id_eeprom@50 {
                compatible = "atmel,24c32";
                reg = <0x50>;
            };
 
        };
        i2c1@1 {    // Display Interface Connector
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <1>;
        };
        i2c1@2 {    // HDMI Interface Connector
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <2>;
        };
        i2c1@3 {    // Camera Interface Connector
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <3>;
        };
    };
 
};


Kernel

Start with petalinux-config -c kernel

Changes:

  • CONFIG_MII=y

  • CONFIG_XILINX_GMII2RGMII=y

  • CONFIG_USB_USBNET=y

  • CONFIG_USB_NET_AX8817X=y

  • CONFIG_USB_NET_AX88179_178A=y

  • CONFIG_USB_NET_CDCETHER=y

  • # CONFIG_USB_NET_CDC_EEM is not set

  • CONFIG_USB_NET_CDC_NCM=y

  • # CONFIG_USB_NET_HUAWEI_CDC_NCM is not set

  • # CONFIG_USB_NET_CDC_MBIM is not set

  • # CONFIG_USB_NET_DM9601 is not set

  • # CONFIG_USB_NET_SR9700 is not set

  • # CONFIG_USB_NET_SR9800 is not set

  • # CONFIG_USB_NET_SMSC75XX is not set

  • CONFIG_USB_NET_SMSC95XX=y

  • # CONFIG_USB_NET_GL620A is not set

  • CONFIG_USB_NET_NET1080=y

  • # CONFIG_USB_NET_PLUSB is not set

  • # CONFIG_USB_NET_MCS7830 is not set

  • # CONFIG_USB_NET_RNDIS_HOST is not set

  • CONFIG_USB_NET_CDC_SUBSET_ENABLE=y

  • CONFIG_USB_NET_CDC_SUBSET=y

  • # CONFIG_USB_ALI_M5632 is not set

  • # CONFIG_USB_AN2720 is not set

  • CONFIG_USB_BELKIN=y

  • CONFIG_USB_ARMLINUX=y

  • # CONFIG_USB_EPSON2888 is not set

  • # CONFIG_USB_KC2190 is not set

  • CONFIG_USB_NET_ZAURUS=y

  • # CONFIG_USB_NET_CX82310_ETH is not set

  • # CONFIG_USB_NET_KALMIA is not set

  • # CONFIG_USB_NET_QMI_WWAN is not set

  • # CONFIG_USB_NET_INT51X1 is not set

  • # CONFIG_USB_SIERRA_NET is not set

  • # CONFIG_USB_VL600 is not set

  • # CONFIG_USB_NET_CH9200 is not set

  • # CONFIG_USB_NET_AQC111 is not set

  • CONFIG_USBIP_CORE=y

  • # CONFIG_USBIP_VHCI_HCD is not set

  • # CONFIG_USBIP_HOST is not set

  • # CONFIG_USBIP_VUDC is not set

  • # CONFIG_USBIP_DEBUG is not set

Change linux-xlnx_%.bbappend:

Code Block
languagejs
FILESEXTRAPATHS_prepend := "${THISDIR}/${PN}:"

SRC_URI += "file://devtool-fragment.cfg \
            file://0001-QSPI-s25fl127_8-2020_2.patch \
            "
  • Add 0001-QSPI-s25fl127_8-2020_2.patch to "<project folder>\project-spec\meta-user\recipes-kernel\linux\linux-xlnx\"

Rootfs

Start with petalinux-config -c rootfs

Changes:

  • CONFIG_i2c-tools=y
  • CONFIG_busybox-httpd=y (for web server app)
  • CONFIG_packagegroup-petalinux-utils = y
  • CONFIG_util-linux-umount=y
  • CONFIG_util-linux-mount=y

Applications

startup

Script App to load init.sh from SD Card if available.

See: \os\petalinux\project-spec\meta-user\recipes-apps\startup\files

webfwu

Webserver application accemble for Zynq access. Need busybox-httpd

Additional Software

Scroll Ignore
scroll-pdftrue
scroll-officetrue
scroll-chmtrue
scroll-docbooktrue
scroll-eclipsehelptrue
scroll-epubtrue
scroll-htmltrue


Page properties
hiddentrue
idComments
Note:
  • Add description for other Software, for example SI CLK Builder ...
  • SI5338 and SI5345 also Link to:

No additional software is needed

Appx. A: Change History and Legal Notices

Scroll Ignore
scroll-pdftrue
scroll-officetrue
scroll-chmtrue
scroll-docbooktrue
scroll-eclipsehelptrue
scroll-epubtrue
scroll-htmltrue

Document Change History

To get content of older revision  got to "Change History"  of this page and select older document revision number.

Page properties
hiddentrue
idComments
  • Note this list must be only updated, if the document is online on public doc!
  • It's semi automatically, so do following
    • Add new row below first

    • Copy "Page Information Macro(date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf export template

    • Metadata is only used of compatibility of older exports


Scroll Title
anchorTable_dch
titleDocument change history.

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
style
widths2*,*,3*,4*
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

DateDocument Revision

Authors

Description

Page info
modified-date
modified-date
dateFormatyyyy-MM-dd

Page info
infoTypeCurrent version
dateFormatyyyy-MM-dd
prefixv.
typeFlat

Page info
infoTypeModified by
typeFlat

  • 2020.2 release
2020-06-23v.17John Hartfiel
  • typo

2020-04-08

v.16John Hartfiel
  • Design update
  • Programming issue note
2020-03-25v.14John Hartfiel
  • script update
2020-02-19v.13Mohsen Chamanbaz
  • 2019.2 release
  • docu update

2019-12-13

v.12

John Hartfiel

  • 2018.3 release
2018-07-13v.11John Hartfiel
  • 2018.2 release

2018-05-17

v.9John Hartfiel
  • bugfix design for 128MB variant

2018-03-20

v.8John Hartfiel
  • Link update
  • remove typo
2018-02-16v.6John Hartfiel
  • Design update
2018-02-09v.5John Hartfiel
  • 2017.4 release
--all

Page info
infoTypeModified users
dateFormatyyyy-MM-dd
typeFlat

--



Legal Notices

Include Page
IN:Legal Notices
IN:Legal Notices


Scroll Only
scroll-pdftrue
scroll-officetrue
scroll-chmtrue
scroll-docbooktrue
scroll-eclipsehelptrue
scroll-epubtrue
scroll-htmltrue


HTML
<style>
.wiki-content .columnLayout .cell.aside {
width: 0%;
}</style>



Scroll pdf ignore


Custom_fix_page_content

Table of contents

Table of Contents
outlinetrue