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Signals, Interfaces and Pins

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I/O signals connected to the SoCs of the FPGA SoC's I/O bank and B2B connectorbanks connected to the board's pin headers:

Bank	Type	B2B Connector	I/O Signal Count	Bank Voltage
14	HR	J3	8 I/O's, 4 LVDS pairs	1.8V
34	HR	J2	42 I/Os, 21 LVDS pairs	VCCIO34
35	HR	J1	42 I/Os, 21 LVDS pairs	VCCIO35

Table 2: General overview of PL single ended and LVDS I/O signals connected to the B2B connectors.pin headers

Bank	VCCIO	I/O's Count	Available On Connectors	Notes
0	3.3V	7	4	4 I/O's used for JTAG interface, 3 control signals (DONE, PROG_B, INIT).
14	3.3V	12	11	8 I/O's (4 LVDS pairs) connected to J3, 3 I/O's to XMOD header JB1 (2 UART I/O's, 1 user I/O), 1 I/O to LED D2.
15	1.8V	18	0	Used for optional HyperFlash™ U4.
34	User select	42	42	0-Ohm resistor R17 option to select 1.8V I/O-bank VCCIO.
35	User select	42	42	0-Ohm resistor R25 option to select 1.8V I/O-bank VCCIO.

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