Page History

Template Revision 2.8 - on construction

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hidden	true
id	Comments

Important General Note:

...

Export PDF to download, if vivado revision is changed!

Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro

01-25	3.1.10	removed u-boot.dtb from QSPI-Boot mode and SD-Boot mode. Is implemented in BOOT.bin corrected Boot Source File in Boot Script-File	ma
2022-01-14	3.1.9	extended notes for microblaze boot process with linux add u.boot.dtb to petalinux notes add dtb to prebuilt content replace 20.2 with 21.2	jh
2021-06-28	3.1.8	added boot process for Microblaze minor typos, formatting	ma
2021-06-01	3.1.7	carrier reference note	jh
2021-05-04	3.1.6	removed zynq_ from zynq_fsbl	ma
2021-04-28	3.1.5	added macro "Scroll ignore" for suppression of horizontal dividing lines during .pdf-export minor typos, formatting	ma
2021-04-27	3.1.4	Version History changed from list to table Design flow removed step 5 from Design flow changed link from TE Board Part Files to Vivado Board Part Flow changed cmd shell from picture to codeblock added hidden template for "Copy PetaLinux build image files", depending from hardware added hidden template for "Power on PCB", depending from hardware Usage update of boot process Requirements - Hardware added "^*used as reference" for hardware requirements all placed a horizontal separation line under each chapter heading changed title-alignment for tables from left to center all tables added "<project folder>\board_files" in Vivado design sources	ma
	3.1.3	Design Flow formatting Launch formatting	ma
	3.1.2	minor typing corrections replaced SDK by Vitis changed from / to \ for windows paths replaced <design name> by <project folder> added "" for path names added boot.scr description added USB for programming	ma
	3.1.1	swapped order from prebuilt files minor typing corrections removed Win OS path length from Design flow, added as caution in Design flow	ma
	3.1	Fix problem with pdf export and side scroll bar update 19.2 to 20.2 add prebuilt content option
	3.0	add fix table of content add table size as macro removed page initial creator

Custom_table_size_100

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Figure template (note: inner scroll ignore/only only with drawIO object):

...

anchor	Figure_xyz
title	Text

Scroll Ignore
Create DrawIO object here: Attention if you copy from other page, use

Scroll Only
image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed

...

Table template:

Layout macro can be use for landscape of large tables
Set column width manually(can be used for small tables to fit over whole page) or leave empty (automatically)

...

anchor	Table_xyz
title	Text

...

Scroll pdf ignore

Overview

Page properties

hidden	true
id	Comments

Notes :

short description of the design
Short Link of "Scroll only" macro:
- Use short link the Wiki Resource page, for example: http://trenz.org/te0720-info
- List of available short links: https://wiki.trenz-electronic.de/display/CON/Redirects

MicroBlaze Design with Hello TE0725 example in endless loop.

Refer to http://trenz.org/te0725-info for the current online version of this manual and other available documentation.

Key Features

Page properties

hidden	true
id	Comments

Notes :

Add basic key futures, which can be tested with the design

Excerpt
Vivado/Vitis 2019.2 MicroBlaze QSPI I2C UART

...

Notes :

add every update file on the download
add design changes on description

...

anchor	Table_DRH
title	Design Revision History

Important General Note:

Export PDF to download, if vivado revision is changed!

Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro

Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)

Figure template (note: inner scroll ignore/only only with drawIO object):

Scroll Title

anchor	Figure_xyz
title	Text

Scroll Ignore
Create DrawIO object here: Attention if you copy from other page, use

Scroll Only
image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed

Table template:
- Layout macro can be use for landscape of large tables
- Set column width manually (can be used for small tables to fit over whole page) or leave empty (automatically)
Scroll Title
anchor Table_xyz
title Text
Scroll Table Layout
orientation portrait
sortDirection ASC
repeatTableHeaders default
style
widths

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2019.2 release

...

2018.2 update

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Board Part update reference link only

...

initial release

- - Comment
    1 2
...

Overview

Scroll Ignore

scroll-pdf	true
scroll-office	true
scroll-chm	true
scroll-docbook	true
scroll-eclipsehelp	true
scroll-epub	true
scroll-html	true

Page properties

hidden	true
id	Comments

Notes :

short description of the design
Short Link of "Scroll only" macro:
- Use short link the Wiki Resource page, for example: http://trenz.org/te0720-info
- List of available short links: https://wiki.trenz-electronic.de/display/CON/Redirects

MicroBlaze Design with Hello TE0725 example in endless loop.

Refer to http://trenz.org/te0725-info for the current online version of this manual and other available documentation.

draw.io Diagram

border	true

diagramName	TE0725
simpleViewer	false
width
links	auto
tbstyle	top
lbox	true
diagramWidth	574
revision	2

Key Features

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anchor	Table_KI
title	Known Issues

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Requirements

Software

Page properties

hidden	true
id	Comments

Notes :

list of software which was used to generate the design

...

anchor	Table_SW
title	Software

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
sortByColumn	1
sortEnabled	false
cellHighlighting	true

...

Hardware

Page properties

hidden	true
id	Comments

Notes :

list of software which was used to generate the design

Basic description of TE Board Part Files is available on TE Board Part Files.

Complete List is available on <design name>/board_files/*_board_files.csv

Design supports following modules:

...

anchor	Table_HWM
title	Hardware Modules

...

Design supports following carriers:

...

Add basic key futures, which can be tested with the design

Excerpt
Vivado/Vitis 2021.2 MicroBlaze QSPI I2C UART

Revision History

Page properties

hidden	true
id	Comments

Notes :

add every update file on the download
add design changes on description

Scroll Title

anchor	Table_DRH
title	Design Revision History

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
style
widths
sortByColumn	1
sortEnabled	false
cellHighlighting	true

Date	Vivado	Project Built	Authors	Description
2022-08-29	2021.2	TE0725-test_board_noprebuilt-vivado_2021.2-build_15_20220829124226.zip TE0725-test_board-vivado_2021.2-build_15_20220829124226.zip	Waldemar Hanemann	2021.2 update Documentation style update
2020-04-20	2019.2	TE0725-test_board_noprebuilt-vivado_2019.2-build_10_20200420092827.zip TE0725-test_board-vivado_2019.2-build_10_20200420092815.zip	John Hartfiel	2019.2 update
2018-08-09	2018.2	TE0725-test_board_noprebuilt-vivado_2018.2-build_02_20180809122533.zip TE0725-test_board-vivado_2018.2-build_02_20180809122018.zip	John Hartfiel	2018.2 update
2018-03-18	2017.4	TE0725-test_board_noprebuilt-vivado_2017.4-build_07_20180319171220.zip TE0725-test_board-vivado_2017.4-build_07_20180319171209.zip	John Hartfiel	Board Part update reference link only
2018-03-16	2017.4	TE0725-test_board_noprebuilt-vivado_2017.4-build_07_20180316163402.zip TE0725-test_board-vivado_2017.4-build_07_20180316163351.zip	John Hartfiel	initial release

Release Notes and Know Issues

Page properties

hidden	true
id	Comments

Notes :

add known Design issues and general notes for the current revision
do not delete known issue, add fixed version time stamp if issue fixed

Scroll Title

anchor	Table_KI
title	Known Issues

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
style
widths
sortByColumn	1
sortEnabled	false
cellHighlighting	true

Issues	Description	Workaround	To be fixed version
No known issues	---	---	---

Requirements

Software

Page properties

hidden	true
id	Comments

Notes :

list of software which was used to generate the design

...

anchor	Table_AHW
title	Additional Hardware

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Content

Page properties

hidden	true
id	Comments

Notes :

content of the zip file

For general structure and of the reference design, see Project Delivery - Xilinx devices

Design Sources

...

anchor	Table_DS
title	Design sources

...

Note
Vitis	2021.2	needed, Vivado is included into Vitis installation

Hardware

Page properties

hidden	true
id	Comments

Notes :

list of software which was used to generate the design

Basic description of TE Board Part Files is available on TE Board Part Files.

Complete List is available on <design name>/board_files/*_board_files.csv

Design supports following modules:

Scroll Title

anchor	Table_HWM
title	Hardware Modules

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
style
widths

Additional Sources

...

anchor	Table_ADS
title	Additional design sources

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Prebuilt

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hidden	true
id	Comments

Notes :

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anchor	Table_PF
title	Prebuilt files

...

Module Model	Board Part Short Name	PCB Revision Support	DDR	QSPI Flash	EMMC	Others	Notes
TE0725-03-15-1C	15_1c	REV03\|REV02\|REV01	NA	32MB	NA	8MB HypeRAM	NA
TE0725-03-35-2C	35_2c	REV03\|REV02\|REV01	NA	32MB	NA	8MB HypeRAM	NA
TE0725-03-100-2C	100_2c	REV03\|REV02\|REV01	NA	32MB	NA	8MB HypeRAM	NA
TE0725-03-100-2CF	100_2c	REV03\|REV02\|REV01	NA	32MB	NA	8MB HypeRAM	POF assembled
TE0725-03-100-2I9	100_2i	REV03\|REV02\|REV01	NA	32MB	NA	8MB HypeRAM	NA
TE0725-03-35-2I	35_2i	REV03\|REV02\|REV01	NA	32MB	NA	8MB HypeRAM	NA

Design supports following carriers:

Scroll Title

anchor	Table_HWC
title-alignment	center
title	Hardware Carrier

Scroll Table Layout

repeatTableHeaders
orientation	portrait
sortDirection	ASC

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File

...

File-Extension

...

Description

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Debian SD-Image

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*.img

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Debian Image for SD-Card

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MCS-File

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*.mcs

...

Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)

...

MMI-File

...

*.mmi

...

File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)

...

Carrier Model	Notes
---

^*used as reference

Additional HW Requirements:

Scroll Title

anchor	Table_AHW
title	Additional Hardware

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
style
widths
sortByColumn	1
sortEnabled	false
cellHighlighting	true

Additional Hardware	Notes
TE0790 JTAG Programmer	It's not recommended to use TE0790 for power supply( TE0790 TRM#PowerandPower-OnSequence)
External power supply

^*used as reference

Content

Page properties

hidden	true
id	Comments

Notes :

content of the zip file

For general structure and of the reference design, see Project Delivery - AMD devices

Design Sources

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SREC-File

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*.srec

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File

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File-Extension

...

Description

...

Debian SD-Image

...

*.img

...

Debian Image for SD-Card

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MCS-File

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*.mcs

...

Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)

...

MMI-File

...

*.mmi

...

File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)

...

Type	Location	Notes
Vivado	<project folder>\block_design <project folder>\constraints <project folder>\ip_lib <project folder>\board_files	Vivado Project will be generated by TE Scripts
Vitis	<project folder>\sw_lib	Additional Software Template for Vitis and apps_list.csv with settings automatically for Vitis app generation

Additional Sources

Scroll Title

anchor	Table_ADS
title	Additional design sources

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
style
widths
sortByColumn	1
sortEnabled	false
cellHighlighting	true

Type	Location	Notes
--	--	--

Prebuilt

Page properties

Download

Reference Design is only usable with the specified Vivado/Vitis/PetaLinux version. Do never use different Versions of Xilinx Software for the same Project.

...

Important set new Vivado version link on every Design update of new vivado version!
Set Link to download folder (Remove ../de/.. ../en/.. from url) for example: https://shop.trenz-electronic.de/Download/?path=Trenz_Electronic/Modules_and_Module_Carriers/4x5/TE0712/Reference_Design/2018.2/test_board

Notes :

prebuilt files

Template Table:

Scroll Title

anchor	Table_PF
title	Prebuilt files

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
style
widths
sortByColumn	1
sortEnabled	false
cellHighlighting	true

File	File-Extension	Description
BIF-File	*.bif	File with description to generate Bin-File
BIN-File	*.bin	Flash Configuration File with Boot-Image (Zynq-FPGAs)
BIT-File	*.bit	FPGA (PL Part) Configuration File
DebugProbes-File	*.ltx	Definition File for Vivado/Vivado Labtools Debugging Interface
Debian SD-Image	*.img	Debian Image for SD-Card
Diverse Reports	---	Report files in different formats
Hardware-Platform-Specification-Files	*.xsa	Exported Vivado Hardware Specification for Vitis and PetaLinux
LabTools Project-File	*.lpr	Vivado Labtools Project File
MCS-File	*.mcs	Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)
MMI-File	*.mmi	File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)
OS-Image	*.ub	Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)
Software-Application-File	*.elf	Software Application for Zynq or MicroBlaze Processor Systems
SREC-File	*.srec	Converted Software Application for MicroBlaze Processor Systems

Scroll Title

anchor	Table_PF
title	Prebuilt files (only on ZIP with prebuilt content)

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
style
widths
sortByColumn	1
sortEnabled	false
cellHighlighting	true

File	File-Extension	Description
BIT-File	*.bit	FPGA (PL Part) Configuration File
DebugProbes-File	*.ltx	Definition File for Vivado/Vivado Labtools Debugging Interface
Debian SD-Image	*.img	Debian Image for SD-Card
Diverse Reports	---	Report files in different formats
Hardware-Platform-Specification-Files	*.xsa	Exported Vivado Hardware Specification for Vitis and PetaLinux
LabTools Project-File	*.lpr	Vivado Labtools Project File
MCS-File	*.mcs	Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)
MMI-File	*.mmi	File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)
Software-Application-File	*.elf	Software Application for Zynq or MicroBlaze Processor Systems

Download

Reference Design is only usable with the specified Vivado/Vitis/PetaLinux version. Do never use different Versions of Xilinx Software for the same Project.

Reference Design is available on:

TE0725 "Test Board" Reference Design

Design Flow

Page properties

hidden	true
id	Comments

Notes :

Basic Design Steps
Add/ Remove project specific description

Note
Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first lunch.

Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.

Launch

...

Note:

Programming and Startup procedure

Note
Check Module and Carrier TRMs for proper HW configuration before you try any design.

Xilinx documentation for programming and debugging: Vivado/SDK/SDSoC-Xilinx Software Programming and Debugging

Get prebuilt boot binaries

_create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell
Press 0 and enter to start "Module Selection Guide"
1. Select assembly version
2. Validate selection
3. Select Create and open delivery binary folder
  Note: Folder (<project foler>/_binaries_<Artikel Name>) with subfolder (boot_<app name>) for different applications will be generated

QSPI

Connect JTAG and power on PCB
(if not done) Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd" or open with "vivado_open_project_guimode.cmd", if generated.
Type on Vivado Console: TE::pr_program_flash
Note: Alternative use SDK or setup Flash on Vivado manually
Reboot (if not done automatically)

SD

Not used on this Example.

JTAG

Connect JTAG and power on PCB
(if not done) Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd" or open with "vivado_open_project_guimode.cmd", if generated.
Open Vivado HW Manager
Program Bitfile

Usage

Prepare HW like described on section Programming
Connect UART USB (most cases same as JTAG)
Power On PCB (Do not restart, if you use Bitfile programming)
Note: FPGA Loads Bitfile from Flash

UART

Open Serial Console (e.g. putty)
1. Speed: 9600
2. COM Port: Win OS, see device manager, Linux OS see dmesg |grep tty (UART is *USB1)
Uart Console:
Hello TE0725 will run on endless loop.

System Design - Vivado

Page properties

hidden	true
id	Comments

Note:

Description of Block Design, Constrains... BD Pictures from Export...

Block Design

Image Removed

Constrains

Basic module constrains

Code Block

language	ruby
title	_i_bitgen_common.xdc

set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property BITSTREAM.CONFIG.CONFIGRATE 66 [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property CFGBVS VCCO [current_design]
set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design]
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
set_property BITSTREAM.CONFIG.M1PIN PULLNONE [current_design]
set_property BITSTREAM.CONFIG.M2PIN PULLNONE [current_design]
set_property BITSTREAM.CONFIG.M0PIN PULLNONE [current_design]

set_property BITSTREAM.CONFIG.USR_ACCESS TIMESTAMP [current_design]

Design specific constrain

---

Software Design - Vitis

Page properties

hidden	true
id	Comments

Note:

optional chapter separate
sections for different apps

For SDK project creation, follow instructions from:

Vitis

Application

...

hidden	true
id	Comments

----------------------------------------------------------

FPGA Example

scu

MCS Firmware to configure SI5338 and Reset System.

srec_spi_bootloader

TE modified 2019.2 SREC

Bootloader to load app or second bootloader from flash into DDR

Descriptions:

Modified Files: blconfig.h, bootloader.c
Changes:
- Add some console outputs and changed bootloader read address.
- Add bugfix for 2018.2 qspi flash

xilisf_v5_11

TE modified 2019.2 xilisf_v5_11

Important set new Vivado version link on every Design update of new vivado version!
Set Link to download folder (Remove ../de/.. ../en/.. from url) for example: https://shop.trenz-electronic.de/Download/?path=Trenz_Electronic/Modules_and_Module_Carriers/4x5/TE0712/Reference_Design/2018.2/test_board

Reference Design is available on:

TE0725 "Test Board" Reference Design

Design Flow

Scroll Ignore

scroll-pdf	true
scroll-office	true
scroll-chm	true
scroll-docbook	true
scroll-eclipsehelp	true
scroll-epub	true
scroll-html	true

Page properties

hidden	true
id	Comments

Notes :

Basic Design Steps
Add/ Remove project specific description

Note
Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first lunch.

Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.

Launch

Scroll Ignore

scroll-pdf	true
scroll-office	true
scroll-chm	true
scroll-docbook	true
scroll-eclipsehelp	true
scroll-epub	true
scroll-html	true

Page properties

hidden	true
id	Comments

Note:

Programming and Startup procedure

Programming

Note

Check Module and Carrier TRMs for proper HW configuration before you try any design.

Reference Design is also available with prebuilt files. It's recommended to use TE prebuilt files for first launch.

Xilinx documentation for programming and debugging: Vivado/SDK/SDSoC-Xilinx Software Programming and Debugging

Get prebuilt boot binaries

Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell
Press 0 and enter to start "Module Selection Guide"
1. Select assembly version
2. Validate selection
3. Select create and open delivery binary folder
  Info
  Note: Folder "<project folder>\_binaries_<Article Name>" with subfolder "boot_<app name>" for different applications will be generated

QSPI

Connect JTAG and power on carrier with module
Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"
Code Block
language py
theme Midnight
title run on Vivado TCL (Script programs .mcs-File on QSPI flash)
TE::pr_program_flash -swapp hello_te0725
Press the reset button to start the application and see the output in the console

SD

Not used on this Example.

JTAG

Connect JTAG and power on PCB
Open Vivado HW Manager
Program FPGA with Bitfile from "prebuilt\hardware\<short dir>\"

Usage

Prepare HW like described on section Programming
Connect UART USB (most cases same as JTAG)

Expand

title	boot process

1. FPGA Loads Bitfile from Flash

3. Hello Trenz will be run on UART console.

info: Do not reboot, if Bitfile programming over JTAG is used as programming method.

UART
Open Serial Console (e.g. putty) Hello TE0725 will run on endless loop.
1. Speed: 9600
2. COM Port: Win OS, see device manager, Linux OS see dmesg |grep tty (UART is *USB1)
  Image Added
  Power On PCB (Do not restart, if you use Bitfile programming)

Vivado HW Manager

Page properties

hidden	true
id	Comments

Note:

Add picture of HW Manager
add notes for the signal either groups or topics, for example:
Control:
- add controllable IOs with short notes..
Monitoring:
- add short notes for signals which will be monitored only
- SI5338 CLKs:
  - Set radix from VIO signals to unsigned integer.
    Note: Frequency Counter is inaccurate and displayed unit is Hz
  - expected CLK Frequency...

VIO Core for signal control and monitoring is not implemented

System Design - Vivado

Scroll Ignore

scroll-pdf	true
scroll-office	true
scroll-chm	true
scroll-docbook	true
scroll-eclipsehelp	true
scroll-epub	true
scroll-html	true

Page properties

hidden	true
id	Comments

Note:

Description of Block Design, Constrains... BD Pictures from Export...

Block Design

Image Added

Constraints

Basic module constraints

Code Block

language	ruby
title	_i_bitgen_common.xdc

set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property BITSTREAM.CONFIG.CONFIGRATE 66 [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property CFGBVS VCCO [current_design]
set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design]
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
set_property BITSTREAM.CONFIG.M1PIN PULLNONE [current_design]
set_property BITSTREAM.CONFIG.M2PIN PULLNONE [current_design]
set_property BITSTREAM.CONFIG.M0PIN PULLNONE [current_design]

set_property BITSTREAM.CONFIG.USR_ACCESS TIMESTAMP [current_design]

Design specific constraints

---

Software Design - Vitis

Scroll Ignore

scroll-pdf	true
scroll-office	true
scroll-chm	true
scroll-docbook	true
scroll-eclipsehelp	true
scroll-epub	true
scroll-html	true

Page properties

hidden	true
id	Comments

Note:

optional chapter separate
sections for different apps

For SDK project creation, follow instructions from:

Vitis

Application

Page properties

hidden	true
id	Comments

----------------------------------------------------------

FPGA Example

scu

MCS Firmware to configure SI5338 and Reset System.

srec_spi_bootloader

TE modified 2019.2 SREC

Bootloader to load app or second bootloader from flash into DDR

Descriptions:

Modified Files: blconfig.h, bootloader.c
Changes:
- Add some console outputs and changed bootloader read address.
- Add bugfix for 2018.2 qspi flash

xilisf_v5_11

TE modified 2019.2 xilisf_v5_11

Changed default Flash type to 5.

----------------------------------------------------------

Zynq Example:

zynq_fsbl

TE modified 2019.2 FSBL

General:

Modified Files:main.c, fsbl_hooks.h/.c (search for 'TE Mod' on source code)
Add Files: te_fsbl_hooks.h/.c(for hooks and board)\n\
General Changes:
- Display FSBL Banner and Device ID

Module Specific:

Add Files: all TE Files start with te_*
- READ MAC from EEPROM and make Address accessible by UBOOT (need copy defines on uboot platform-top.h)
- CPLD access
- Read CPLD Firmware and SoC Type
- Configure Marvell PHY

zynq_fsbl_flash

TE modified 2019.2 FSBL

General:

Modified Files: main.c
General Changes:
- Display FSBL Banner
- Set FSBL Boot Mode to JTAG
- Disable Memory initialisation

ZynqMP Example:

...

Zynq Example:

...

Module Specific:

Add Files: all TE Files start with te_*
- READ MAC from EEPROM and make Address accessible by UBOOT (need copy defines on uboot platform-top.h)
- CPLD access
- Read CPLD Firmware and SoC Type
- Configure Marvell PHY

...

ZynqMP Example:

...

zynqmp_fsbl

TE modified 2019.2 FSBL

General:

Modified Files: xfsbl_main.c, xfsbl_hooks.h/.c, xfsbl_board.h/.c(search for 'TE Mod' on source code)
Add Files: te_xfsbl_hooks.h/.c (for hooks and board)\n\
General Changes:
- Display FSBL Banner and Device Name

Module Specific:

Add Files: all TE Files start with te_*
- Si5338 Configuration
- ETH+OTG Reset over MIO

zynqmp_fsbl_flash

TE modified 2019.2 FSBL

General:

Modified Files: xfsbl_initialisation.c, xfsbl_hw.h, xfsbl_handoff.c, xfsbl_main.c
General Changes:
- Display FSBL Banner
- Set FSBL Boot Mode to JTAG
- Disable Memory initialisation

zynqmp_pmufw

Xilinx default PMU firmware.

----------------------------------------------------------

General Example:

hello_te0820

Hello TE0820 is a Xilinx Hello World example as endless loop instead of one console output.

u-boot

U-Boot.elf is generated with PetaLinux. Vitis is used to generate Boot.bin.

--

General Example:

hello_te0820

Hello TE0820 is a Xilinx Hello World example as endless loop instead of one console output.

u-boot

U-Boot.elf is generated with PetaLinux. Vitis is used to generate Boot.bin.

Template location: "<project folder>\sw_lib\sw_apps\"

hello_te0725

Trenz Hello TE0725 example as endless loop. Output on console.

Template location: \sw_lib\sw_apps\hello_te0725

The printed Text can be modified.

Additional Software

Scroll Ignore

scroll-pdf	true
scroll-office	true
scroll-chm	true
scroll-docbook	true
scroll-eclipsehelp	true
scroll-epub	true
scroll-html	true

Template location: ./sw_lib/sw_apps/

hello_te0725

Hello TE0725 is a Xilinx Hello World example as endless loop instead of one console output.

...

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Note:

Add description for other Software, for example SI CLK Builder ...
SI5338 and SI5345 also Link to:
- Si5345
- Si5338

No additional software is needed.

Appx. A: Change History and Legal Notices

Document Change History

To get content of older revision got to "Change History" of this page and select older document revision number.

Page properties

hidden	true
id	Comments

Note this list must be only updated, if the document is online on public doc!
It's semi automatically, so do following
- Add new row below first
- Copy "Page Information Macro(date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf export template
- Metadata is only used of compatibility of older exports

Scroll Title

anchor	Table_dch
title	Document change history.

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
style
widths	2,,3,4
sortByColumn	1
sortEnabled	false
cellHighlighting	true

Date

Document Revision

Authors

Description

Page info

	modified-date
	modified-date
dateFormat	yyyy-MM-dd

Page info

	current-version
	current-version

...

typo

2020-04-20

v.12

John Hartfiel

2019.2 update
Documentation style update

2018-08-09

v.9

John Hartfiel

2018.2 update

2018.06.05

v.8

John Hartfiel

Board Part Documentation update
Typo correction UART Speed

2018-03-16

v.5

John Hartfiel

2017.4 release

2018-03-12

v.1

Page info

	created-user
	created-user

Initial release

All

Page info

	modified-users
	modified-users

Legal Notices

Include Page

	IN:Legal Notices
	IN:Legal Notices

Scroll Only

HTML
<style> .wiki-content .columnLayout .cell.aside { width: 0%; }</style>

Scroll pdf ignore

Custom_fix_page_content

Trenz Electronic Documentation

Page History

Versions Compared

Old Version 13

New Version Current

Key

Table of contents

Overview

Key Features

Overview

Key Features

Requirements

Software

Hardware

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Revision History

Release Notes and Know Issues

Requirements

Software

Content

Design Sources

Hardware

Additional Sources

Prebuilt

Content

Design Sources

Scroll TitleanchorTable_

Additional Sources

Prebuilt

Download

Download

Design Flow

Launch

Get prebuilt boot binaries

QSPI

SD

JTAG

Usage

UART

System Design - Vivado

Block Design

Image Removed

Constrains

Basic module constrains

Design specific constrain

Software Design - Vitis

Application

scu

srec_spi_bootloader

xilisf_v5_11

Design Flow

Launch

Programming

Get prebuilt boot binaries

QSPI

SD

JTAG

Usage

UART

Vivado HW Manager

System Design - Vivado

Block Design

Image Added

Constraints

Basic module constraints

Design specific constraints

Software Design - Vitis

Application

scu

srec_spi_bootloader

xilisf_v5_11

zynq_fsbl

zynq_fsbl_flash

zynqmp_fsbl

zynqmp

_fsbl_flash

zynqmp_pmufw

zynqmp_fsbl

zynqmp_fsbl_flash

zynqmp_pmufw

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id Comments
Notes :

Scroll Title
anchor Table_