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Firmware for PCB CPLD with designator U18. CPLD Device in Chain: LCMX02-256HC

Feature Summary

  • Reset Management
  • JTAG
  • Power ManagementRest
  • PUD_C
  • LED

Firmware Revision and supported PCB Revision

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Name / opt. VHD NameDirectionPinBank PowerDescription
CPLD_IO / XIO inin17 1.8VFPGA Bank 45 P28
DONEin131.8VFPGA Configuration DONE_0 Pin
EN_PL20(currently internal DCDC Pullup is used to enable power) / currently_not_usedout203.3VEnable module power
F_TCK / C_TCKout81.8VJTAG to FPGA
F_TDI / C_TDIout101.8VJTAG to FPGA
F_TDO / C_TDOin111.8VJTAG to FPGA
F_TMS / C_TMSout91.8VJTAG to FPGA
INIT_Bin161.8VFPGA INIT_B 
JTAGMODEin263.3VEnable JTAG access to CPLD for Firmware update (zero: JTAG routed to moduleFPGA, one: CPLD access)
 / LED1out43.3Vgreen LED D1
N.C. / dummyout53.3Vdummy pin
nRST_SC0 / RESINin213.3VB2B Reset_N
PROG_Bout121.8VFPGA Configuration PROGRAM_B_0 Pin
PUDC_Bout141.8VFPGA PUDC_B
SC1
233.3VB2B JM1-32 / 4x5 Boot MODE Pin  / currently_not_used
SC2inout253.3VB2B JM1-30 / 4x5 PGOOD Pin
SC3in273.3VB2B JM1-28 / 4x5 Power Enable Pin
SC4
283.3VB2B JM1-7 / 4x5 No Sequencing Pin / currently_not_used
TCK / M_TCKin303.3VJTAG from B2B connector
TDI / M_TDIin323.3VJTAG from B2B connector
TDO / M_TDOout13.3VJTAG from B2B connector
TMS / M_TMSin29

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3.3VJTAG from B2B connector


Functional Description

JTAG

JTAG signals routed directly through the CPLD to FPGA. Access between CPLD and FPGA can be multiplexed via JTAGEN (logical one for CPLD, logical zero for FPGA).

Power

EN_PL is set constant one.

SC2 (PGOOD) is zero conditions:

  1. B2B SC3(EN1) is zero
  2.  PROG_B is zero, but B2B nRST_SC0 and B2B SC3(EN1) are set high. In this case PROG_B is not set high with CPLD pullup, so 1.8V is missing on CPLD IO Bank is missing.

Reset

PROG_B is set to zero if SC3(EN1) is zero or nRST_SC0 is zero, otherwise high impedance. Internal Pullup on PROG_B CPLD is enabled.

PUD_C

PUD_C is set to zero. Internal Pullup on power up, see UG570

LED

Green LED D1.

Blink SequencePriorityDescription
********1B2B Reset is set to low
*****ooo2EN1 (power enable) is low
****oooo3Power problem (use PROG_B pullup to check 1.8V)
***ooooo4INIT_B low (CRC or IDCODE error, see UG570)
*ooooooo5Done is low (FPGA not programmed, see UG570)
User Defined6XIO is connected to LED

Appx. A: Change History and Legal Notices

Revision Changes

REV01 to REV02

  • Add 4x5 Module control IOs
  • Rework Power
  • Rework LED

Document Change History

To get content of older revision  got to "Change History"  of this page and select older document revision number.

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DateDocument RevisionCPLD Firmware RevisionSupported PCB RevisionAuthorsDescription

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dateFormatyyyy-MM-dd

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 REV02 REV01, REV02

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Work in progress2017-06-07 


CPLD REV02 finished, Firmware released 2018-06-05

v.3REV01REV01John Hartfiel CPLD REV01 , Firmware released  2016-11-02
2018-03-14

v.1

 REV01REV01

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Initial release

 All  

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Legal Notices

Include Page
IN:Legal Notices
IN:Legal Notices