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Firmware for PCB CPLD with designator U4. CPLD Device in Chain: LCMX02-256HC

Feature Summary

  • Power Management
  • ...JTAG
  • Reset
  • Power
  • LED
  • USER IO

Firmware Revision and supported PCB Revision

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Name / opt. VHD NameDirectionPinDescription
DONE inin13 FPGA FPGA DONE signal
EN_SC3in16B2B Enable Pin
F_TCK / C_TCKout28JTAG FPGA
F_TDI / C_TDIout27JTAG FPGA
F_TDO / C_TDOin23JTAG FPGA
F_TMS / C_TMSout25JTAG FPGA
JTAGSELin26Enable JTAG access to CPLD for Firmware update (zero: JTAG routed to module, one: CPLD access)
MODE_SC1in11B2B Boot Mode Pin
NOSEQ_SC4in12B2B NOSEQ Pin / currently_not_used
nRST_SC0in8B2B Reset
PG_ALLin10Power good from 1.8V Sence on U23
PROG_Bout17FPGA PROG_B Reset
PWR_DISout5Power disable (U1), Module has external pullup
STAT_SC2out14B2B PGOOD
SYSLED1 / LED1out9Green LED D4
TCK_SC7 / M_TCKin30JTAG B2B
TDI_SC6 / M_TDIin32JTAG B2B
TDO_SC5 / M_TDOout1JTAG B2B
TMS_SC8 / M_TMSin29JTAG B2B
UFLout4J1 (Ultra Small Sufrace Mount Coax)
UI_CLK / XB_SCout20FPGA Bank 16 Pin B8
UIO / XA_SCin21FPGA Bank 16 Pin D10

 

Functional Description

JTAG

JTAG signals routed directly through the CPLD to FPGA. Access between CPLD and FPGA can be multiplexed via JTAGEN (logical one for CPLD, logical zero for FPGA) on JM1-89.

Reset

PROG_B is nRST_SC0 and PG_ALL and EN_SC3 after power on delay.

Power

Power Good (STAT_SC2) is PGALL and EN_SC3.

PWR_DIS is high impedance.

USER IO

MODE_SC1 is connected to XBSC.

XA_SC is connected to UFL.

LED

Green LED D4

StatusDescription
OnDone is low, FPGA not programmed
OFFDone is high, FPGA is programmed


Appx. A: Change History and Legal Notices

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DateDocument RevisionCPLD Firmware RevisionSupported PCB RevisionAuthorsDescription

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modified-date
modified-date
dateFormatyyyy-MM-dd

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current-version
current-version
prefixv.


 

  REV01 REV01

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modified-user
modified-user

Work in progress


2017-06-07REV01 , Firmware released  2015-04-17
2018-03-15

v.191

  REV01  REV01

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created-user
created-user

Initial release
 All  

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modified-users
modified-users

 

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