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The following table lists all on the FMC connector assigned net names.



ABCDEFGHJK
1GNDNetJ2_B1GNDPG_C2MGNDPG_M2CGND
GND
2SFPB_RD_PGNDSFPA_TD_PGND
GNDCLK1_PGND
GND
3SFPB_RD_NGNDSFPA_TD_NGND
GNDCLK1_NGND
GND
4GND
GNDGBTCLK0_PGND
GNDCLK0_PGNDCLK2_P
5GND
GNDGBTCLK0_NGND
GNDCLK0_NGNDCLK2_N
6SFPC_RD_PGNDSFPA_RD_PGND
GNDLA00_PGND
GND
7SFPC_RD_NGNDSFPA_RD_NGND

LA00_NLA02_P

8GND
GNDLA01_PGND
GNDLA02_NGND
9GND
GNDLA01_N
GNDLA03_PGND
GND
10SFPD_RD_PGNDLA06_PGND

LA03_NLA04_P

11SFPD_RD_NGNDLA06_NLA05_PGND
GNDLA04_NGND
12GND
GNDLA05_N
GNDLA08_PGND
GND
13GND
GNDGND

LA08_NLA07_P

14
GND
LA09_PGND
GNDLA07_NGND
15
GND
LA09_N
GND
GND
GND
16GND
GNDGND





17GND
GND
GND
GND
GND
18
GND


GND
GND
GND
19
GND
GND





20GNDGBTCLK1_PGND
GND
GND
GND
21GNDGBTCLK1_NGND

GND
GND
GND
22SFPB_TD_PGND
GND





23SFPB_TD_NGND

GND
GND
GND
24GND
GND

GND
GND
GND
25GND
GNDGND





26SFPC_TD_PGND

GND
GND
GND
27SFPC_TD_NGND


GND
GND
GND
28GND
GNDGND





29GND
GNDTCKGND
GND
GND
30SFPD_TD_PGNDFMC_SCLTDI
GND
GND
GND
31SFPD_TD_NGNDFMC_SDATDO





32GND
GND3P3VAUXGND
GND
GND
33GND
GNDTMS
GND
GND
GND
34
GNDGA0






35
GND12VGA1GND
GND
GND
36GND
GND3P3V
GND
GND
GND
37GND
12VGND





38
GNDGND3P3VGND
GND
GND
39
GND3P3VGNDVADJGNDVADJGND
GND
40GND
GND3P3VGNDVADJGNDVADJGND

Table 8: HPC FMC Connector pin assignment.

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Si5345A Pin
Signal Name / Description
Connected ToDirectionNoteDefault

IN0

Reference input clock.

U1Input25.000000 MHz oscillator, Si8208AI
IN1-Not connected.InputNot used.

IN2

-

Not connected.InputNot used.

IN3

CLK2J2-K4/K5InputHPC FMC configured as C2M clock.

A1

-

GNDInputI2C slave device address LSB.
XAXB-Y1Input54.0000 MHz XTAL CX3225SB

OUT0

CLKPLL2F

U5-H6/G5Output

FPGA bank 2.

25MHz
OUT1-Not connected.OutputNot used.---
OUT2GBTCLK1J2-B20/B21OutputM2C via HPC FMC.125MHz
OUT3-Not connected.OutputNot used.---
OUT4-Not connected.OutputNot used.---
OUT5-Not connected.OutputNot used.---
OUT6

-

Not connected.

Output

Not used.---
OUT7GBTCLK0J2-D4/D5OutputM2C via HPC FMC.156.25MHz
OUT8CLK0J2-H4/H5OutputM2C via HPC FMC.156.25MHz
OUT9CLK1J2-G2/G3OutputM2C via HPC FMC.125MHz

 Table 9: Programmable clock generator inputs and outputs.

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Date

Revision

Contributors

Description

Page info
infoTypeModified date
dateFormatyyyy-MM-dd
typeFlat

Martin Rohrmüller

Updated Table 15 and 17 to Rev02.

Added FMC connector pin assignment (Table 8).

Page info
infoTypeCurrent version
prefixv.

32

typeFlat
showVersionsfalse

Page info
infoTypeModified by
typeFlat
showVersionsfalse

  • add default CLK values also to SI section
  • changes on document change history style
2018-08-24v.38Martin Rohrmüller
  • Updated Table 15 and 17 to Rev02.

  • Added FMC connector pin assignment (Table 8).

2018-06-15


v.32


Martin Rohrmüller

  • Initial document.
---

allJan Kumann, John Hartfiel

Page info
infoTypeModified users
typeFlat
showVersionsfalse

  • ---

Table 18: Document change history.

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