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Basic Notes
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- Template is for different design and SDSoC and examples, remove unused or wrong description!
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Online version of this manual and other related documents can be found at https://wiki.trenz-electronic.de/display/PD/Trenz+Electronic+Documentation |
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Table of contents |
Overview
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Key Features
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- PetaLinux
- MicroBlaze
- SREC
- Flash
- MIG
- ETH (ETH1)
- LED
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Revision History
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Release Notes and Know Issues
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Requirements
Software
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Hardware
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Hardware Support
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Basic description of TE Board Part Files is available on TE Board Part Files.
Complete List is available on <design name>/board_files/*_board_files.csv
Design supports following modules:
...
Design supports following carriers:
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Additional HW Requirements:
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Content
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For general structure and of the reference design, see Project Delivery - Xilinx devices
Design Sources
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<style>
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width: 100% !important;
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Important General Note: Export PDF to download, if vivado revision is changed! Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro - Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)
- ...
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Table of contents |
Overview
Microblaze Design with linux example.
Refer to http://trenz.org/te0710-info for the current online version of this manual and other available documentation.
Key Features
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- Vitis/Vivado 2019.2
- PetaLinux
- MicroBlaze
- SREC
- Flash
- MIG
- ETH (ETH1)
- LED
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Revision History
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- add design changes on description
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Date | Vivado | Project Built | Authors | Description |
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2020-04-21 | 2019.2 | TE0710-test_board-vivado_2019.2-build_10_20200421063949.zip TE0710-test_board_noprebuilt-vivado_2019.2-build_10_20200421064005.zip | John Hartfiel | | 2018-03-29 | 2017.4 | te0710-test_board-vivado_2017.4-build_07_20180329130739.zip te0710-test_board_noprebuilt-vivado_2017.4-build_07_20180329130757.zip | John Hartfiel | |
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Release Notes and Know Issues
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- do not delete known issue, add fixed version time stamp if issue fixed
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Issues | Description | Workaround | To be fixed version |
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-- | -- | -- | -- |
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Requirements
Software
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Software | Version | Note |
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Vitis | 2019.2 | - needed
- Vivado is included into Vitis installation
| PetaLinux | 2019.2 | |
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Hardware
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Notes : - list of software which was used to generate the design
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Basic description of TE Board Part Files is available on TE Board Part Files.
Complete List is available on <design name>/board_files/*_board_files.csv
Design supports following modules:
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Module Model | Board Part Short Name | PCB Revision Support | DDR | QSPI Flash | EMMC | Others | Notes |
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TE0710-02-35-2CF | 35_2cf_512mb | REV02 | 512MB | 32MB | NA | NA | less IOs | TE0710-02-35-2IF | 35_2if_512mb | REV02 | 512MB | 32MB | NA | NA | less IOs | TE0710-02-100-2CF | 100_2cf_512mb | REV02 | 512MB | 32MB | NA | NA | NA | TE0710-02-100-2IF | 100_2if_512mb | REV02 | 512MB | 32MB | NA | NA | NA |
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Design supports following carriers:
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Carrier Model | Notes |
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TE0701 |
| TE0703 | used as reference carrier | TE0705 |
| TE0706 |
| TEBA0841 |
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Additional HW Requirements:
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Additional Hardware | Notes |
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USB Cable for JTAG/UART | Check Carrier Board and Programmer for correct typ | XMOD Programmer | Carrier Board dependent, only if carrier has no own FTDI |
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Content
For general structure and of the reference design, see Project Delivery - Xilinx devices
Design Sources
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Type | Location | Notes |
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Vivado | <design name>/block_design <design name>/constraints <design name>/ip_lib | Vivado Project will be generated by TE Scripts | SDK/HSI | <design name>/sw_lib | Additional Software Template for Vitis and apps_list.csv with settings automatically for Vitis app generation | PetaLinux | <design name>/os/petalinux | PetaLinux template with current configuration |
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Additional Sources
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Prebuilt
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- Template Table:
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File | File-Extension | Description |
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BIF-File | *.bif | File with description to generate Bin-File | BIN-File | *.bin | Flash Configuration File with Boot-Image (Zynq-FPGAs) | BIT-File | *.bit | FPGA (PL Part) Configuration File | DebugProbes-File | *.ltx | Definition File for Vivado/Vivado Labtools Debugging Interface | Debian SD-Image | *.img | Debian Image for SD-Card | Diverse Reports | --- | Report files in different formats | Hardware-Platform-Specification-Files | *.xsa | Exported Vivado Hardware Specification for Vitis and PetaLinux | LabTools Project-File | *.lpr | Vivado Labtools Project File | MCS-File | *.mcs | Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only) | MMI-File | *.mmi | File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only) | OS-Image | *.ub | Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk) | Software-Application-File | *.elf | Software Application for Zynq or MicroBlaze Processor Systems | SREC-File | *.srec | Converted Software Application for MicroBlaze Processor Systems |
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File | File-Extension | Description |
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BIT-File | *.bit | FPGA (PL Part) Configuration File | DebugProbes-File | *. |
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Additional Sources
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Prebuilt
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<table width="100%">
<tr> <th>File </th> <th>File-Extension</th> <th>Description </th> </tr>
<tr> <td>BIF-File </td> <td>*.bif </td> <td>File with description to generate Bin-File </td> </tr>
<tr> <td>BIN-File </td> <td>*.bin </td> <td>Flash Configuration File with Boot-Image (Zynq-FPGAs) </td> </tr>
<tr> <td>BIT-File </td> <td>*.bit </td> <td>FPGA Configuration File </td> </tr>
<tr> <td>DebugProbes-File </td> <td>*.ltx </td> <td>Definition File for Vivado/Vivado Labtools Debugging Interface </td> </tr>
<tr> <td>Debian SD-Image </td> <td>*.img </td> <td>Debian Image for SD-Card </td> </tr>
<tr> <td>Diverse Reports </td> <td> --- </td> <td>Report files in different formats </td> </tr>
<tr> <td>Hardware-Platform-Specification-Files</td> <td>*.hdf </td> <td>Exported Vivado Hardware Specification for SDK/HSI </td> </tr>
<tr> <td>LabTools Project-File </td> <td>*.lpr </td> <td>Vivado Labtools Project File </td> </tr>
<tr> <td>MCS-File </td> <td>*.mcs </td> <td>Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only) </td> </tr>
<tr> <td>MMI-File </td> <td>*.mmi </td> <td>File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only) </td> </tr>
<tr> <td>OS-Image </td> <td>*.ub </td> <td>Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk) </td> </tr>
<tr> <td>Software-Application-File </td> <td>*.elf </td> <td>Software Application for Zynq or MicroBlaze Processor Systems </td> </tr>
<tr> <td>SREC-File </td> <td>*.srec </td> <td>Converted Software Application for MicroBlaze Processor Systems </td> </tr>
</table>
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...
File
...
File-Extension
...
Description
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ltx | Definition File for Vivado/Vivado Labtools Debugging Interface | Diverse Reports | --- | Report files in different formats | Hardware-Platform-Specification-Files | *. |
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...
xsa | Exported Vivado Hardware Specification for |
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...
Vitis and PetaLinux | LabTools Project-File | *.lpr | Vivado Labtools Project File | MCS-File | *.mcs | Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only) | MMI-File | *.mmi | File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only) | OS-Image | *.ub | Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk) | Software-Application-File | *.elf | Software Application for Zynq or MicroBlaze Processor Systems | SREC-File | *.srec | Converted Software Application for MicroBlaze Processor Systems |
|
Download
Reference Design is only usable with the specified Vivado/SDK/PetaLinux/SDx version. Do never use different Versions of Xilinx Software for the same Project.
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- Important set new Vivado version link on every Design update of new vivado version!
- Set Link to download folder (Remove ../de/.. ../en/.. from url) for example
|
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Add correct pathen//TE080320171/Starterkit
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Reference Design is available on:
Design Flow
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Notes :
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Basic Design Steps
Add/ Remove project specific
--> |
Note |
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Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first lunch. |
...
TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/SDK GUI. For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality
- _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
- Press 0 and enter for minimum setupto start "Module Selection Guide"
- (optional Win OS) Generate Virtual Drive or use short directory for the reference design (for example x:\<design name>)
- Create Project (follow instruction of the product selection guide), settings file will be configured automatically during this process
- optional for manual changes) Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
Note: Select correct one, see TE Board Part Files
- Create HDF XSA and export to prebuilt folder
- Run on Vivado TCL: TE::hw_build_design -export_prebuilt
Note: Script generate design and export files into \prebuilt\hardware\<short dir>. Use GUI is the same, except file export to prebuilt folder
- Create Linux (uboot.elf and image.ub) with exported HDFXSA
- HDF XSA is exported to "prebuilt\hardware\<short name>"
Note: HW Export from Vivado GUI create another path as default workspace. - Create Linux images on VM, see PetaLinux KICKstart
- Use TE Template from /os/petalinux
Note: run init_config.sh before you start petalinux config. This will set correct temporary path variable.
Important Note: Select correct Flash partition offset on petalinux-config: Subsystem Auto HW Settings → Flash Settings, FPGA+Boot+bootenv=0x900000 (increase automatically generate Boot partition)
- Add Linux files (uboot.elf and image.ub) to prebuilt folder
- "prebuilt\os\petalinux\default" or "prebuilt\os\petalinux\<short name>"
Notes: Scripts select "prebuilt\os\petalinux\<short name>", if exist, otherwise "prebuilt\os\petalinux\default"
- Generate UBoot SREC:
- Create SDK Project with TE Scripts on Vivado TCL: TE::sw_run_sdk
- Create "uboot-dummy" application
Note: Use Hello World Example - Copy u-boot.elf into "\workspace\sdk\uboot-dummy\Debug"
- Open "uboot-dummy" properties → C/C++ Build → Settings and go into Build Steps Tap.
- Add to Post-build steps: mb-objcopy -O srec u-boot.elf u-boot.srec
- Press Apply or regenerate project
Note: SREC is generated on "\workspace\sdk\uboot-dummy\Debug\u-boot.srec"
- Generate Programming Files with HSI/SDK
- Run on Vivado TCL: TE::sw_run_hsi
Note: Scripts generate applications and bootable files, which are defined in "sw_lib\apps_list.csv" - (alternative) Start SDK with Vivado GUI or start with TE Scripts on Vivado TCL: TE::sw_run_sdk
Note: See SDK Projects
- Copy "\prebuilt\software\<short name>\srec_spi_bootloader.elf" into "\firmware\microblaze_0\"
- (optional) Copy "\\workspace\sdk\scu\Release\scu.elf" into "\firmware\microblaze_mcs_0\"
- Regenerate Vivado Project or Update Bitfile only with "srec_spi_bootloader.elf" and "scu.elf"
Launch
Programming
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Description of Block Design, Constrains...
BD Pictures from Export...
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Note |
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Check Module and Carrier TRMs for proper HW configuration before you try any design. |
Xilinx documentation for programming and debugging: Vivado/SDK/SDSoC-Xilinx Software Programming and Debugging
QSPI
- Connect JTAG and power on PCB
- (if not done) Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd" or open with "vivado_open_project_guimode.cmd", if generated.
- Type on Vivado Console: TE::pr_program_flash_mcsfile -swapp u-boot
Note: Alternative use SDK or setup Flash on Vivado manually - Reboot (if not done automatically)
SD
Not used on this Example.
JTAG
Not used on this Example.
Usage
- Prepare HW like described on section Programming
- Connect UART USB (most cases same as JTAG)
- Power on PCB
Note: FPGA Loads Bitfile from Flash, SREC Bootloader from Bitfile Firmware loads U-Boot into DDR (This takes a while), U-boot loads Linux from QSPI Flash into DDR
Boot process takes a while, please wait.
Image Removed
Linux
Note: Linux boot process is slower on Microblaze.
- Open Serial Console (e.g. putty)
- Speed: 9600
- COM Port: Win OS, see device manager, Linux OS see dmesg |grep tty (UART is *USB1)
- Linux Console:
Note: Wait until Linux boot finished For Linux Login use:
- User Name: root
- Password: root
- You can use Linux shell now.
- ETH0 works with udhcpc
Vivado HW Manager:
- Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder).
- User LED Control
- ETH Control and Link Status
- MicroBlaze Reset Status
Image Removed
System Design - Vivado
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Block Design
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Constrains
Basic module constrains
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language | ruby |
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title | _i_bitgen_common.xdc |
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set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property BITSTREAM.CONFIG.CONFIGRATE 66 [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property CFGBVS VCCO [current_design]
set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design]
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
set_property BITSTREAM.CONFIG.M1PIN PULLNONE [current_design]
set_property BITSTREAM.CONFIG.M2PIN PULLNONE [current_design]
set_property BITSTREAM.CONFIG.M0PIN PULLNONE [current_design]
set_property BITSTREAM.CONFIG.USR_ACCESS TIMESTAMP [current_design] |
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language | ruby |
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title | _i_bitgen.xdc |
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set_property BITSTREAM.CONFIG.UNUSEDPIN PULLDOWN [current_design] |
Design specific constrain
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linenumbers | true |
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collapse | true |
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set_property PACKAGE_PIN G3 [get_ports {LED_RED_XA_SC[0]}]
set_property IOSTANDARD LVCMOS15 [get_ports {LED_RED_XA_SC[0]}]
set_property PACKAGE_PIN T10 [get_ports {ETH2_LINK_LED[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {ETH2_LINK_LED[0]}]
set_property PACKAGE_PIN V15 [get_ports {ETH1_LINK_LED[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {ETH1_LINK_LED[0]}]
set_property PACKAGE_PIN T18 [get_ports {ETH1_PD_N[0]}]
set_property PACKAGE_PIN D10 [get_ports {ETH2_PD_N[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {ETH2_PD_N[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {ETH1_PD_N[0]}]
set_property PACKAGE_PIN L15 [get_ports {LED_RED_D3[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LED_RED_D3[0]}] |
Software Design - SDK/HSI
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optional chapter
separate sections for different apps
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For SDK project creation, follow instructions from:
SDK Projects
Application
SREC SPI BootLoader
Add some Console outputs and changed Bootloader Read Address.
Template location: \sw_lib\sw_apps\srec_spi_bootloader
xilisf_v5_9
Changed default Flash Typ to 5.
Template location: \sw_lib\sw_services
U-Boot
U-Boot.elf is generated with PetaLinux. SDK/HSI is used to generate u-boot.srec. Vivado to generate *.mcs
Software Design - PetaLinux
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Description currently not available.
Config
- Set kernel flash Address to 0x900000 and Kernel size to 0xA00000:
(--> Subsystem Auto Hardware Settings --> Flash Settings)
- SUBSYSTEM_FLASH_AXI_QUAD_SPI_0_BANKLESS_PART0_SIZE = 0x400000
- SUBSYSTEM_FLASH_AXI_QUAD_SPI_0_BANKLESS_PART1_SIZE = 0x4E0000
- SUBSYSTEM_FLASH_AXI_QUAD_SPI_0_BANKLESS_PART2_SIZE = 0x20000
- SUBSYSTEM_FLASH_AXI_QUAD_SPI_0_BANKLESS_PART3_SIZE = 0xA00000
U-Boot
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#include <configs/platform-auto.h>
#define CONFIG_SYS_BOOTM_LEN 0xF000000
#undef CONFIG_PHY_XILINX
#undef XILINX_EMACLITE_BASEADDR 0x40E00000
#undef CONFIG_MII
#undef CONFIG_PHY_GIGE
#undef CONFIG_PHY_MARVELL
#undef CONFIG_PHY_NATSEMI
#undef CONFIG_NET_MULTI
#undef CONFIG_BOOTP_MAY_FAIL
#undef CONFIG_NETCONSOLE 1
#undef CONFIG_SERVERIP 192.168.150.117
#undef CONFIG_IPADDR
/* PREBOOT */
#define CONFIG_PREBOOT "echo U-BOOT for petalinux;setenv preboot; echo; "
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Device Tree
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/include/ "system-conf.dtsi"
/ {
};
/* ETH PHY */
&axi_ethernetlite_0 {
phy-handle = <&phy0>;
mdio {
#address-cells = <1>;
#size-cells = <0>;
phy0: phy@0 {
device_type = "ethernet-phy";
reg = <1>;
};
};
};
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Kernel
No changes.
Rootfs
No changes.
Applications
No changes.
Additional Software
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Add Description for other Software, for example SI CLK Builder ...
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Appx. A: Change History and Legal Notices
Document Change History
To get content of older revision got to "Change History" of this page and select older document revision number.
- Important Note: Select correct Flash partition offset on petalinux-config: Subsystem Auto HW Settings → Flash Settings, FPGA+Boot+bootenv=0x900000 (increase automatically generate Boot partition), increase image size to A:, see TE0710 Test Board#Config
- Add Linux files (uboot.elf and image.ub) to prebuilt folder
"prebuilt\os\petalinux\<ddr size>" or "prebuilt\os\petalinux\<short name>"
Notes: Scripts select "prebuilt\os\petalinux\<short name>", if exist, otherwise "prebuilt\os\petalinux\<DDR size>" of the selected device
- Generate Programming Files with Vitis
- Run on Vivado TCL: TE::sw_run_vitis -all
Note: Depending of PC performance this can take several minutes. Scripts generate applications and bootable files, which are defined in "sw_lib\apps_list.csv" and open Vitis - (alternative) Start Vitis with Vivado GUI or start with TE Scripts on Vivado TCL: TE::sw_run_vitis
Note: TCL scripts generate also platform project, this must be done manuelly in case GUI is used. See Vitis
- Copy "\prebuilt\software\<short name>\srec_spi_bootloader.elf" into "\firmware\microblaze_0\"
- Regenerate Vivado Project or Update Bitfile only with "srec_spi_bootloader.elf"
Launch
Programming
Page properties |
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Note: - Programming and Startup procedure
|
Note |
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Check Module and Carrier TRMs for proper HW configuration before you try any design. |
Xilinx documentation for programming and debugging: Vivado/SDK/SDSoC-Xilinx Software Programming and Debugging
Get prebuilt boot binaries
- _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell
- Press 0 and enter to start "Module Selection Guide"
- Select assembly version
- Validate selection
- Select Create and open delivery binary folder
Note: Folder (<project foler>/_binaries_<Artikel Name>) with subfolder (boot_<app name>) for different applications will be generated
QSPI
- Connect JTAG and power on PCB
- (if not done) Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd" or open with "vivado_open_project_guimode.cmd", if generated.
- Type on Vivado Console: TE::pr_program_flash -swapp u-boot
Note: Alternative use SDK or setup Flash on Vivado manually - Reboot (if not done automatically)
SD
Not used on this Example.
JTAG
Not used on this Example.
Usage
- Prepare HW like described on section 50856429
- Connect UART USB (most cases same as JTAG)
- Power on PCB
Note: FPGA Loads Bitfile from Flash, SREC Bootloader from Bitfile Firmware loads U-Boot into DDR (This takes a while), U-boot loads Linux from QSPI Flash into DDR
Boot process takes a while, please wait.
Image Added
Linux
Note: Linux boot process is slower on Microblaze.
- Open Serial Console (e.g. putty)
- Speed: 9600
- COM Port: Win OS, see device manager, Linux OS see dmesg |grep tty (UART is *USB1)
- Linux Console:
Note: Wait until Linux boot finished For Linux Login use:
- User Name: root
- Password: root
- You can use Linux shell now.
- ETH0 works with udhcpc
Vivado HW Manager:
- Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder).
- Control:
- User LED Control
- ETH Power Down
- Monitoring
- ETH Link Status
- MicroBlaze Reset Status
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System Design - Vivado
Block Design
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title | Block Design PCB REV02 |
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Constrains
Basic module constrains
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language | ruby |
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title | _i_bitgen_common.xdc |
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set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property BITSTREAM.CONFIG.CONFIGRATE 66 [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property CFGBVS VCCO [current_design]
set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design]
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
set_property BITSTREAM.CONFIG.M1PIN PULLNONE [current_design]
set_property BITSTREAM.CONFIG.M2PIN PULLNONE [current_design]
set_property BITSTREAM.CONFIG.M0PIN PULLNONE [current_design]
set_property BITSTREAM.CONFIG.USR_ACCESS TIMESTAMP [current_design] |
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language | ruby |
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title | _i_bitgen.xdc |
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set_property BITSTREAM.CONFIG.UNUSEDPIN PULLDOWN [current_design] |
Design specific constrain
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set_property PACKAGE_PIN G3 [get_ports {LED_RED_XA_SC[0]}]
set_property IOSTANDARD LVCMOS15 [get_ports {LED_RED_XA_SC[0]}]
set_property PACKAGE_PIN T10 [get_ports {ETH2_LINK_LED[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {ETH2_LINK_LED[0]}]
set_property PACKAGE_PIN V15 [get_ports {ETH1_LINK_LED[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {ETH1_LINK_LED[0]}]
set_property PACKAGE_PIN T18 [get_ports {ETH1_PD_N[0]}]
set_property PACKAGE_PIN D10 [get_ports {ETH2_PD_N[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {ETH2_PD_N[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {ETH1_PD_N[0]}]
set_property PACKAGE_PIN L15 [get_ports {LED_RED_D3[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LED_RED_D3[0]}] |
Software Design - Vitis
For SDK project creation, follow instructions from:
Vitis
Application
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---------------------------------------------------------- FPGA Example scuMCS Firmware to configure SI5338 and Reset System. srec_spi_bootloaderTE modified 2019.2 SREC Bootloader to load app or second bootloader from flash into DDR Descriptions: - Modified Files: blconfig.h, bootloader.c
- Changes:
- Add some console outputs and changed bootloader read address.
- Add bugfix for 2018.2 qspi flash
xilisf_v5_11TE modified 2019.2 xilisf_v5_11 - Changed default Flash type to 5.
---------------------------------------------------------- Zynq Example: zynq_fsblTE modified 2019.2 FSBL General: Module Specific: - Add Files: all TE Files start with te_*
- READ MAC from EEPROM and make Address accessible by UBOOT (need copy defines on uboot platform-top.h)
- CPLD access
- Read CPLD Firmware and SoC Type
- Configure Marvell PHY
zynq_fsbl_flashTE modified 2019.2 FSBL General: - Modified Files: main.c
- General Changes:
- Display FSBL Banner
- Set FSBL Boot Mode to JTAG
- Disable Memory initialisation
ZynqMP Example: ---------------------------------------------------------- zynqmp_fsblTE modified 2019.2 FSBL General: - Modified Files: xfsbl_main.c, xfsbl_hooks.h/.c, xfsbl_board.h/.c(search for 'TE Mod' on source code)
- Add Files: te_xfsbl_hooks.h/.c (for hooks and board)\n\
- General Changes:
- Display FSBL Banner and Device Name
Module Specific: - Add Files: all TE Files start with te_*
- Si5338 Configuration
- ETH+OTG Reset over MIO
zynqmp_fsbl_flashTE modified 2019.2 FSBL General: - Modified Files: xfsbl_initialisation.c, xfsbl_hw.h, xfsbl_handoff.c, xfsbl_main.c
- General Changes:
- Display FSBL Banner
- Set FSBL Boot Mode to JTAG
- Disable Memory initialisation
zynqmp_pmufwXilinx default PMU firmware. ---------------------------------------------------------- General Example: hello_te0820Hello TE0820 is a Xilinx Hello World example as endless loop instead of one console output. u-bootU-Boot.elf is generated with PetaLinux. SDK/HSI is used to generate Boot.bin. |
srec_spi_bootloader
TE modified 2019.2 SREC
Bootloader to load app or second bootloader from flash into DDR
Descriptions:
- Modified Files: blconfig.h, bootloader.c
- Changes:
- Add some console outputs and changed bootloader read address.
- Add bugfix for 2018.2 qspi flash (some reinitialisation)
xilisf_v5_14
TE modified 2019.2 xilisf_v5_14
- Changed default Flash type to 5.
u-boot
U-Boot.elf is generated with PetaLinux. SDK/HSI is used to generate u-boot.srec. Vivado to generate *.mcs
Software Design - PetaLinux
Description currently not available.
Config
Start with petalinux-config or petalinux-config --get-hw-description
Changes:
- SUBSYSTEM_FLASH_AXI_QUAD_SPI_0_BANKLESS_PART0_SIZE = 0x5E0000
- SUBSYSTEM_FLASH_AXI_QUAD_SPI_0_BANKLESS_PART1_SIZE = 0x300000
- SUBSYSTEM_FLASH_AXI_QUAD_SPI_0_BANKLESS_PART2_SIZE = 0x20000
- SUBSYSTEM_FLASH_AXI_QUAD_SPI_0_BANKLESS_PART3_SIZE = 0xA00000
- (Set kernel flash Address to 0x900000 and Kernel size to 0xA00000)
U-Boot
Start with petalinux-config -c u-boot
Changes:
- CONFIG_ENV_IS_NOWHERE=y
- # CONFIG_ENV_IS_IN_SPI_FLASH is not set
- # CONFIG_PHY_ATHEROS is not set
- # CONFIG_PHY_BROADCOM is not set
- # CONFIG_PHY_DAVICOM is not set
- # CONFIG_PHY_LXT is not set
- # CONFIG_PHY_MICREL_KSZ90X1 is not set
- # CONFIG_PHY_MICREL is not set
- # CONFIG_PHY_NATSEMI is not set
- # CONFIG_PHY_REALTEK is not set
- CONFIG_RGMII=y
Change platform-top.h:
Device Tree
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/include/ "system-conf.dtsi"
/ {
};
/* QSPI PHY */
&axi_quad_spi_0 {
#address-cells = <1>;
#size-cells = <0>;
flash0: flash@0 {
compatible = "jedec,spi-nor";
spi-tx-bus-width=<1>;
spi-rx-bus-width=<4>;
reg = <0x0>;
#address-cells = <1>;
#size-cells = <1>;
spi-max-frequency = <25000000>;
};
};
/* ETH PHY */
&axi_ethernetlite_0 {
phy-handle = <&phy0>;
mdio {
#address-cells = <1>;
#size-cells = <0>;
phy0: phy@0 {
device_type = "ethernet-phy";
reg = <1>;
};
};
};
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Kernel
Start with petalinux-config -c kernel
Changes:
Rootfs
Start with petalinux-config -c rootfs
Changes:
- # CONFIG_dropbear is not set
- # CONFIG_dropbear-dev is not set
- # CONFIG_dropbear-dbg is not set
- # CONFIG_packagegroup-core-ssh-dropbear is not set
- # CONFIG_packagegroup-core-ssh-dropbear-dev is not set
- # CONFIG_packagegroup-core-ssh-dropbear-dbg is not set
- # CONFIG_imagefeature-ssh-server-dropbear is not set
Applications
No changes.
Additional Software
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Note:
- Add description for other Software, for example SI CLK Builder ...
- SI5338 and SI5345 also Link to:
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Appx. A: Change History and Legal Notices
Document Change History
To get content of older revision got to "Change History" of this page and select older document revision number.
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| - Release 2019.2
- Docu update
| 2019-03-29 | v.4 | John Hartfiel |
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Legal Notices
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| IN:Legal Notices |
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| IN:Legal Notices |
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