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Additional HardwareNotes
USB Cable for JTAG/UARTCheck Carrier Board and Programmer for correct type
XMOD ProgrammerCarrier Board dependent, only if carrier has no own FTDI
Heat sinkIt's recommended to use heat sink for this design

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For general structure and of the reference design, see Project Delivery - AMD devices

Design Sources

TypeLocationNotes
Vivado<design name>/block_design
<design name>/constraints
<design name>/ip_lib
<design name>/firmware
Vivado Project will be generated by TE Scripts
SDK/HSI<design name>/sw_libAdditional Software Template for SDK/HSI and apps_list.csv with settings for HSI
PetaLinux<design name>/os/petalinuxPetaLinux template with current configuration

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Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.

See also:Vivado/SDK/SDSoCAMD Development Tools#XilinxSoftware-BasicUserGuides

The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.

TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/SDK GUI.  For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality


  1. _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
  2. Press 0 and enter for minimum setup
  3. (optional Win OS) Generate Virtual Drive or use short directory  for the reference design (for example x:\<design name>)
  4. Create Project
    1. Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
      Note: Select correct one, see TE Board Part Files
  5. Create HDF and export to prebuilt folder
    1. Run on Vivado TCL: TE::hw_build_design -export_prebuilt
      Note: Script generate design and export files into \prebuilt\hardware\<short dir>. Use GUI is the same, except file export to prebuilt folder
  6. Generate MCS Firmware (optional):
    1. Create SDK Project with TE Scripts on Vivado TCL: TE::sw_run_sdk
    2. Create "SCU" application
      Note: Select MCS Microblaze and SCU Application
    3. Select Release Built
    4. Regenerate App
  7. (optional) Copy "\\workspace\sdk\scu\Release\scu.elf" into  "\firmware\microblaze_mcs_0\"
  8. Regenerate Vivado Project or Update Bitfile only with "scu.elf"

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Xilinx documentation for programming and debugging: Vivado/SDK/SDSoC-Xilinx Software Programming and Debugging

QSPI

  1. Connect JTAG and power on PCB
  2. (if not done) Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd" or open with "vivado_open_project_guimode.cmd", if generated.
  3. Type on Vivado Console: TE::pr_program_flash_mcsfile -swapp u-boot
    Note: Alternative use SDK or setup Flash on Vivado manually
  4. Reboot (if not done automatically)

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  1. Open Vivado HW-Manager 
  2. "Refresh device" is needed after Bitfile programming, because MCS reconfigure SI5338 and enables IBERT a little bit later.
    1. loopback depends on TEB0841 Revision an connection

IBERTComponent NameNet NameTEB0841
X0Y0115-0MGT4loop back RX/TX. Note: N.C. on TEB0841-01, use  internal loopback
X0Y1115-1MGT5loopback over SD Pin header possible
X0Y2115-2MGT6loop back RX/TX
X0Y3115-3MGT7loop back RX/TX
X0Y4116-0MGT0loop back RX/TX
X0Y5116-1MGT1loop back RX/TX
X0Y6116-2MGT2loop back RX/TX
X0Y7116-3MGT3loopback over sfp possible

System Design - Vivado

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DateDocument RevisionAuthorsDescription

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  • description update

v.2John Hartfiel
  • Release 2017.4
2018-04-18v.1

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  • Initial release

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