Page History
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| Issues | Description | Workaround | To be fixed version | ||||
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| For PCB REV01 only: CLK1B is not available on | addtional clk is not connected on PCB | use other internal generated CLK, maybe mor effort is needed to get ETH running | |||||
SREC SPI BootLoader default Offset | Default load offset is set to 0x400000 | Change manually on SDK to 0x5E0000 | next update | Timing fails for fmeter IP | Timing ignore constrains does not work for some signals. | This can be ignored | --- |
Requirements
Software
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<!-- Add needed external Software --> |
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- Set kernel flash Address to 0x900000 and Kernel size to 0xA00000:
(--> Subsystem Auto Hardware Settings --> Flash Settings)- SUBSYSTEM_FLASH_AXI_QUAD_SPI_0_BANKLESS_PART0_SIZE = 0x4000000x5E0000
- SUBSYSTEM_FLASH_AXI_QUAD_SPI_0_BANKLESS_PART1_SIZE = 0x4E00000x300000
- SUBSYSTEM_FLASH_AXI_QUAD_SPI_0_BANKLESS_PART2_SIZE = 0x20000
- SUBSYSTEM_FLASH_AXI_QUAD_SPI_0_BANKLESS_PART3_SIZE = 0xA00000
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| v.23 | John Hartfiel | Design Update | |||||||||||||||||||||||
| v.22 | John Hartfiel |
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| 2018-02-13 | v.19 | John Hartfiel |
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| 2018-01-08 | v.16 | John Hartfiel |
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| 2017-12-15 | v.15 | John Hartfiel |
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| 2017-11-07 | v.11 | John Hartfiel |
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| 2017-10-06 | v.10 | John Hartfiel |
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| 2017-10-05 | v.8 | John Hartfiel |
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| 2017-09-11 | v.1 |
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