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DateVivadoProject BuiltAuthorsDescription
2018-06-212017.4

TE0841-test_board_noprebuilt-vivado_2017.4-build_11_20180621164459.zip
TE0841-test_board-vivado_2017.4-build_11_20180621164432.zip

John Hartfiel
  • REV02 Board parts
  • new SI5338 configuration (default REV02)
  • change xilisf_v5_9 for N25Q512A11G1240E support
  • Some changes on block design
2018-05-152017.4TE0841-test_board_noprebuilt-vivado_2017.4-build_08_20180515144542.zip
TE0841-test_board-vivado_2017.4-build_08_20180515144523.zip		John Hartfiel
  • initial release

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Module ModelBoard Part Short NamePCB Revision SupportDDRQSPI FlashOthersNotes
TE0841-01-035-1C 01_35_1cREV012x 512MB DDR432MB---
TE0841-01-035-1I01_35_1iREV012x 512MB DDR432MB---
TE0841-01-035-2I01_35_2iREV012x 512MB DDR432MB---
TE0841-01-040-1C01_40_1cREV012x 512MB DDR432MB---
TE0841-01-040-1I01_40_1iREV012x 512MB DDR432MB---
TE0841-01-040-2I01_40_2iREV012x 512MB DDR432MB---
TE0841-02-035-1C02_35_1cREV022x 1GB DDR464MB---
TE0841-02-035-1I02_35_1iREV022x 1GB DDR464MB---
TE0841-02-035-2I02_35_2iREV022x 1GB DDR464MB---
TE0841-02-040-1C02_40_1c-02-040-1C02_40_1cREV022x 1GB DDR464MB---
TE0841-02-040-1I02_40_1iREV022x 1GB DDR464MB---
TE0841-02-040-1IL02_40_1iREV022x 1GB DDR464MBlow profile B2B connector

Design supports following carriers:

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  1. Speed: 9600
  2. COM Port: Win OS, see device manager, Linux OS see  dmesg |grep tty  (UART is *USB1)

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Vivado HW Manager: 

  1. Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder).
    1. Set radix from VIO signals (fm_si...) to unsigned integer.
      Note: Frequency Counter is inaccurate and displayed unit is Hz
    2. SI will be configured with MCS firmware, default all off on PCB REV01,  PCB REV02 SI5338 will be preconfigured.
    3. LED control via VIO
    4. MGT CLK Freq can be changed over BUFG_GT control signals divider
    5. MCS Reset possible via VIO
    6. MIG Reset is possible over VIO
    7. MCS can be disabled over VIO (For PCB REV01 MCS is enabled, fpr PCB REV02 MCS is disabled by default VIO)

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System Design - Vivado

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Description of Block Design, Constrains...
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Block Design

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Constrains

Basic module constrains

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Code Block
languageruby
title_i_fm.xdc
linenumberstrue
set_false_path -from [get_clocks {msys_i/util_ds_buf_5/U0/BUFG_GT_O[0]}] -to [get_clocks -of_objects [get_pins msys_i/clk_wiz_0/inst/mmcme3_adv_inst/CLKOUT0]]
set_false_path -from [get_clocks {msys_i/util_ds_buf_6/U0/BUFG_GT_O[0]}] -to [get_clocks -of_objects [get_pins msys_i/clk_wiz_0/inst/mmcme3_adv_inst/CLKOUT0]]
set_false_path -from [get_clocks -of_objects [get_pins msys_i/clk_wiz_0/inst/mmcme3_adv_inst/CLKOUT0]] -to [get_clocks {msys_i/util_ds_buf_6/U0/BUFG_GT_O[0]}]
set_false_path -from [get_clocks -of_objects [get_pins msys_i/clk_wiz_0/inst/mmcme3_adv_inst/CLKOUT0]] -to [get_clocks {msys_i/util_ds_buf_5/U0/BUFG_GT_O[0]}]

set_false_path -from [get_clocks -of_objects [get_pins msys_i/clk_wiz_0/inst/mmcme3_adv_inst/CLKOUT0]] -to [get_clocks {msys_i/util_ds_buf_1/U0/IBUF_OUT[0]}]
set_false_path -from [get_clocks -of_objects [get_pins msys_i/clk_wiz_0/inst/mmcme3_adv_inst/CLKOUT0]] -to]] -to [get_clocks {msys_i/util_ds_buf_4/U0/IBUF_OUT[0]}]
set_false_path -from [get_clocks {msys_i/util_ds_buf_0/U0/IBUF_OUT[0]}] -to [get_clocks -of_objects [get_clockspins {msys_i/utilclk_dswiz_buf_40/U0inst/IBUF_OUT[0]}mmcme3_adv_inst/CLKOUT0]]
set_false_path -from [get_clocks {msys_i/util_ds_buf_1/U0/IBUF_OUT[0]}] -to [get_clocks -of_objects [get_pins msys_i/clk_wiz_0/inst/mmcme3_adv_inst/CLKOUT0]]
set_false_path -from [get_clocks {msys_i/util_ds_buf_4/U0/IBUF_OUT[0]}] -to [get_clocks -of_objects [get_pins msys_i/clk_wiz_0/inst/mmcme3_adv_inst/CLKOUT0]]

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Modified Xilinx SREC Bootloader. Changes: Correct flash typ and SRec Start address, some additional console outputs, see source code

Changed xilisf_v5_9 to support N25Q512_1V8 for SREC (changes on xilisf.c and xilisf_intelstm.h)

Template location: \sw_lib\sw_apps\srec_spi_bootloader

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DateDocument RevisionAuthorsDescription

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prefixv.



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  • Design update
  • new assembly variants (PCB REV02)

v.3John Hartfiel
  • Release 2017.4
2018-04-16v.1

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  • Initial release

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