Versions Compared

Old Version 4

changes.mady.by.user John Hartfiel

Saved on

compared with

New Version 5

changes.mady.by.user John Hartfiel

Saved on

Key

  • This line was added.
  • This line was removed.
  • Formatting was changed.

...

  • Power Management
  • Reset
  • UART

  • IO Expender(RGPIO)

Firmware Revision and supported PCB Revision

...

Name / opt. VHD NameDirectionPinBank PowerDescription
BM2/MIO4   / BM2_MIO4outB353.3VBoot Mode Pin to FPGA (SD or QSPI)
BOOTMODE   outB323.3VB2B UART from MIO15
MIO15     CONFIGX    CONFIGX  inB333.3VB2B UART to MIO14
CPLD_GPIO0 
A33.3VB2B / currently_not_used
CPLD_GPIO1 
B13.3VB2B / currently_not_used
CPLD_GPIO2 
A13.3VB2B / currently_not_used
CPLD_GPIO3 
A23.3V/ currently_not_usedB2B, used for Boot Mode
DONE DONE       inA353.3VFPGA Done signal/ currently_not_used
EN_1V      1VoutB33.3Vdisable/enable module power 1V and all other related voltages/ currently_not_used
EXT_IO1    IO1inoutA33EXT_IO_VCC/ currently_not_usedB2B, RGPIO /
EXT_IO10   IO10 
B22EXT_IO_VCC/ currently_not_usedB2B, RGPIO
EXT_IO11   IO11 
A24EXT_IO_VCC/ currently_not_usedB2B, RGPIO
EXT_IO12   IO12 
A23EXT_IO_VCC/ currently_not_usedB2B, RGPIO
EXT_IO13   IO13 
B21EXT_IO_VCC/ currently_not_usedB2B, RGPIO
EXT_IO14   IO14 
A28EXT_IO_VCC/ currently_not_usedB2B, RGPIO
EXT_IO15   IO15 
B18EXT_IO_VCC/ currently_not_usedB2B, RGPIO
EXT_IO16   IO16 
A22EXT_IO_VCC/ currently_not_usedB2B, RGPIO
EXT_IO17   IO17 
B8EXT_IO_VCC/ currently_not_usedB2B, RGPIO
EXT_IO18   IO18 
A9EXT_IO_VCC/ currently_not_usedB2B, RGPIO
EXT_IO19   IO19 
A20EXT_IO_VCC/ currently_not_usedB2B, RGPIO
EXT_IO2    IO2
B24EXT_IO_VCC/ currently_not_usedB2B, RGPIO
EXT_IO20   IO20 
B14EXT_IO_VCC/ currently_not_usedB2B, RGPIO
EXT_IO21   IO21 
A8EXT_IO_VCC/ currently_not_usedB2B, RGPIO
EXT_IO22   IO22 
B7EXT_IO_VCC/ currently_not_usedB2B, RGPIO
EXT_IO23   IO23 
B13EXT_IO_VCC/ currently_not_usedB2B, RGPIO
EXT_IO24   IO24 
A18EXT_IO_VCC/ currently_not_usedB2B, RGPIO
EXT_IO25   IO25 
A5EXT_IO_VCC/ currently_not_usedB2B, RGPIO
EXT_IO26   IO26 
B4EXT_IO_VCC/ currently_not_usedB2B, RGPIO
EXT_IO27   IO27 
A13EXT_IO_VCC/ currently_not_usedB2B, RGPIO
EXT_IO28   IO28 
A17EXT_IO_VCC/ currently_not_usedB2B, RGPIO
EXT_IO29   IO29 
A6EXT_IO_VCC/ currently_not_usedB2B, RGPIO
EXT_IO3    IO3
A27EXT_IO_VCC/ currently_not_usedB2B, RGPIO
EXT_IO30   IO30 
B5EXT_IO_VCC/ currently_not_usedB2B, RGPIO
EXT_IO31   IO31 
B12EXT_IO_VCC/ currently_not_usedB2B, RGPIO
EXT_IO32   IO32 
A16EXT_IO_VCC/ currently_not_usedB2B, RGPIO
EXT_IO33   IO33 
A7EXT_IO_VCC/ currently_not_usedB2B, RGPIO
EXT_IO34   IO34 
B9EXT_IO_VCC/ currently_not_usedB2B, RGPIO
EXT_IO35   IO35 
A15EXT_IO_VCC/ currently_not_usedB2B, RGPIO
EXT_IO36   IO36 
B15EXT_IO_VCC/ currently_not_usedB2B, RGPIO
EXT_IO37   IO37 
A11EXT_IO_VCC/ currently_not_usedB2B, RGPIO
EXT_IO38   IO38 
A12EXT_IO_VCC/ currently_not_usedB2B, RGPIO
EXT_IO39   IO39 
B16EXT_IO_VCC/ currently_not_usedB2B, RGPIO
EXT_IO4    IO4
B20EXT_IO_VCC/ currently_not_usedB2B, RGPIO
EXT_IO40   IO40 
A21EXT_IO_VCC/ currently_not_usedB2B, RGPIO
EXT_IO5    IO5
A31EXT_IO_VCC/ currently_not_usedB2B, RGPIO
EXT_IO6    IO6
B23EXT_IO_VCC/ currently_not_usedB2B, RGPIO
EXT_IO7    IO7
A26EXT_IO_VCC/ currently_not_usedB2B, RGPIO
EXT_IO8    IO8
A25EXT_IO_VCC/ currently_not_usedB2B, RGPIO
EXT_IO9    IO9
A30EXT_IO_VCC/ currently_not_usedB2B, RGPIO
FPGA_CPLD1 
A403.3VFPGA AB18/ currently_not_used
FPGA_CPLD2 
B283.3VFPGA AB20/ currently_not_used
FPGA_CPLD3 
A383.3VFPGA AD20/ currently_not_used
FPGA_CPLD4 
A363.3VFPGA AE20 goes to LED2/ currently_not_used
JTAGENBinB303.3VEnable CPLD JTAG access, otherwiste M_... is used as GPIO/ currently_not_used
LED2outB10EXT_IO_VCCStatus LED / currently_not_usedD1 red
M_TCK      TCKinA453.3VJTAG if JTAGENB is high/ currently_not_used
M_TDI      TDIinA473.3VJTAG if JTAGENB is high/ currently_not_used
M_TDO      TDOoutA483.3VJTAG if JTAGENB is high/ currently_not_used
M_TMS      TMSinB343.3VJTAG if JTAGENB is high/ currently_not_used
MIO14      MIO14outA443.3VUART out to FPGA
MIO15      MIO15inA423.3VUART in from FPGA 
nRST_IN    INinA323.3VReset from B2B to PS_POR / currently_not_used
PG_ALLinA463.3VStatus power
PROG_B     B inB253.3VStatus  Status PROG_B/ currently_not_used
PS_POR     POR inoutA413.3Vopen drain as second reset from nRSR_IN/ currently_not_used


Functional Description

JTAG

Set JTAGENB(J3-136) high to get access to CPLD via JTAG, otherwise CPLD JTAG Pins can be used as GPIO.

Power

EN_1V is set to constant high.

Boot Mode

CPLD_GPIO3 (J2-16) is used to set boot Mode Pin BM2_MIO4. Signal is inverted to be compatible with second XMOD on TEBT0782

J2-16Description
lowSD Boot*
highQSPI (default)

* not supported with TEBT0782

Reset

nRST_IN drive POR_B as open drain.

U27(TPS3106) or nRST_IN can reset Zynq.

UART

MIO8 is connected to CONFIGX.

BOOTMODE is connected to MIO9.

RGPIO (beta)

RGPIO Master is a 32Bit Remote GPIO Interface to talk with FPGA over 3 lanes. System need RGPIO IP on FPGA side.

IO Expender

Currently not implemented.

LED

  • RGPIO CLK is  FPGA_CPLD1 (max 25MHz).
  • Output is FPGA_CPLD2
  • Input is FPGA_CPLD3
RGPIO from FPGAValue
0...19EXT_IO(even numbers), if RGPIO is activated. otherwise EXTIO is high impedance
20...23RGPIO in 20...23
24...27reserved
28...31activation code "1010"
RGPIO to FPGA
0...19EXT_IO(odd numbers)
20...23RGPIO out 20...23
24...27reserved
28...31activation code from FPGA. Must match "1010"


LED

LED2 D1 Red
PriorityBlink SequenceComment
1********PG_ALL, Power problem
2*****oooPROG_B, SoC PROGAM_B down
3****ooooPS_POR, SoC PS_POR_B down
4***oooooDONE, SoC DONE down
5user definedFPGA_CPLD4 connected to LED

Appx. A: Change History and Legal Notices

...

Document Change History

To get content of older revision  revision got to "Change History"   of this page and select older document revision number.

...