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changes.mady.by.user John Hartfiel

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changes.mady.by.user John Hartfiel

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Name / opt. VHD NameDirectionPinBank PowerDescription
BM2/MIO4   / BM2_MIO4outB353.3VBoot Mode Pin to FPGA (SD or QSPI)
BOOTMODE   outB323.3VB2B UART from MIO15
CONFIGX  inB333.3VB2B UART to MIO14
CPLD_GPIO0 
A33.3VB2B / currently_not_used
CPLD_GPIO1 
B13.3VB2B / currently_not_used
CPLD_GPIO2 
A13.3VB2B / currently_not_used
CPLD_GPIO3 inA23.3VB2B, used for Boot Mode
DONE inA353.3VFPGA Done signal
EN_1VoutB33.3Vdisable/enable module power 1V and all other related voltages
EXT_IO1inoutA33EXT_IO_VCCB2B, RGPIO /
EXT_IO10 inoutB22EXT_IO_VCCB2B, RGPIO
EXT_IO11 inoutA24EXT_IO_VCCB2B, RGPIO
EXT_IO12 inoutA23EXT_IO_VCCB2B, RGPIO
EXT_IO13 inoutB21EXT_IO_VCCB2B, RGPIO
EXT_IO14 inoutA28EXT_IO_VCCB2B, RGPIO
EXT_IO15 inoutB18EXT_IO_VCCB2B, RGPIO
EXT_IO16 inoutA22EXT_IO_VCCB2B, RGPIO
EXT_IO17 inoutB8EXT_IO_VCCB2B, RGPIO
EXT_IO18 inoutA9EXT_IO_VCCB2B, RGPIO
EXT_IO19 inoutA20EXT_IO_VCCB2B, RGPIO
EXT_IO2inoutB24EXT_IO_VCCB2B, RGPIO
EXT_IO20 inoutB14EXT_IO_VCCB2B, RGPIO
EXT_IO21 inoutA8EXT_IO_VCCB2B, RGPIO
EXT_IO22 inoutB7EXT_IO_VCCB2B, RGPIO
EXT_IO23 inoutB13EXT_IO_VCCB2B, RGPIO
EXT_IO24 inoutA18EXT_IO_VCCB2B, RGPIO
EXT_IO25 inoutA5EXT_IO_VCCB2B, RGPIO
EXT_IO26 inoutB4EXT_IO_VCCB2B, RGPIO
EXT_IO27 inoutA13EXT_IO_VCCB2B, RGPIO
EXT_IO28 
A17EXT_IO_VCCB2B, RGPIO
EXT_IO29 
A6EXT_IO_VCCB2B, RGPIO
EXT_IO3
A27EXT_IO_VCCB2B, RGPIO
EXT_IO30 
B5EXT_IO_VCCB2B, RGPIO
EXT_IO31 
B12EXT_IO_VCCB2B, RGPIO
EXT_IO32 
A16EXT_IO_VCCB2B, RGPIO
EXT_IO33 
A7EXT_IO_VCCB2B, RGPIO
EXT_IO34 
B9EXT_IO_VCCB2B, RGPIO
EXT_IO35 
A15EXT_IO_VCCB2B, RGPIO
EXT_IO36 
B15EXT_IO_VCCB2B, RGPIO
EXT_IO37 
A11EXT_IO_VCCB2B, RGPIO
EXT_IO38 
A12EXT_IO_VCCB2B, RGPIO
EXT_IO39 
B16EXT_IO_VCCB2B, RGPIO
EXT_IO4
B20EXT_IO_VCCB2B, RGPIO
EXT_IO40 
A21EXT_IO_VCCB2B, RGPIO
EXT_IO5
A31EXT_IO_VCCB2B, RGPIO
EXT_IO6
B23EXT_IO_VCCB2B, RGPIO
EXT_IO7
A26EXT_IO_VCCB2B, RGPIO
EXT_IO8
A25EXT_IO_VCCB2B, RGPIO
EXT_IO9
A30EXT_IO_VCCB2B, RGPIO
FPGA_CPLD1 
A403.3VFPGA AB18/ currently_not_used
FPGA_CPLD2 
B283.3VFPGA AB20/ currently_not_used
FPGA_CPLD3 
A383.3VFPGA AD20/ currently_not_used
FPGA_CPLD4 
A363.3VFPGA AE20 goes to LED2/ currently_not_used
JTAGENBinB303.3VEnable CPLD JTAG access, otherwiste M_... is used as GPIO
LED2outB10EXT_IO_VCCStatus LED D1 red
M_TCKinA453.3VJTAG if JTAGENB is high/ currently_not_used
M_TDIinA473.3VJTAG if JTAGENB is high/ currently_not_used
M_TDOoutA483.3VJTAG if JTAGENB is high/ currently_not_used
M_TMSinB343.3VJTAG if JTAGENB is high/ currently_not_used
MIO14outA443.3VUART out to FPGA
MIO15inA423.3VUART in from FPGA 
nRST_INinA323.3VReset from B2B to PS_POR
PG_ALLinA463.3VStatus power
PROG_B inB253.3VStatus PROG_B/ currently_not_used
PS_POR inoutA413.3Vopen drain as second reset from nRSR_IN/ currently_not_used

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CPLD_GPIO3 (J2-16) is used to set boot Mode Pin BM2_MIO4. Signal is inverted to be compatible with second XMOD on TEBT0782

J2-16Description
lowSD Boot*
highQSPI (default)

* not supported with TEBT0782

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  • RGPIO CLK is  FPGA_CPLD1 (max 25MHz).
  • Output is FPGA_CPLD2
  • Input is FPGA_CPLD3
RGPIO from FPGAValue
0...19EXT_IO(even numbers), if RGPIO is activated. otherwise EXTIO is high impedance
20...23RGPIO in 20...23
24...27reserved
28...31activation code "1010"
RGPIO to FPGA
0...19EXT_IO(odd numbers)
20...23RGPIO out 20...23
24...27reserved
28...31activation code from FPGA. Must match "1010"


LED

LED2 D1 Red
PriorityBlink SequenceComment
1********PG_ALL, Power problem
2*****oooPROG_B, SoC PROGAM_B down
3****ooooPS_POR, SoC PS_POR_B down
4***oooooDONE, SoC DONE down
5user definedFPGA_CPLD4 connected to LED

Appx. A: Change History and Legal Notices

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