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DateVivadoProject BuiltAuthorsDescription
2018-06-05222017.4TE0841-IBERT_noprebuilt-vivado_2017.4-build_11_20180622140813.zip
TE0841-IBERT-vivado_2017.4-build_11_20180622140615.zip
John Hartfiel
  • initial release

Release Notes and Know Issues

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  • REV02 Board parts
  • new SI5338 configuration (default REV02)
  • change xilisf_v5_9 for N25Q512A11G1240E support
  • Some changes on block design
2018-06-052017.4TE0841-IBERT_noprebuilt-vivado_2017.4-build_10_20180605143852.zip
TE0841-IBERT-vivado_2017.4-build_10_20180605143837.zip
John Hartfiel
  • initial release

Release Notes and Know Issues

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IssuesDescriptionWorkaroundTo be fixed version
---------PCB REV01 only: IBERT no CLKPCB REV01 SI5338 is not preprogrammed and SI programming over MCS is disabled by default design and I2C is not connectedLoad test_board bitfile for REV01 and load IBERT design again without power off HW---

Requirements

Software

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Module ModelBoard Part Short NamePCB Revision SupportDDRQSPI FlashOthersNotes
TE0841-01-035-1C 01_35_1cREV012x 512MB DDR432MB---
TE0841-01-035-1I01_35_1iREV012x 512MB DDR432MB---
TE0841-01-035-2I01_35_2iREV012x 512MB DDR432MB---
TE0841-01-040-1C01_40_1cREV012x 512MB DDR432MB---Serial number 512479 up tp 512474  has same 64MB Flash like REV02
TE0841-01-040-1I01_40_1iREV012x 512MB DDR432MB---
TE0841-01-040-2I01_40_2iREV012x 512MB DDR432MB---

Design supports following carriers:

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Additional HW Requirements:

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For general structure and of the reference design, see Project Delivery

Design Sources

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Additional Sources

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Prebuilt

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TE0841-02-035-1C02_35_1cREV022x 1GB DDR464MB---
TE0841-02-035-1I02_35_1iREV022x 1GB DDR464MB---
TE0841-02-035-2I02_35_2iREV022x 1GB DDR464MB---
TE0841-02-040-1C02_40_1cREV022x 1GB DDR464MB---
TE0841-02-040-1I02_40_1iREV022x 1GB DDR464MB---
TE0841-02-040-1IL02_40_1iREV022x 1GB DDR464MBlow profile B2B connector

Design supports following carriers:

Carrier ModelNotes
TEBA0841 used as reference carrier

Additional HW Requirements:

Additional HardwareNotes
USB Cable for JTAG/UARTCheck Carrier Board and Programmer for correct type
XMOD ProgrammerCarrier Board dependent, only if carrier has no own FTDI
Heat sinkIt's recommended to use heat sink for this design

Content

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For general structure and of the reference design, see Project Delivery - Xilinx devices

Design Sources

TypeLocationNotes
Vivado<design name>/block_design
<design name>/constraints
<design name>/ip_lib
<design name>/firmware
Vivado Project will be generated by TE Scripts
SDK/HSI<design name>/sw_libAdditional Software Template for SDK/HSI and apps_list.csv with settings for HSI

Additional Sources

TypeLocationNotes
 SI5338 Project \misc\SI5338

Prebuilt

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<table width="100%">
<tr> <th>File                      </td> <td>*.bif           </td>  <td>File with description to generate Bin-Fileth> <th>File-Extension</th>  <th>Description                                                                              </td>th> </tr>
<tr> <td>BIN<td>BIF-File                             </td> <td>*.binbif         </td>  <td>File <td>Flashwith Configurationdescription Fileto withgenerate BootBin-ImageFile (Zynq-FPGAs)                                    </td> </          </td> </tr>
<tr> <td>BIT<td>BIN-File                             </td> <td>*.bitbin         </td>  <td>FPGA<td>Flash Configuration File with Boot-Image (Zynq-FPGAs)                                    </td> </tr>
<tr> <td>BIT-File                             </td> </tr>
<tr> <td>DebugProbes-File<td>*.bit         </td>  <td>FPGA Configuration File          </td> <td>*.ltx         </td>  <td>Definition File for Vivado/Vivado Labtools Debugging Interface                                          </td> </tr>
<tr> <td>Debian SD<td>DebugProbes-ImageFile                      </td> <td>*.imgltx         </td>  <td>Debian<td>Definition ImageFile for SD-Card  Vivado/Vivado Labtools Debugging Interface                           </td> </tr>
<tr> <td>Debian SD-Image                      </td> <td>*.img         </td> </tr>
<tr> <td>Diverse Reports  <td>Debian Image for SD-Card                     </td> <td>  ---         </td>  <td>Report files in different formats                         </td> </tr>
<tr> <td>Diverse     Reports                        </td> </tr>
<tr> <td>Hardware-Platform-Specification-Files</td> <td>*.hdf<td>  ---         </td>  <td>Exported<td>Report Vivadofiles Hardwarein Specification for SDK/HSIdifferent formats                                       </td> </tr>
<tr> <td>LabTools Project-File                </td> <td></tr>
<tr> <td>Hardware-Platform-Specification-Files</td> <td>*.lprhdf         </td>  <td>Vivado<td>Exported LabtoolsVivado ProjectHardware FileSpecification for SDK/HSI                                       </td> </tr>
<tr> <td>LabTools Project-File                 </td> </tr>
<tr> <td>MCS-File <td>*.lpr         </td>  <td>Vivado Labtools Project File                 </td> <td>*.mcs         </td>  <td>Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)                             </td> </tr>
<tr> <td>MMI<td>MCS-File                             </td> <td>*.mmimcs         </td>  <td>Flash <td>FileConfiguration File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)Boot-Image (MicroBlaze or FPGA part only)                  </td> </tr>
<tr> <td>OS<td>MMI-ImageFile                             </td> <td>*.ubmmi          </td>  <td>Image<td>File with LinuxBRAM-Location Kernelto (Ongenerate PetalinuxMCS optional with Devicetree and RAM-Disk)             or BIT-File with *.elf content (MicroBlaze only) </td> </tr>
<tr> <td>Software<td>OS-Application-FileImage            </td> <td>*.elf         </td>  <td>Software Application for Zynq or MicroBlaze Processor Systems</td> <td>*.ub          </td>  <td>Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)             </td> </tr>
<tr> <td>SREC<td>Software-Application-File                            </td> <td>*.srecelf         </td>  <td>Converted Software<td>Software Application for Zynq or MicroBlaze Processor Systems                            </td> </tr>    
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File-Extension

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Description

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<tr> <td>SREC-File                            </td> <td>*.srec        </td>  <td>Converted Software Application for MicroBlaze Processor Systems                          </td> </tr>    
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File

File-Extension

Description

BIT-File*.bitFPGA (PL Part) Configuration File
DebugProbes-File*.ltxDefinition File for Vivado/Vivado Labtools Debugging Interface
Diverse Reports---Report files in different formats
Hardware-Platform-Specification-Files*.hdfExported Vivado Hardware Specification for SDK/HSI and PetaLinux
LabTools Project-File*.lprVivado Labtools Project File

MCS-File

*.mcs

Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)

MMI-File

*.mmi

File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)

Software-Application-File*.elfSoftware Application for Zynq or MicroBlaze Processor Systems

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Reference Design is available on:

Design Flow

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Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.

See also:Vivado/SDK/SDSoC

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Xilinx Development Tools#XilinxSoftware-BasicUserGuides

The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.

TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/SDK GUI.  For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality


  1. _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
  2. Press 0 and enter for minimum setup
  3. (optional Win OS) Generate Virtual Drive or use short directory  for the reference design (for example x:\<design name>)
  4. Create Project
    1. Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
      Note: Select correct one, see TE Board Part Files
  5. Create HDF and export to prebuilt folder
    1. Run on Vivado TCL: TE::hw_build_design -export_prebuilt
      Note: Script generate design and export files into \prebuilt\hardware\<short dir>. Use GUI is the same, except file export to prebuilt folder
  6. Generate MCS Firmware (optional):
    1. Create SDK Project with TE Scripts on Vivado TCL: TE::sw_run_sdk
    2. Create "SCU" application
      Note: Select MCS Microblaze and SCU Application
    3. Select Release Built
    4. Regenerate App
  7. (optional) Copy "\\workspace\sdk\scu\Release\scu.elf" into  "\firmware\microblaze_mcs_0\"
  8. Regenerate Vivado Project or Update Bitfile only and "scu.elf"
  9. Copy MCS file with Bitfile into prebuilt folder
    1. Create SDK Project with TE Scripts on Vivado TCL: TE::sw_run_hsi

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Xilinx documentation for programming and debugging: Vivado/SDK/SDSoC-Xilinx Software Programming and Debugging

QSPI

  1. Connect JTAG and power on PCB
  2. (if not done) Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd" or open with "vivado_open_project_guimode.cmd", if generated.
  3. Type on Vivado Console: TE::pr_program_flash_mcsfile -swapp
    Note: Alternative use SDK or setup Flash on Vivado manually
  4. Reboot (if not done automatically)

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  1. Connect JTAG and power on PCB
  2. Open Vivado HW Manager
  3. Program FPGA with Bitfile from "prebuilt\hardware\<short dir>"Note SREC Bootloader try to find application on flash, this will stop, if Flash is empty.

Usage

  1. Prepare HW like described on section Programming 70156396
  2. Connect UART USB (most cases same as JTAG)
  3. Power on PCB
    Note: FPGA Loads Bitfile from Flash,MCS Firmware configure SI5338 and starts MicroBlaze, MicroBlaze SREC Bootloader loads Hello TE0781 from Flash into RAM and starts application. Example will be run on UART console.IBERT.
              Do not reboot, if Bitfile programming over JTAG is used as programming method.

UART

Open Serial Console (e.g. putty)

  1. Speed: 9600
  2. COM Port: Win OS, see device manager, Linux OS see  dmesg |grep tty  (UART is *USB1)

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    1. On TE0841 SI5338 has default configuration and reprogramming of SI5338 is optional
  1. LED:
    1. D1 (green) OFF→ MCS SI configuration finished (System Reset is off)

Vivado HW Manager: 

  1. Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder).
    1. Set radix from VIO signals (fm_si...) to unsigned integer.
      Note: Frequency Counter is inaccurate and displayed unit is Hz
    2. SI will be configured with MCS firmware, default all off on PCB REV01
    3. LED control via VIO
    4. MGT CLK Freq can be changed over BUFG_GT control signals divider
    5. MCS Reset possible via VIO

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System Design - Vivado

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Block Design

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Constrains

Basic module constrains

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languageruby
title_i_bitgen_common.xdc

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  1. Manager 
  2. "Refresh device" is needed after Bitfile programming, because MCS reconfigure SI5338 and enables IBERT a little bit later.
    1. loopback depends on TEB0841 Revision an connection

Image Added



IBERT

Component Name

Net NameTEB0841
X0Y0224-0MGT4loop back RX/TX
X0Y1224-1MGT5loop back RX/TX
X0Y2224-2MGT6loopback over SD Pin header possible with lower Linerate otherwise use internal loopback
X0Y3224-3MGT7loop back RX/TX. Note: N.C. on TEB0841-01, use  internal loopback
X0Y4225-0MGT0loop back RX/TX
X0Y5225-1MGT1loop back RX/TX
X0Y6225-2MGT2loop back RX/TX
X0Y7225-3MGT3loopback over sfp possible

System Design - Vivado

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Block Design

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HDL

  • IBERT_top.v
  • ibert xci IPs

Constrains

Basic module constrains

Code Block
languageruby
title_i_bitgen_common.xdc
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property BITSTREAM.CONFIG.M1PINCONFIGRATE PULLNONE69 [current_design]
set_property BITSTREAM.CONFIG.M2PIN PULLNONECFGBVS GND [current_design]
set_property BITSTREAM.CONFIG_VOLTAGE 1.M0PIN8 PULLNONE [current_design]

set_property BITSTREAM.CONFIG.USR_ACCESSMODE TIMESTAMPSPIx4 [current_design]

Design specific constrain

Code Block
languageruby
title_i_ddr4.xdc
linenumberstrue

set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_pins -hier -filter {NAME =~ */u_ddr4_infrastructure/gen_mmcme*.u_mmcme_adv_inst/CLKIN1}]
create_clock -name ddr4_0_clk -period 4.95 [get_pins */ddr4_0/*/u_ddr4_infrastructure/gen_mmcme*.u_mmcme_adv_inst/CLKIN1]
create_clock -name ddr4_1_clk -period 4.95 [get_pins */ddr4_1/*/u_ddr4_infrastructure/gen_mmcme*.u_mmcme_adv_inst/CLKIN1]
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLUP [current_design
Code Block
languageruby
title_i_qspi.xdc
linenumberstrue
# You must provide all the delay numbers
# CCLK delay is 0.1, 6.7 ns min/max for ultra-scale devices; refer Data sheet
# Consider the max delay for worst case analysis
set cclk_delay 6.7
create_generated_clock -name clk_sck -source [get_pins -hierarchical *axi_quad_spi_0/ext_spi_clk] -edges {3 5 7} -edge_shift [list $cclk_delay $cclk_delay $cclk_delay] [get_pins -hierarchical *USRCCLKO]
set_multicycle_path -setup -from clk_sck -to [get_clocks -of_objects [get_pins -hierarchical */ext_spi_clk]] 2
set_multicycle_path -hold -end -from clk_sck -to [get_clocks -of_objects [get_pins -hierarchical */ext_spi_clk]] 1
set_multicycle_path -setup -start -from [get_clocks -of_objects [get_pins -hierarchical */ext_spi_clk]] -to clk_sck 2
set_multicycle_path -hold -from [get_clocks -of_objects [get_pins -hierarchical */ext_spi_clk]] -to clk_sck 1
# Max delay constraints are used to instruct the tool to place IP near to STARTUPE3 primitive.
# If needed adjust the delays appropriately
set_max_delay -datapath_only -from [get_pins -hier {*STARTUP*_inst/DI[*]}] 1.000
set_max_delay -datapath_only -from [get_clocks clk_out2_msys_clk_wiz_0_0] -to [get_pins -hier *STARTUP*_inst/USRCCLKO] 1.000
#set_max_delay -datapath_only -from [get_clocks clk_out2_msys_clk_wiz_0_0] -to [get_pins -hier *STARTUP*_inst/DO[*] {*STARTUP*_inst/DTS[*]}] 1.000
set_max_delay -datapath_only -from [get_clocks clk_out2_msys_clk_wiz_0_0] -to [get_pins -hier *STARTUP*_inst/DO[*]] 1.000
set_max_delay -datapath_only -from [get_clocks clk_out2_msys_clk_wiz_0_0] -to [get_pins -hier *STARTUP*_inst/DTS[*]] 1.000
Code Block
languageruby
title_i_fm.xdc
linenumberstrue
set_false_path -from [get_clocks {msys_i/util_ds_buf_5/U0/BUFG_GT_O[0]}] -to [get_clocks -of_objects [get_pins msys_i/clk_wiz_0/inst/mmcme3_adv_inst/CLKOUT0]]
set_false_path -from [get_clocks {msys_i/util_ds_buf_6/U0/BUFG_GT_O[0]}] -to [get_clocks -of_objects [get_pins msys_i/clk_wiz_0/inst/mmcme3_adv_inst/CLKOUT0]]
set_false_path -from [get_clocks -of_objects [get_pins msys_i/clk_wiz_0/inst/mmcme3_adv_inst/CLKOUT0]] -to [get_clocks {msys_i/util_ds_buf_6/U0/BUFG_GT_O[0]}]
set_false_path -from [get_clocks -of_objects [get_pins msys_i/clk_wiz_0/inst/mmcme3_adv_inst/CLKOUT0]] -to [get_clocks {msys_i/util_ds_buf_5/U0/BUFG_GT_O[0]}]

set_false_path -from [get_clocks -of_objects [get_pins msys_i/clk_wiz_0/inst/mmcme3_adv_inst/CLKOUT0]] -to [get_clocks {msys_i/util_ds_buf_1/U0/IBUF_OUT[0]}]
set_false_path -from [get_clocks -of_objects [get_pins msys_i/clk_wiz_0/inst/mmcme3_adv_inst/CLKOUT0]] -to [get_clocks {msys_i/util_ds_buf_4/U0/IBUF_OUT[0]}]
set_false_path -from [get_clocks {msys_i/util_ds_buf_1/U0/IBUF_OUT[0]}] -to [get_clocks -of_objects [get_pins msys_i/clk_wiz_0/inst/mmcme3_adv_inst/CLKOUT0]]
set_false_path -from [get_clocks {msys_i/util_ds_buf_4/U0/IBUF_OUT[0]}] -to [get_clocks -of_objects [get_pins msys_i/clk_wiz_0/inst/mmcme3_adv_inst/CLKOUT0]]
BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design]
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
set_property BITSTREAM.CONFIG.M1PIN PULLNONE [current_design]
set_property BITSTREAM.CONFIG.M2PIN PULLNONE [current_design]
set_property BITSTREAM.CONFIG.M0PIN PULLNONE [current_design]

set_property BITSTREAM.CONFIG.USR_ACCESS TIMESTAMP [current_design]

Design specific constrain


Code Block
languageruby
titleibert_ultrascale_gth_0.xdc
linenumberstrue
# file: ibert_ultrascale_gth_0.xdc
####################################################################################
##   ____  ____ 
##  /   /\/   /
## /___/  \  /    Vendor: Xilinx
## \   \   \/     Version : 2012.3
##  \   \         Application : IBERT Ultrascale
##  /   /         Filename : example_ibert_ultrascale_gth_0.xdc
## /___/   /\     
## \   \  /  \ 
##  \___\/\___\
##
##
## 
## Generated by Xilinx IBERT 7Series 
##**************************************************************************
##
## Icon Constraints
##
create_clock -name D_CLK -period 10.0 [get_ports gth_sysclkp_i]
set_clock_groups -group [get_clocks D_CLK -include_generated_clocks] -asynchronous
set_property C_CLK_INPUT_FREQ_HZ 100000000 [get_debug_cores dbg_hub]
set_property C_ENABLE_CLK_DIVIDER true [get_debug_cores dbg_hub]

##gth_refclk lock constraints
##
set_property PACKAGE_PIN AD6 [get_ports gth_refclk0p_i[0]]
set_property PACKAGE_PIN AD5 [get_ports gth_refclk0n_i[0]]
set_property PACKAGE_PIN AB6 [get_ports gth_refclk1p_i[0]]
set_property PACKAGE_PIN AB5 [get_ports gth_refclk1n_i[0]]
##
## Refclk constraints
##
create_clock -name gth_refclk0_0 -period 8.0 [get_ports gth_refclk0p_i[0]]
create_clock -name gth_refclk1_0 -period 8.0 [get_ports gth_refclk1p_i[0]]
set_clock_groups -group [get_clocks gth_refclk0_0 -include_generated_clocks] -asynchronous
set_clock_groups -group [get_clocks gth_refclk1_0 -include_generated_clocks] -asynchronous
##
## System clock pin locs and timing constraints
##
#set_property PACKAGE_PIN R25 [get_ports gth_sysclkp_i]
#set_property IOSTANDARD LVDS [get_ports gth_sysclkp_i]

Software Design - SDK/HSI

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MCS Firmware to configure SI5338 and Reset System.

Template location: \sw_lib\sw_apps\scu

Hello TE0841

Xilinx Hello World example as endless loop

Template location: \sw_lib\sw_apps\hello_te0841

SREC SPI Bootloader

Modified Xilinx SREC Bootloader. Changes: Correct flash typ and SRec Start address, some additional console outputs, see source code

Template location: \sw_lib\sw_apps\srec_spi_bootloader                               \sw_lib\sw_services\xilisf_v5_9scu

Additional Software

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DateDocument RevisionAuthorsDescription

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modified-date
dateFormatyyyy-MM-dd

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current-version
prefixv.



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modified-user

working in process


  • some notes
  • Issue for PCB REV01 only: MCS is disabled on the prebuilt design files

v.5John Hartfiel
  • Design update
  • new assembly variants (PCB REV02)

v.4John Hartfiel
  • Release 2017.4
2018-04-16v.1

Page info
created-user
created-user

  • Initial release

All

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modified-users


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