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<table width="100%">
<tr> <th>File                                 </th> <th>File-Extension</th>  <th>Description                                                                              </th> </tr>
<tr> <td>BIF-File                             </td> <td>*.bif           </td>  <td>File with description to generate Bin-Fileth> <th>File-Extension</th>  <th>Description                                                                              </td>th> </tr>
<tr> <td>BIN<td>BIF-File                             </td> <td>*.binbif         </td>  <td>File <td>Flashwith Configurationdescription Fileto withgenerate BootBin-ImageFile (Zynq-FPGAs)                                    </td> </          </td> </tr>
<tr> <td>BIT<td>BIN-File                             </td> <td>*.bitbin         </td>  <td>FPGA<td>Flash Configuration File with Boot-Image (Zynq-FPGAs)                                    </td> </tr>
<tr> <td>BIT-File                             </td> </tr>
<tr> <td>DebugProbes-File<td>*.bit         </td>  <td>FPGA Configuration File          </td> <td>*.ltx         </td>  <td>Definition File for Vivado/Vivado Labtools Debugging Interface                                          </td> </tr>
<tr> <td>Debian SD<td>DebugProbes-ImageFile                      </td> <td>*.imgltx         </td>  <td>Debian<td>Definition ImageFile for SD-Card  Vivado/Vivado Labtools Debugging Interface                           </td> </tr>
<tr> <td>Debian SD-Image                      </td> <td>*.img         </td> </tr>
<tr> <td>Diverse Reports  <td>Debian Image for SD-Card                     </td> <td>  ---         </td>  <td>Report files in different formats                         </td> </tr>
<tr> <td>Diverse     Reports                        </td> </tr>
<tr> <td>Hardware-Platform-Specification-Files</td> <td>*.hdf<td>  ---         </td>  <td>Exported<td>Report Vivadofiles Hardwarein Specification for SDK/HSIdifferent formats                                       </td> </tr>
<tr> <td>LabTools Project-File                </td> <td></tr>
<tr> <td>Hardware-Platform-Specification-Files</td> <td>*.lprhdf         </td>  <td>Vivado<td>Exported LabtoolsVivado ProjectHardware FileSpecification for SDK/HSI                                       </td> </tr>
<tr> <td>LabTools Project-File                 </td> </tr>
<tr> <td>MCS-File <td>*.lpr         </td>  <td>Vivado Labtools Project File                 </td> <td>*.mcs         </td>  <td>Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)                             </td> </tr>
<tr> <td>MMI<td>MCS-File                             </td> <td>*.mmimcs         </td>  <td>Flash <td>FileConfiguration File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)Boot-Image (MicroBlaze or FPGA part only)                  </td> </tr>
<tr> <td>OS<td>MMI-ImageFile                             </td> <td>*.ubmmi          </td>  <td>Image<td>File with LinuxBRAM-Location Kernelto (Ongenerate PetalinuxMCS optional with Devicetree and RAM-Disk)             or BIT-File with *.elf content (MicroBlaze only) </td> </tr>
<tr> <td>Software<td>OS-Application-FileImage            </td> <td>*.elf         </td>  <td>Software Application for Zynq or MicroBlaze Processor Systems</td> <td>*.ub          </td>  <td>Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)             </td> </tr>
<tr> <td>SREC<td>Software-Application-File                            </td> <td>*.srecelf         </td>  <td>Converted Software<td>Software Application for Zynq or MicroBlaze Processor Systems                            </td> </tr>    
</table>
-->

<tr> <td>SREC-File                            </td> <td>*.srec        </td>  <td>Converted Software Application for MicroBlaze Processor Systems                          </td> </tr>    
</table>
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Description of Block Design, Constrains...
BD Pictures from Export...
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set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_pins -hier -filter {NAME =~ */u_ddr4_infrastructure/gen_mmcme*.u_mmcme_adv_inst/CLKIN1}]
create_clock -name ddr4_0_clk -period 4.95 [get_pins */ddr4_0/*/u_ddr4_infrastructure/gen_mmcme*.u_mmcme_adv_inst/CLKIN1]
create_clock -name ddr4_1_clk -period 4.95 [get_pins */ddr4_1/*/u_ddr4_infrastructure/gen_mmcme*.u_mmcme_adv_inst/CLKIN1]
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLUP [current_design

# You must provide all the delay numbers
# CCLK delay is 0.1, 6.7 ns min/max for ultra-scale devices; refer Data sheet
# Consider the max delay for worst case analysis
set cclk_delay 6.7
create_generated_clock -name clk_sck -source [get_pins -hierarchical *axi_quad_spi_0/ext_spi_clk] -edges {3 5 7} -edge_shift [list $cclk_delay $cclk_delay $cclk_delay] [get_pins -hierarchical *USRCCLKO]
set_multicycle_path -setup -from clk_sck -to [get_clocks -of_objects [get_pins -hierarchical */ext_spi_clk]] 2
set_multicycle_path -hold -end -from clk_sck -to [get_clocks -of_objects [get_pins -hierarchical */ext_spi_clk]] 1
set_multicycle_path -setup -start -from [get_clocks -of_objects [get_pins -hierarchical */ext_spi_clk]] -to clk_sck 2
set_multicycle_path -hold -from [get_clocks -of_objects [get_pins -hierarchical */ext_spi_clk]] -to clk_sck 1
# Max delay constraints are used to instruct the tool to place IP near to STARTUPE3 primitive.
# If needed adjust the delays appropriately
set_max_delay -datapath_only -from [get_pins -hier {*STARTUP*_inst/DI[*]}] 1.000
set_max_delay -datapath_only -from [get_clocks clk_out2_msys_clk_wiz_0_0] -to [get_pins -hier *STARTUP*_inst/USRCCLKO] 1.000
#set_max_delay -datapath_only -from [get_clocks clk_out2_msys_clk_wiz_0_0] -to [get_pins -hier *STARTUP*_inst/DO[*] {*STARTUP*_inst/DTS[*]}] 1.000
set_max_delay -datapath_only -from [get_clocks clk_out2_msys_clk_wiz_0_0] -to [get_pins -hier *STARTUP*_inst/DO[*]] 1.000
set_max_delay -datapath_only -from [get_clocks clk_out2_msys_clk_wiz_0_0] -to [get_pins -hier *STARTUP*_inst/DTS[*]] 1.000