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DateVivadoProject BuiltAuthorsDescription
2018-06-05222017.4TE0841-IBERT_noprebuilt-vivado_2017.4-build_1011_2018060514385220180622140813.zip
TE0841-IBERT-vivado_2017.4-build_1011_2018060514383720180622140615.zip
John Hartfiel
  • initial release

Release Notes and Know Issues

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  • REV02 Board parts
  • new SI5338 configuration (default REV02)
  • change xilisf_v5_9 for N25Q512A11G1240E support
  • Some changes on block design
2018-06-052017.4TE0841-IBERT_noprebuilt-vivado_2017.4-build_10_20180605143852.zip
TE0841-IBERT-vivado_2017.4-build_10_20180605143837.zip
John Hartfiel
  • initial release

Release Notes and Know Issues

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IssuesDescriptionWorkaroundTo be fixed version
---------PCB REV01 only: IBERT no CLKPCB REV01 SI5338 is not preprogrammed and SI programming over MCS is disabled by default design and I2C is not connectedLoad test_board bitfile for REV01 and load IBERT design again without power off HW---

Requirements

Software

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Complete List is available on <design name>/board_files/*_board_files.csv

Design supports following modules:

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/*_board_files.csv

Design supports following modules:

Module ModelBoard Part Short NamePCB Revision SupportDDRQSPI FlashOthersNotes
TE0841-01-035-1C 01_35_1cREV012x 512MB DDR432MB---
TE0841-01-035-1I01_35_1iREV012x 512MB DDR432MB---
TE0841-01-035-2I01_35_2iREV012x 512MB DDR432MB---
TE0841-01-040-1C01_40_1cREV012x 512MB DDR432MB---Serial number 512479 up tp 512474  has same 64MB Flash like REV02
TE0841-01-040-1I01_40_1iREV012x 512MB DDR432MB---
TE0841-01-040-2I01_40_2iREV012x 512MB DDR432MB---
TE0841-02-035-1C02_35_1cREV022x 1GB DDR464MB---
TE0841-0102-035-1I0102_35_1iREV01REV022x 512MB 1GB DDR432MB64MB---
TE0841-0102-035-2I0102_35_2iREV01REV022x 512MB 1GB DDR432MB64MB---
TE0841-0102-040-1C0102_40_1cREV01REV022x 512MB 1GB DDR432MB64MB---
TE0841-0102-040-1I0102_40_1iREV01REV022x 512MB 1GB DDR432MB64MB---
TE0841-0102-040-2I1IL0102_40_2i1iREV01REV022x 512MB 1GB DDR432MB---64MBlow profile B2B connector

Design supports following carriers:

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For general structure and of the reference design, see Project Delivery - Xilinx devices

Design Sources

TypeLocationNotes
Vivado<design name>/block_design
<design name>/constraints
<design name>/ip_lib
<design name>/firmware
Vivado Project will be generated by TE Scripts
SDK/HSI<design name>/sw_libAdditional Software Template for SDK/HSI and apps_list.csv with settings for HSI

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Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.

See also:Vivado/SDK/SDSoC

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Xilinx Development Tools#XilinxSoftware-BasicUserGuides

The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.

TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/SDK GUI.  For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality


  1. _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
  2. Press 0 and enter for minimum setup
  3. (optional Win OS) Generate Virtual Drive or use short directory  for the reference design (for example x:\<design name>)
  4. Create Project
    1. Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
      Note: Select correct one, see TE Board Part Files
  5. Create HDF and export to prebuilt folder
    1. Run on Vivado TCL: TE::hw_build_design -export_prebuilt
      Note: Script generate design and export files into \prebuilt\hardware\<short dir>. Use GUI is the same, except file export to prebuilt folder
  6. Generate MCS Firmware (optional):
    1. Create SDK Project with TE Scripts on Vivado TCL: TE::sw_run_sdk
    2. Create "SCU" application
      Note: Select MCS Microblaze and SCU Application
    3. Select Release Built
    4. Regenerate App
  7. (optional) Copy "\\workspace\sdk\scu\Release\scu.elf" into  "\firmware\microblaze_mcs_0\"
  8. Regenerate Vivado Project or Update Bitfile only and "scu.elf"
  9. Copy MCS file with Bitfile into prebuilt folder
    1. Create SDK Project with TE Scripts on Vivado TCL: TE::sw_run_hsi

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Xilinx documentation for programming and debugging: Vivado/SDK/SDSoC-Xilinx Software Programming and Debugging

QSPI

  1. Connect JTAG and power on PCB
  2. (if not done) Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd" or open with "vivado_open_project_guimode.cmd", if generated.
  3. Type on Vivado Console: TE::pr_program_flash_mcsfile -swapp
    Note: Alternative use SDK or setup Flash on Vivado manually
  4. Reboot (if not done automatically)

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  1. Prepare HW like described on section Programming 70156396
  2. Connect UART USB (most cases same as JTAG)
  3. Power on PCB
    Note: FPGA Loads Bitfile from Flash,MCS Firmware configure SI5338 and starts IBERT.
              Do not reboot, if Bitfile programming over JTAG is used as programming method.
    1. On TE0841 SI5338 has default configuration and reprogramming of SI5338 is optional
  4. LED:
    1. D1 (green) OFF→ MCS SI configuration finished (System Reset is off)

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  1. Open Vivado HW-Manager 
  2. "Refresh device" is needed after Bitfile programming, because MCS reconfigure SI5338 and enables IBERT a little bit later.
    1. loopback depends on TEB0841 Revision an connection

Image RemovedImage Added



IBERT

Component Name

Net NameTEB0841
X0Y0224-0MGT4loop back RX/TX
X0Y1224-1MGT5loop back RX/TX
X0Y2224-2MGT6loopback over SD Pin header possible with lower Linerate otherwise use internal loopback
X0Y3224-3MGT7loop back RX/TX. Note: N.C. on TEB0841-01, use  internal loopback
X0Y4225-0MGT0loop back RX/TX
X0Y5225-1MGT1loop back RX/TX
X0Y6225-2MGT2loop back RX/TX
X0Y7225-3MGT3loopback over sfp possible

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Block Design

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HDL

  • IBERT_top.v
  • ibert xci IPs

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Code Block
languageruby
titleibert_ultrascale_gth_0.xdc
linenumberstrue
# file: ibert_ultrascale_gth_0.xdc
####################################################################################
##   ____  ____ 
##  /   /\/   /
## /___/  \  /    Vendor: Xilinx
## \   \   \/     Version : 2012.3
##  \   \         Application : IBERT Ultrascale
##  /   /         Filename : example_ibert_ultrascale_gth_0.xdc
## /___/   /\     
## \   \  /  \ 
##  \___\/\___\
##
##
## 
## Generated by Xilinx IBERT 7Series 
##**************************************************************************
##
## Icon Constraints
##
create_clock -name D_CLK -period 10.0 [get_ports gth_sysclkp_i]
set_clock_groups -group [get_clocks D_CLK -include_generated_clocks] -asynchronous
set_property C_CLK_INPUT_FREQ_HZ 100000000 [get_debug_cores dbg_hub]
set_property C_ENABLE_CLK_DIVIDER true [get_debug_cores dbg_hub]

##gth_refclk lock constraints
##
set_property PACKAGE_PIN AD6 [get_ports gth_refclk0p_i[0]]
set_property PACKAGE_PIN AD5 [get_ports gth_refclk0n_i[0]]
set_property PACKAGE_PIN AB6 [get_ports gth_refclk1p_i[0]]
set_property PACKAGE_PIN AB5 [get_ports gth_refclk1n_i[0]]
##
## Refclk constraints
##
create_clock -name gth_refclk0_0 -period 8.0 [get_ports gth_refclk0p_i[0]]
create_clock -name gth_refclk1_0 -period 8.0 [get_ports gth_refclk1p_i[0]]
set_clock_groups -group [get_clocks gth_refclk0_0 -include_generated_clocks] -asynchronous
set_clock_groups -group [get_clocks gth_refclk1_0 -include_generated_clocks] -asynchronous
##
## System clock pin locs and timing constraints
##
set#set_property PACKAGE_PIN R25 [get_ports gth_sysclkp_i]
set#set_property IOSTANDARD LVDS [get_ports gth_sysclkp_i]

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DateDocument RevisionAuthorsDescription

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modified-date
modified-date
dateFormatyyyy-MM-dd

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current-version
current-version
prefixv.



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modified-user
modified-user

  • some notes
  • Issue for PCB REV01 only: MCS is disabled on the prebuilt design files

v.5John Hartfiel
  • Design update
  • new assembly variants (PCB REV02)

v.4John Hartfiel
  • Release 2017.4
2018-04-16v.1

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created-user
created-user

  • Initial release

All

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modified-users


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