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DateVivadoProject BuiltAuthorsDescription
2018-06-05222017.4TE0841-IBERT_noprebuilt-vivado_2017.4-build_1011_2018060514385220180622140813.zip
TE0841-IBERT-vivado_2017.4-build_1011_2018060514383720180622140615.zip		John Hartfiel
  • initial release

Release Notes and Know Issues

  • REV02 Board parts
  • new SI5338 configuration (default REV02)
  • change xilisf_v5_9 for N25Q512A11G1240E support
  • Some changes on block design
2018-06-052017.4TE0841-IBERT_noprebuilt-vivado_2017.4-build_10_20180605143852.zip
TE0841-IBERT-vivado_2017.4-build_10_20180605143837.zip		John Hartfiel
  • initial release

Release Notes and Know Issues

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Complete List is available on <design name>/board_files/*_board_files.csv

Design supports following modules:

Design supports following modules:

Module ModelBoard Part Short NamePCB Revision SupportDDRQSPI FlashOthersNotes
TE0841-01-035-1C 01_35_1cREV012x 512MB DDR432MB---
TE0841-01-035-1I01_35_1iREV012x 512MB DDR432MB---
TE0841-01-035-2I01_35_2iREV012x 512MB DDR432MB---
TE0841-01-040-1C01_40_1cREV012x 512MB DDR432MB---
TE0841-01-040-1I01_40_1iREV012x 512MB DDR432MB---
TE0841-01-040-2I01_40_2iREV012x 512MB DDR432MB---
TE0841-02-035-1C02_35_1cREV022x 1GB DDR464MB
Module ModelBoard Part Short NamePCB Revision SupportDDRQSPI FlashOthersNotes
TE0841-01-035-1C 01_35_1cREV012x 512MB DDR432MB---
TE0841-0102-035-1I0102_35_1iREV01REV022x 512MB 1GB DDR432MB64MB---
TE0841-0102-035-2I0102_35_2iREV01REV022x 512MB 1GB DDR432MB64MB---
TE0841-0102-040-1C0102_40_1cREV01REV022x 512MB 1GB DDR432MB64MB---
TE0841-0102-040-1I0102_40_1iREV01REV022x 512MB 1GB DDR432MB64MB---
TE0841-0102-040-2I1IL0102_40_2i1iREV01REV022x 512MB 1GB DDR432MB64MBlow profile B2B connector---

Design supports following carriers:

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  1. Open Vivado HW-Manager 
  2. "Refresh device" is needed after Bitfile programming, because MCS reconfigure SI5338 and enables IBERT a little bit later.
    1. loopback depends on TEB0841 Revision an connection

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IBERT

Component Name

Net NameTEB0841
X0Y0224-0MGT4loop back RX/TX
X0Y1224-1MGT5loop back RX/TX
X0Y2224-2MGT6loopback over SD Pin header possible with lower Linerate otherwise use internal loopback
X0Y3224-3MGT7loop back RX/TX. Note: N.C. on TEB0841-01, use  internal loopback
X0Y4225-0MGT0loop back RX/TX
X0Y5225-1MGT1loop back RX/TX
X0Y6225-2MGT2loop back RX/TX
X0Y7225-3MGT3loopback over sfp possible

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Block Design

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HDL

  • IBERT_top.v
  • ibert xci IPs

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Code Block
languageruby
titleibert_ultrascale_gth_0.xdc
linenumberstrue
# file: ibert_ultrascale_gth_0.xdc
####################################################################################
##   ____  ____ 
##  /   /\/   /
## /___/  \  /    Vendor: Xilinx
## \   \   \/     Version : 2012.3
##  \   \         Application : IBERT Ultrascale
##  /   /         Filename : example_ibert_ultrascale_gth_0.xdc
## /___/   /\     
## \   \  /  \ 
##  \___\/\___\
##
##
## 
## Generated by Xilinx IBERT 7Series 
##**************************************************************************
##
## Icon Constraints
##
create_clock -name D_CLK -period 10.0 [get_ports gth_sysclkp_i]
set_clock_groups -group [get_clocks D_CLK -include_generated_clocks] -asynchronous
set_property C_CLK_INPUT_FREQ_HZ 100000000 [get_debug_cores dbg_hub]
set_property C_ENABLE_CLK_DIVIDER true [get_debug_cores dbg_hub]

##gth_refclk lock constraints
##
set_property PACKAGE_PIN AD6 [get_ports gth_refclk0p_i[0]]
set_property PACKAGE_PIN AD5 [get_ports gth_refclk0n_i[0]]
set_property PACKAGE_PIN AB6 [get_ports gth_refclk1p_i[0]]
set_property PACKAGE_PIN AB5 [get_ports gth_refclk1n_i[0]]
##
## Refclk constraints
##
create_clock -name gth_refclk0_0 -period 8.0 [get_ports gth_refclk0p_i[0]]
create_clock -name gth_refclk1_0 -period 8.0 [get_ports gth_refclk1p_i[0]]
set_clock_groups -group [get_clocks gth_refclk0_0 -include_generated_clocks] -asynchronous
set_clock_groups -group [get_clocks gth_refclk1_0 -include_generated_clocks] -asynchronous
##
## System clock pin locs and timing constraints
##
set#set_property PACKAGE_PIN R25 [get_ports gth_sysclkp_i]
set#set_property IOSTANDARD LVDS [get_ports gth_sysclkp_i]

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DateDocument RevisionAuthorsDescription

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prefixv.



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  • Design update
  • new assembly variants (PCB REV02)

v.4John Hartfiel
  • Release 2017.4
2018-04-16v.1

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  • Initial release

All

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