Design Name always "TE Series Name" + Design name, for example "TE0720 Test Board"
HTML
<!--
TemplateRevision 1.3
Basic Notes
- export PDF to download, if vivado revision is changed!
- Template is for different design and SDSoC and examples, remove unused or wrong description!
-->
Scroll Only (inline)
Online version of this manual and other related documents can be found at https://wiki.trenz-electronic.de/display/PD/Trenz+Electronic+Documentation
Scroll pdf ignore
Table of contents
Table of Contents
outline
true
Overview
HTML
<!--
General Design description
-->
MicroBlaze Design with HyperRAM memory test example.
This reference designs is bundled with a FREE evaluation edition of the commercially proven, low-cost, low-circuit area, high performance, HyperBus Memory Controller (HBMC) IP supplied by Synaptic Laboratories Ltd. Synaptic Labs HBMC IP is commercially proven in both Intel and Xilinx projects, and was selected by Intel. This FREE HBMC IP evaluation license never expires, and no customer registration or NIC ID is required.
You can check for and obtain the latest version of the FREE evaluation HBMC IP from S/Labs website for Xilinx on S/Labs HBMC IP (Free Trail IP) . Please send your HBMC IP support questions to info@synaptic-labs.com
Key Features
HTML
<!--
Add Basic Key Features of the design (should be tested)
-->
Excerpt
MicroBlaze
QSPI
I2C
UART
HyperRAM
S/Labs HBMC IP (Free Trail IP)
Revision History
HTML
<!--
- Add changes from design
- Export PDF to download, if vivado revision is changed!
-->
...
initial release
Release Notes and Know Issues
HTML
<!--
- add known Design issues and general Notes for the current revision
-->
Complete List is available on <design name>/board_files/*_board_files.csv
Design supports following modules:
...
Design supports following carriers:
...
Additional HW Requirements:
...
tables have all same width (web max 1200px and pdf full page(640px), flexible width or fix width on menu for single column can be used as before) -->
<style>
.wrapped{
width: 100% !important;
max-width: 1200px !important;
}
</style>
Page properties
hidden
true
id
Comments
Important General Note:
Export PDF to download, if vivado revision is changed!
Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro
Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)
Figure template (note: inner scroll ignore/only only with drawIO object):
Scroll Title
anchor
Figure_xyz
title
Text
Scroll Ignore
Create DrawIO object here: Attention if you copy from other page, use
Scroll Only
image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed
Table template:
Layout macro can be use for landscape of large tables
Set column width manually(can be used for small tables to fit over whole page) or leave empty (automatically)
MicroBlaze Design with HyperRAM memory test example.
This reference design is bundled with a FREE evaluation edition of the low-cost, commercially proven, high performance memory controller IP supplied by Synaptic Laboratories Ltd (SLL). This free IP evaluation license never expires, and no customer registration or NIC ID is required. Click here to find the latest free trials of SLL’s memory controller IP for HyperBus, OctaBus, Xccela Bus, JEDEC xSPI Profile 1.0 and JEDEC xSPI Profile 2.0 for Intel, Microchip, and Xilinx FPGA. SLL IP is also qualified for use with Trenz HS CRUVI enabled boards. Please send all sales enquiry and technical support questions for SLL’s IP to info@synaptic-labs.com
Refer to http://trenz.org/te0725-info for the current online version of this manual and other available documentation.
Key Features
Page properties
hidden
true
id
Comments
Notes :
Add basic key futures, which can be tested with the design
Additional Software Template for Vitis and apps_list.csv with settings automatically for Vitis app generation
Additional Sources
Scroll Title
anchor
Table_ADS
title
Additional design sources
Scroll Table Layout
orientation
portrait
sortDirection
ASC
repeatTableHeaders
default
style
widths
sortByColumn
1
sortEnabled
false
cellHighlighting
true
Type
Location
Notes
--
--
--
Prebuilt
Page properties
hidden
true
id
Comments
Notes :
prebuilt files
Template Table:
Scroll Title
anchor
Table_PF
title
Prebuilt files
Scroll Table Layout
orientation
portrait
sortDirection
ASC
repeatTableHeaders
default
style
widths
sortByColumn
1
sortEnabled
false
cellHighlighting
true
File
File-Extension
Description
BIF-File
*.bif
File with description to generate Bin-File
BIN-File
*.bin
Flash Configuration File with Boot-Image (Zynq-FPGAs)
BIT-File
*.bit
FPGA (PL Part) Configuration File
DebugProbes-File
*.ltx
Definition File for Vivado/Vivado Labtools Debugging Interface
Debian SD-Image
*.img
Debian Image for SD-Card
...
Content
HTML
<!--
Remove unused content
-->
For general structure and of the reference design, see Project Delivery
Design Sources
...
Additional Sources
...
Prebuilt
HTML
<!--
<table width="100%">
<tr> <th>File </th> <th>File-Extension</th> <th>Description </th> </tr>
<tr> <td>BIF-File </td> <td>*.bif </td> <td>File with description to generate Bin-File </td> </tr>
<tr> <td>BIN-File </td> <td>*.bin </td> <td>Flash Configuration File with Boot-Image (Zynq-FPGAs) </td> </tr>
<tr> <td>BIT-File </td> <td>*.bit </td> <td>FPGA Configuration File </td> </tr>
<tr> <td>DebugProbes-File </td> <td>*.ltx </td> <td>Definition File for Vivado/Vivado Labtools Debugging Interface </td> </tr>
<tr> <td>Debian SD-Image </td> <td>*.img </td> <td>Debian Image for SD-Card </td> </tr>
<tr> <td>Diverse Reports </td> <td> --- </td> <td>Report files in different formats </td> </tr>
<tr> <td>Hardware-Platform-Specification-Files</td> <td>*.hdf </td> <td>Exported Vivado Hardware Specification for SDK/HSI </td> </tr>
<tr> <td>LabTools Project-File </td> <td>*.lpr </td> <td>Vivado Labtools Project File </td> </tr>
<tr> <td>MCS-File </td> <td>*.mcs </td> <td>Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only) </td> </tr>
<tr> <td>MMI-File </td> <td>*.mmi </td> <td>File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only) </td> </tr>
<tr> <td>OS-Image </td> <td>*.ub </td> <td>Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk) </td> </tr>
<tr> <td>Software-Application-File </td> <td>*.elf </td> <td>Software Application for Zynq or MicroBlaze Processor Systems </td> </tr>
<tr> <td>SREC-File </td> <td>*.srec </td> <td>Converted Software Application for MicroBlaze Processor Systems </td> </tr>
</table>
-->
...
File
...
File-Extension
...
Description
...
Diverse Reports
---
Report files in different formats
Hardware-Platform-Specification-Files
*.
...
xsa
Exported Vivado Hardware Specification for
...
Vitis and PetaLinux
LabTools Project-File
*.lpr
Vivado Labtools Project File
MCS-File
*.mcs
Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)
MMI-File
*.mmi
File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)
OS-Image
*.ub
Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)
Software-Application-File
*.elf
Software Application for Zynq or MicroBlaze Processor Systems
Download
Reference Design is only usable with the specified Vivado/SDK/PetaLinux/SDx version. Do never use different Versions of Xilinx Software for the same Project.
The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.
TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/SDK GUI. For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality
_create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell: Image Removed
Press 0 and enter for minimum setup
(optional Win OS) Generate Virtual Drive or use short directory for the reference design (for example x:\<design name>)
Create Project
Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd" Note: Select correct one, see TE Board Part Files
Create HDF and export to prebuilt folder
Run on Vivado TCL: TE::hw_build_design -export_prebuilt Note: Script generate design and export files into \prebuilt\hardware\<short dir>. Use GUI is the same, except file export to prebuilt folder
Generate Programming Files with HSI/SDK
Run on Vivado TCL: TE::sw_run_hsi Note: Scripts generate applications and bootable files, which are defined in "sw_lib\apps_list.csv"
(alternative) Start SDK with Vivado GUI or start with TE Scripts on Vivado TCL: TE::sw_run_sdk Note: See SDK Projects
Copy Application (memory_tests.elf) into \firmware\microblaze_0\
Regenerate Design:
Run on Vivado TCL: TE::hw_build_design -export_prebuilt Note: App from Firmware folder will be add into BlockRAM. If you add other app, you must select *.elf manually on Vivado
(alternative) Use SDK or Vivado to update generate Bitfile with new Application and regenerate mcs manually.
Launch
Programming
HTML
<!--
Description of Block Design, Constrains...
BD Pictures from Export...
-->
Note
Check Module and Carrier TRMs for proper HW configuration before you try any design.
Converted Software Application for MicroBlaze Processor Systems
Scroll Title
anchor
Table_PF
title
Prebuilt files (only on ZIP with prebult content)
Scroll Table Layout
orientation
portrait
sortDirection
ASC
repeatTableHeaders
default
style
widths
sortByColumn
1
sortEnabled
false
cellHighlighting
true
File
File-Extension
Description
BIT-File
*.bit
FPGA (PL Part) Configuration File
DebugProbes-File
*.ltx
Definition File for Vivado/Vivado Labtools Debugging Interface
Diverse Reports
---
Report files in different formats
Hardware-Platform-Specification-Files
*.xsa
Exported Vivado Hardware Specification for Vitis and PetaLinux
LabTools Project-File
*.lpr
Vivado Labtools Project File
MCS-File
*.mcs
Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)
MMI-File
*.mmi
File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)
Software-Application-File
*.elf
Software Application for Zynq or MicroBlaze Processor Systems
SREC-File
*.srec
Converted Software Application for MicroBlaze Processor Systems
Download
Reference Design is only usable with the specified Vivado/Vitis/PetaLinux version. Do never use different Versions of Xilinx Software for the same Project.
Page properties
hidden
true
id
Comments
Important set new Vivado version link on every Design update of new vivado version!
The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.
TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/SDK GUI. For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality
_create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell: Image Added
Press 0 and enter to start "Module Selection Guide"
(optional Win OS) Generate Virtual Drive or use short directory for the reference design (for example x:\<design name>)
Create Project (follow instruction of the product selection guide), settings file will be configured automatically during this process)
(optional for manual changes
Connect JTAG and power on PCB
(if not done
) Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
or open with "vivado_open_project_guimode.cmd", if generated.
Alternative use SDK or setup Flash on Vivado manually
Reboot (if not done automatically)
SD
Not used on this Example.
JTAG
Connect JTAG and power on PCB
(if not done) Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd" or open with "vivado_open_project_guimode.cmd", if generated.
Open Vivado HW Manager
Program Bitfile
Usage
Info
HBMC IP is a 10 minute run-time limited evaluation version of the full-edition
<!--
Add Description for other Software, for example SI CLK Builder ...
-->
No additional software is needed.
Appx. A: Change History and Legal Notices
Document Change History
To get content of older revision got to "Change History" of this page and select older document revision number.
Script generate design and export files into \prebuilt\hardware\<short dir>. Use GUI is the same, except file export to prebuilt folder
Generate Programming Files with Vitis
Run on Vivado TCL: TE::sw_run_vitis -all Note: Scripts generate applications and bootable files, which are defined in "sw_lib\apps_list.csv" App from Firmware folder will be add into BlockRAM. If you add other app, you must select *.elf manually on Vivado
(alternative) Start SDK with Vivado GUI or start with TE Scripts on Vivado TCL: TE::sw_run_vitis Note: TCL scripts generate also platform project, this must be done manuelly in case GUI is used. See Vitis
Copy Application (memory_test.elf) into \firmware\microblaze_0\
memory_test.elf or srec_spi_bootloader.elf Note only one elf shouldbe put into this folder
Regenerate Design:
Run on Vivado TCL: TE::hw_build_design -export_prebuilt Note: App from Firmware folder will be add into BlockRAM. If you add other app, you must select *.elf manually on Vivado
(alternative) Use SDK or Vivado to update generate Bitfile with new Application and regenerate mcs manually.
Launch
Programming
Page properties
hidden
true
id
Comments
Note:
Programming and Startup procedure
Note
Check Module and Carrier TRMs for proper HW configuration before you try any design.
_create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell
Press 0 and enter to start "Module Selection Guide"
Select assembly version
Validate selection
Select Create and open delivery binary folder Note: Folder (<project foler>/_binaries_<Artikel Name>) with subfolder (boot_<app name>) for different applications will be generated
QSPI
Connect JTAG and power on PCB
(if not done) Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd" or open with "vivado_open_project_guimode.cmd", if generated.
Type on Vivado Console: TE::pr_program_flash Note: Alternative use SDK or setup Flash on Vivado manually
Reboot (if not done automatically)
SD
Not used on this Example.
JTAG
Connect JTAG and power on PCB
(if not done) Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd" or open with "vivado_open_project_guimode.cmd", if generated.
Open Vivado HW Manager
Program Bitfile
Note: Flash musst be configured with correct mcs file, in case srec_spi_bootloader.elf is used as app
Usage
Info
HBMC IP is a 10 minute run-time limited evaluation version of the full-edition
Power On PCB (Do not restart, if you use Bitfile programming) Note: FPGA Loads Bitfile from Flash
UART
Open Serial Console (e.g. putty)
Speed: 9600
COM Port: Win OS, see device manager, Linux OS see dmesg |grep tty (UART is *USB1)
Uart Console: Srec and Hello TE0725: Important, Hello TE0725 is running on Hyperam and Hyperram DEMO-IP has timebomb and stop working after appr. 10 min Image Added
System Design - Vivado
Page properties
hidden
true
id
Comments
Note:
Description of Block Design, Constrains... BD Pictures from Export...
To get content of older revision got to "Change History" of this page and select older document revision number.
Page properties
hidden
true
id
Comments
Note this list must be only updated, if the document is online on public doc!
It's semi automatically, so do following
Add new row below first
Copy "Page Information Macro(date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf export template
Metadata is only used of compatibility of older exports
Scroll Title
anchor
Table_dch
title
Document change history.
Scroll Table Layout
orientation
portrait
sortDirection
ASC
repeatTableHeaders
default
style
widths
2*,*,3*,4*
sortByColumn
1
sortEnabled
false
cellHighlighting
true
HTML
<!--
Generate new entry:
1:add new row below first
2:Copy Page Information Macro(date+user) Preview, Page Information Macro Preview
3.Update Metadate =Page Information Macro Preview+1
-->