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Block Diagram
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Figure 1: TEM0001-01 block diagram
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- Microsemi SmartFusion2 FPGA SoC, U5
- 8 Mbyte SDRAM 166MHz, U2
- Micro USB2 B socket (receptacle), J9
- Switch button (reset), S1
- Switch button (user), S2
- Red LED (user), D10
- Green LED (indicating supply voltage), D1
- 8x red LEDs (user), D2 - D9
- FTDI USB2 to JTAG/UART adapter, U3
- 8 Mbyte QSPI Flash memory, U1
- 32.768 KHz auxiliary crystal oscillator, Y1
- 25 MHz main crystal oscillator, Y2
- 1x14 pin header (2.54mm pitch), J2
- 1x6 pin header (2.54mm pitch), J4
- 3-pin header (2.54mm pitch), J3
- 1x14 pin header (2.54mm pitch), J1
- 2x6 Pmod connector, J6
Initial Delivery State
Storage device name | Content | Notes |
|---|---|---|
Quad SPI Flash (U1) OTP area | DEMO Design | - |
| I2C Configuration EEPROM, U9 | Programmed | - |
Table 1: Initial delivery state of programmable devices on the module
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I/O signals of the FPGA SoC's I/O banks connected to the board's pin headers and connectors:
| Bank | Connector Designator | I/O Signal Count | Bank Voltage | Notes |
|---|---|---|---|---|
| 1 | J1 | 1 I/O's | 3.3V | - |
| 1 | J2 | 4 I/O's | 3.3V | 2 I/O's of bank 1 can be pulled-up to 3.3V (4K7 resistors) with 2 I/O's of Bank 7 or pins can be shared. |
| 2 | J1 | 13 I/O's | 3.3V | - |
| 2 | J2 | 5 I/O's | 3.3V | - |
| 2 | J6 | 8 /O's | 3.3V | Pmod Connector. |
| 3 | J4 | 5 I/O's | 3.3V | JTAG interface. |
| 4 | J3 | 2 I/O's | 3.3V | I/O's (PROBE A, B) are dedicated to live probes. |
| 7 | J2 | 2 I/O's | 3.3V | Those 2 I/O's are dedicated to pull-up 2 I/O's of bank 1 or pins can be shared. |
Table 2: General overview of single ended I/O signals connected to pin headers and connectors
FPGA I/O banks
| Bank | VCCIO | I/O's Count | Available on Connectors | Notes |
|---|---|---|---|---|
| 1 | 3.3V | 14 | 5 | 6 I/O's connected to FTDI chip, 1 I/O used for user button S2, 2 I/O's connected to red user LEDs D2 and D10. |
| 2 | 3.3V | 37 | 26 | 6 I/O's user for QSPI Flash, 5 I/O's connected to red user LEDs D3 ... D7. |
| 3 | 3.3V | 5 | 5 | Bank 3 is dedicated to JTAG interface. |
| 4 | 3.3V | 24 | 0 | 2 I/O's are dedicated to live probes, all other I/O's are used as memory interface. |
| 7 | 3.3V | 22 | 2 | 2 I/O's available on header J2, 2 I/O's connected to red user LEDs D8 and D9, all other I/O's are used as memory interface. |
Table 3: General overview of FPGA I/O banks
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Optionally 1x6 male pin header J4 can be fitted on board for access to the JTAG interface on board. The pin assignment of header J4 is shown on table below:
| JTAG Signal | Pin on Header J4 | Note |
|---|---|---|
| TCK | 3 | - |
| TDI | 5 | - |
| TDO | 4 | - |
| TMS | 6 | - |
| JTAGSEL | 2 | The JTAGSEL pin of SmartFusion2 device depends on the used JTAG programmer. |
Table 4: optional second JTAG interface or GPIO (JTAGSEL dependent)
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The QSPI interface of the FPGA device is routed to and used by the on-module QSPI flash IC U1:
| SD IO Signal Schematic Name | FPGA I/O | Flash IC U1 Pin | Note |
|---|---|---|---|
| F_CS | Bank 2, pin K15 | 1 | QSPI chip select |
| F_CLK | Bank 2, pin P18 | 6 | QSPI clock |
| F_DI | Bank 2, pin P19 | 5 | QSPI data |
| F_DO | Bank 2, pin K16 | 2 | QSPI data |
| F_D2 | Bank 2, pin J18 | 3 | QSPI data |
| F_D3 | Bank 2, pin N19 | 7 | QSPI data |
Table 5: QSPI interface signals
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The FPGA SoC module has following reference clocking signals provided by on-board oscillators:
| Clock Source | Schematic Name | Frequency | Clock Input Destination |
|---|---|---|---|
| Microchip MEMS Oscillator, U7 | CLK12M | 12.0000 MHz | FTDI FT2232 U3, pin 3; FPGA SoC bank 2, pin N16 |
ECS SMD Crystal Oscillator, Y1 | - | 32.768 KHz | FPGA SoC U5 auxiliary clock input, pin W17/Y17 |
| AVX Quartz Crystal Oscillator, Y2 | - | 25.000 MHz | FPGA SoC U5 main clock input, pin W18/Y18 |
Table 6: Clock sources overview
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There are 10 LEDs fitted on the FPGA module board. The LEDs are user configurable to indicate for example any system status.
| LED | Color | Signal Schematic Name | FPGA | Notes |
|---|---|---|---|---|
| D1 | Green | - | - | Indicating 3.3V board supply voltage |
| D2 | Red | 'LED1' | E18 | user |
| D3 | Red | 'LED2' | R17 | user |
| D4 | Red | 'LED3' | R18 | user |
| D5 | Red | 'LED4' | T18 | user |
| D6 | Red | 'LED5' | U18 | user |
| D7 | Red | 'LED6' | R16 | user |
| D8 | Red | 'LED7' | E1 | user |
| D9 | Red | 'LED8' | D2 | user |
| D10 | Red | 'USER_LED' | G17 | user |
Table 7: LEDs of the module
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The TEM0001 FPGA module is equipped with two push buttons S1 and S2:
| Button | Signal Schematic Name | FPGA | Notes |
|---|---|---|---|
| S1 | 'USER_BTN' | B19 | user configurable |
| S2 | 'RESET' | U17 | system reset |
Table 8: Push buttons of the module
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Figure 3: Power Distribution Diagram
Power Consumption
| FPGA | Design | Typical Power, 25C ambient |
|---|---|---|
| Mircosemi SmartFusion2 FPGA SoC M2S010-VFG400 | Not configured | TBD* |
Table 9: Module power consumption
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Technical Specifications
Absolute Maximum Ratings
Parameter | Min | Max | Units | Reference document |
|---|---|---|---|---|
VIN supply voltage (5.0V nominal) | -0.3 | 6.0 | V | EP53A7HQI / EP53A7LQI datasheet |
| I/O Input voltage for FPGA I/O bank | -0.3 | 3.63 | V | Microsemi datasheet DS0128 |
Storage Temperature | -40 | +90 | °C | LED R6C-AL1M2VY/3T datasheet |
Table 10: Absolute maximum ratings
Recommended Operating Conditions
| Parameter | Min | Max | Units | Reference document |
|---|---|---|---|---|
| VIN supply voltage (5.0V nominal) | 4.75 | 5.25 | V | same as USB-VBUS specification |
| I/O Input voltage for FPGA I/O bank | 0 | 3.45 | V | Microsemi datasheet DS0128 |
| Operating temperature range | 0 | +70 | °C | Winbond datasheet W9864G6GT |
Table 11: Recommended operating conditions
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Hardware Revision History
| Date | Revision | Notes | PCN | Documentation Link |
|---|---|---|---|---|
| - | 01 |
| - | TEM0001-01 |
Table 12: Module hardware revision history
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Figure 5: Module hardware revision number
Document Change History
| Date | Revision | Contributors | Description | ||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| Ali Naseri |
|
Table 13: Document change history
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