Page History

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1. Intel Cyclone 10LP 10CL025 FPGA SoC, U1
2. Winbond W9864G6JT -6 8 Mbyte SDRAM 166MHz, U2
3. Intel EPCQ16ASI8N 2 MByte serial configuration memory, U5
4. ST Microelectronics LIS3DH MEMS digital output motion sensor, U4
5. FTDI USB2 to JTAG/UART adapter, U3
6. Configuration EEPROM for FTDI chip, U9
7. 12.0000 MHz oscillator, U7
8. 8x red user LEDs, D2 ... D9
9. Red LED (Conf. DONE), D10
10. Green LED (indicating supply voltage), D1
11. Switch Push button (user), S2
12. Switch Push button (reset), S1
13. Micro USB2 B socket (receptacle), J9
14. 1x14 pin header (2.54mm pitch), J2
15. 1x6 pin header (2.54mm pitch), J4
16. 2x6 Pmod connector, J6
17. 3-pin header (2.54mm pitch), J3
18. 1x14 pin header (2.54mm pitch), J1

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Table 2: General overview of single ended I/O signals connected to pin headers and connectors

FPGA I/O banks

Table 3: General overview of FPGA I/O banks

JTAG Interface

Primary JTAG access to the FPGA SoC device U5 is provided through Micro USB2 B connector J9. The JTAG interface is created by the FTDI FT2232H USB2 to JTAG/UART adapter IC U3. 

Optionally 1x6 male pin header J4 can be fitted on board for access to the JTAG interface on board. The pin assignment of header J4 is shown on table below:

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The JTAGSEL pin of SmartFusion2 device depends on the used JTAG programmer. 

Table 4: optional second JTAG interface or GPIO (JTAGSEL dependent)

QSPI Interface

The QSPI interface of the FPGA device is routed to and used by the on-module QSPI flash IC U1:

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Table 3: General overview of FPGA I/O banks

JTAG Interface

Primary JTAG access to the FPGA SoC device U1 is provided through Micro USB2 B connector J9. The JTAG interface is created by the FTDI FT2232H USB2 to JTAG/UART adapter IC U3. 

Optionally 1x6 male pin header J4 can be fitted on board for access to the JTAG interface on board. The pin assignment of header J4 is shown on table below:

Table 4: optional JTAG pin header

On-board Peripherals

Serial Configuration Memory

On-board serial configuration memory (U5) is provided by Intel EPCQ16ASI8N with 16 MBit (2

Table 5: QSPI interface signals

On-board Peripherals

Quad SPI Flash Memory

On-module QSPI flash memory (U7) is provided by Winbond Serial Flash Memory W74M64FV with 64 MBit (8 MByte) storage capacity. This non volatile memory is used to store initial FPGA configuration. Besides FPGA configuration, remaining free flash memory can be used for user application and data storageto store initial FPGA configuration via JTAG interface. The memory is connected to FPGA bank 1 via active serial (AS) x1 interface.

SDRAM

The TEM0001 FPGA module is equipped with a Winbond W9864G6JT 64 MBit (8 MByte) SDRAM chip U2. This SDRAM chip is connected to the FPGA bank 4 7 and 7 8 via 16-bit memory interface with 166MHz clock frequency and CL3 CAS latency.

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The FTDI chip U3 converts signals from USB2.0 to a variety of standard serial and parallel interfaces. Refer to the FTDI data sheet to get information about the capacity of the FT2232H chip.
FTDI FT2232H chip is used in MPPSE mode for JTAG, 2 I/O's of channel A and 6 I/O's of Channel B are routed to the FPGA bank 1 3 of the FPGA SoC and are usable for example as UART interfaceGPIOs, UART or other standard interfaces.

The configuration of FTDI FT2232H chip is pre-programmed on the EEPROM U9.

Motion Sensor

On the TEI0003 FPGA board there is a digital output 3-axis motion sensor present. The motion is provided by ST Microelectronics 

System Clock Oscillator

The FPGA SoC module has following reference clocking signals provided by on-board oscillators:

Table 65: Clock sources overview

On-board LEDs

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Table 6Table 7: LEDs of the module

Push Buttons

The TEM0001 FPGA module is equipped with two push buttons S1 and S2:

Table 87: Push buttons of the module

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Table 12: Module hardware revision history

Hardware revision number is printed on the PCB board together with the module model number separated by the dash.
Image Removed

Figure 5: Module hardware revision number

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