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Table of Contents

Table of Contents


The Trenz Electronic TEI0001 is a low cost small-sized FPGA module integrating a Intel Cyclone 10LP 10CL025 FPGA SoC, 2 MByte serial memory for configuration and operation, 8 MByte SDRAM and a 3-axis accelerometer.

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Key Features

  • Intel Cyclone 10LP 10CL025 FPGA SoC

  • 8 MByte SDRAM
  • 2 MByte serial configuration memory

  • ST Microelectronics LIS3DH 3-axis accelerometer
  • JTAG and UART over Micro USB2 connector
  • 1x6 pin header for JTAG access to FPGA SoC
  • 1x PMOD header providing 8 GPIOs
  • 2x 14-pin headers (2,54 mm pitch) providing 23 GPIOs

  • 1x 3-pin header providing 2 GPIOs
  • 8x user LEDs

  • 1x user push button
  • 5.0V single power supply with on-board voltage regulators
  • Size: 61.5 x 25 mm

Additional assembly options are available for cost or performance optimization upon request.

Block Diagram

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titleFigure 1: TEI0003-02 block diagram
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diagramNameTEI0001 block diagram

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Main Components

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titleFigure 2: TEI0003-02 FPGA module
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  1. Intel Cyclone 10LP 10CL025 FPGA SoC, U1
  2. Winbond W9864G6JT 8 Mbyte SDRAM 166MHz, U2
  3. Intel EPCQ16ASI8N 2 MByte serial configuration memory, U5
  4. ST Microelectronics LIS3DH 3-axis accelerometer, U4
  5. FTDI USB2 to JTAG/UART adapter, U3
  6. Configuration EEPROM for FTDI chip, U9
  7. 12.0000 MHz oscillator, U7
  8. 8x red user LEDs, D2 ... D9
  9. Red LED (Conf. DONE), D10
  10. Green LED (indicating supply voltage), D1
  11. Push button (user), S2
  12. Push button (reset), S1
  13. Micro USB2 B socket (receptacle), J9
  14. 1x14 pin header (2.54mm pitch), J2
  15. 1x6 pin header (2.54mm pitch), J4
  16. 2x6 Pmod connector, J6
  17. 3-pin header (2.54mm pitch), J3
  18. 1x14 pin header (2.54mm pitch), J1

Initial Delivery State

Storage device name



Serial configuration memory, U5

DEMO Design

I2C Configuration EEPROM, U9



Table 1: Initial delivery state of programmable devices on the module

Boot Process

By default the configuration mode pins of the FPGA are set to load the FPGA design from the serial configuration memory, hence the FPGA is configured from serial configuration memory at system start-up. The JTAG interface of the module is provided for storing the initial FPGA configuration data to the serial configuration memory.

Signals, Interfaces and Pins

I/Os on Pin Headers and Connectors

I/O signals of the FPGA SoC's I/O banks connected to the board's pin headers and connectors:

BankConnector DesignatorI/O Signal CountBank VoltageNotes
2J29 I/O's3.3V2 I/O's of bank 2 can be pulled-up to 3.3V (4K7 resistors) with 2 I/O's of same bank or pins can be shared
4J18 I/O's3.3V-
J32 I/O's3.3V-
5J16 I/O's3.3V-
6J68 I/O's3.3VPmod Connector
1J44 I/O's3.3VJTAG interface
J21 Input3.3Vlow active Reset input

Table 2: General overview of single ended I/O signals connected to pin headers and connectors

FPGA I/O banks

BankVCCIOI/O's CountConnected toNotes
13.3V6LIS3DH digital motion sensor, U4SPI interface, 2 interrupt lines
41x6 pin header, J4JTAG interface
42 MByte serial configuration memory, U5FPGA configuration memory with active serial (AS) x1 interface
1J2-10, push button S1 low active reset input
23.3V91x14 pin header, J2GPIOs (2 I/O's of bank 2 can be pulled-up to 3.3V (4K7 resistors) with 2 I/O's of same Bank or pins can be shared)
33.3V8LEDs D2 ... D98 x red user LEDs
8FTDI FT2232H JTAG/UART Adapter, U3configurable as GPIO/UART or other serial interfaces
1push button S2user button
43.3V10pin headers J1, J3GPIOs
53.3V6pin headers J1GPIOs
63.3V8Pmod connector J6GPIOs
1Red LED, D10Configuration DONE Led (ON when configuration in progress, OFF when configuration is done)
73.3V198 Mbyte SDRAM 166MHz, U216bit SD-RAM memory interface
83.3V218 Mbyte SDRAM 166MHz, U216bit SD-RAM memory interface

Table 3: General overview of FPGA I/O banks

JTAG Interface

Primary JTAG access to the FPGA SoC device U1 is provided through Micro USB2 B connector J9. The JTAG interface is created by the FTDI FT2232H USB2 to JTAG/UART adapter IC U3. 

Optionally 1x6 male pin header J4 can be fitted on board for access to the JTAG interface on board. The pin assignment of header J4 is shown on table below:

JTAG SignalPin on Header J4Note

Table 4: optional JTAG pin header

On-board Peripherals

Serial Configuration Memory

On-board serial configuration memory (U5) is provided by Intel EPCQ16ASI8N with 16 MBit (2 MByte) storage capacity. This non volatile memory is used to store initial FPGA configuration via JTAG interface. The memory is connected to FPGA bank 1 via active serial (AS) x1 interface.

Serial Memory U5 PinSignal Schematic NameConnected toNotes
Pin 2, DATA1AS_DATA0FPGA bank 1, pin H2
Data out
Pin 5, DATA0AS_ASDOFPGA bank 1, pin C1Data in
Pin 1, nCSAS_NCSFPGA bank 1, pin D2chip select

FPGA bank 1, pin H1


Table 5: Serial configuration memory interface connections


The FPGA module is equipped with a Winbond W9864G6JT 64 MBit (8 MByte) SDRAM chip U2. This SDRAM chip is connected to the FPGA bank 7 and 8 via 16-bit memory interface with 166MHz clock frequency and CL3 CAS latency.

SDRAM I/O Signals

Signal Schematic Name

Connected toNotes
Address inputs

A0 ... A13

bank 8-
Bank address inputs

BA0 / BA1

bank 8

Data input/output

DQ0 ... DQ15

bank 7

Data mask

DQM0 ... DQM1

bank 7

ClockCLKbank 7
Control Signals


bank 8

Chip select


bank 8

Clock enable


bank 8

Row Address Strobe


bank 8

Column Address Strobe

WEbank 8Write Enable

Table 6: 16bit SDRAM memory interface

FTDI FT2232H Chip

The FTDI chip U3 converts signals from USB2.0 to a variety of standard serial and parallel interfaces. Refer to the FTDI data sheet to get information about the capacity of the FT2232H chip.
FTDI FT2232H chip is used in MPPSE mode for JTAG, 2 I/O's of channel A and 6 I/O's of Channel B are routed to FPGA bank 3 of the FPGA SoC and are usable for example as GPIOs, UART or other standard interfaces.

The configuration of FTDI FT2232H chip is pre-programmed on the EEPROM U9.

FTDI Chip U3 PinSignal Schematic NameConnected toNotes
Pin 12, ADBUS0TCKFPGA bank 1, pin H3
JTAG interface
Pin 13, ADBUS1TDIFPGA bank 1, pin H4
Pin 14, ADBUS2TDOFPGA bank 1, pin J4

FPGA bank 1, pin J5

Pin 17, ADBUS4ADBUS4FPGA bank 3, pin M8user configurable
Pin 20, ADBUS7ADBUS7FPGA bank 3, pin N8user configurable
Pin 32, BDBUS0BDBUS0FPGA bank 3, pin user configurable
Pin 33, BDBUS1BDBUS1FPGA bank 3, pin user configurable
Pin 34, BDBUS2BDBUS2FPGA bank 3, pin user configurable
Pin 35, BDBUS3BDBUS3FPGA bank 3, pin user configurable
Pin 37, BDBUS4BDBUS4FPGA bank 3, pin user configurable
Pin 38, BDBUS5BDBUS5FPGA bank 3, pin user configurable

Table 7: FTDI chip interfaces and pins

3-Axis Accelerometer

On the TEI0003 FPGA board there is a 3-axis accelerometer present. This accelerometer provided by ST Microelectronics LIS3DH and offers many function to detect motion and has also a temperature sensor integrated. It also has a FIFO buffer for storing output data. The sensor is connected to the FPGA through SPI interface and two interrupt lines.

Accelerometer U4 PinSignal Schematic NameConnected toNotes
Pin 11, INT1SEN_INT1FPGA bank 1, pin B1
Interrupt lines
Pin 9, INT2SEN_INT2FPGA bank 1, pin C2
Pin 6, SDA/SDI/SDOSEN_SDIFPGA bank 1, pin G2SPI interface


FPGA bank 1, pin G1

Pin 4, SCL/SPCSEN_SPCFPGA bank 1, pin F3
Pin 8, CSSEN_CSFPGA bank 1, pin D1
Pin 13, ADC3ADC35VSense 5V input voltage

Table 8: 3-axis accelerometer interfaces and pins

System Clock Oscillator

The FPGA SoC module has following reference clocking signals provided by on-board oscillators:

Clock SourceSchematic NameFrequencyClock Input Destination
Microchip MEMS Oscillator, U7CLK12M12.0000 MHzFTDI FT2232 U3, pin 3; FPGA SoC bank 2, pin M2
optional Microchip MEMS Oscillator, U6 (not fitted)CLK_X-FPGA SoC bank 6, pin E15

Table 9: Clock sources overview

On-board LEDs

There are 10 LEDs fitted on the FPGA module board. The LEDs are user configurable to indicate for example any system status.

LEDColorSignal Schematic NameFPGANotes
D1Green--Indicating 3.3V board supply voltage
D2Red'LED1'bank 6, pin M6user
D3Red'LED2'bank 6, pin T4user
D4Red'LED3'bank 6, pin T3user
D5Red'LED4'bank 6, pin R3user
D6Red'LED5'bank 6, pin T2user
D7Red'LED6'bank 6, pin R4user
D8Red'LED7'bank 6, pin N5user
D9Red'LED8'bank 6, pin N3user
D10Red'CONF_DONE'bank 6, pin H14indication configuration is DONE when LED is off

Table 10: LEDs of the module

Push Buttons

The FPGA module is equipped with two push buttons S1 and S2:

ButtonSignal Schematic NameFPGANotes
S1'USER_BTN'bank 3, pin N6user configurable
S2'RESET'bank 1, pin H5system reset

Table 11: Push buttons of the module


All connectors are are for 100mil headers, all connector locations are in 100mil (2.54mm) grid. The module's PCB provides footprints to mount and solder optional pin headers, if those are not factory-fitted on module.

Power and Power-On Sequence

To power-up a module, power supply with minimum current capability of 1A is recommended.

Power Supply

The FPGA module can be power-supplied through Micro USB2 connector J9 with supply voltage 'USB-VBUS' or alternative through pin header J2 with supply voltage 'VIN'.

The TEI0003 module needs one single power supply of 5.0V nominal.

There are following dependencies how the initial voltage of the extern power supply is distributed to the on-board DCDC converters:

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titleFigure 3: Power Distribution Diagram
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Power Consumption

FPGADesignTypical Power, 25C ambient
Intel Cyclone 10LP 10CL025 FPGA SoCNot configuredTBD*

Table 12: Module power consumption

*TBD - To Be Determined.

Actual power consumption depends on the FPGA design and ambient temperature.

Power-On Sequence

There is no specific or special power-on sequence, just one single power source is needed.

Power Rails

Connector DesignatorVCC / VCCIO Schematic NameVoltageDirectionPinsNotes
J25V5.0VOutPin 14-
VIN5.0VInPin 13-
3.3V3.3VOutPin 12-



OutPin 6, 12-


5.0VInPin 1-

Table 13: Connector power pin description

Bank Voltages



Voltage Range

13.3Vall bank voltages fixed

Table 14: FPGA SoC VCCO bank voltages

Technical Specifications

Absolute Maximum Ratings




Reference document

VIN supply voltage (5.0V nominal)




EP53A7HQI / EP53A7LQI datasheet
I/O Input voltage for FPGA I/O bank-0.54.2VIntel Cyclone 10 LP datasheet

Storage Temperature




LED R6C-AL1M2VY/3T datasheet

Table 15: Absolute maximum ratings

Recommended Operating Conditions

ParameterMinMaxUnitsReference document
VIN supply voltage (5.0V nominal)4.755.25Vsame as USB-VBUS specification
I/O Input voltage for FPGA I/O bank–0.53.6VIntel Cyclone 10 LP datasheet
Operating temperature range0+70


Winbond datasheet W9864G6GT

Table 16: Recommended operating conditions

Please check Intel Cyclone 10 LP datasheet  for complete list of absolute maximum and recommended operating ratings for the FPGA device.

Physical Dimensions

Please note that two different units are used on the figures below, SI system millimeters (mm) and imperial system thousandths of an inch(mil). This is because of the 100mil pin headers used, see also explanation below. To convert mils to millimeters and vice versa use formula 100mil's = 2,54mm.

  • Board size: PCB 25mm × 61,5mm. Notice that some parts the are hanging slightly over the edge of the PCB like the the Micro USB2 B connector, which determine the total physical dimensions of the carrier board. Please download the assembly diagram for exact numbers.

  • PCB thickness: ca. 1.65mm

  • Highest part on the PCB without fitted headers and connectors is the Micro USB2 B connector, which has an approximately hight of 3 mm. Please download the step model for exact numbers.


Scroll Title
titleFigure 4: Module physical dimensions drawing

Revision History

Hardware Revision History



PCNDocumentation Link


First Production Release


Table 17: Module hardware revision history

Hardware revision number is printed on the PCB board together with the module model number separated by the dash.

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titleFigure 5: Module hardware revision number

Document Change History




Page info

Page info
infoTypeCurrent version

Ali Naseri

  • First TRM release

Table 18: Document change history


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