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The Trenz Electronic TEI0001 is a low cost small-sized FPGA module integrating a Intel Cyclone 10LP 10CL025 MAX 10 FPGA SoC, 2 8 MByte serial memory for configuration and operation, 8 MByte SDRAM and a 3-axis accelerometer.

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titleFigure 1: TEI0003-02 block diagram
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Main Components

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titleFigure 2: TEI0003-02 FPGA module
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  1. Intel MAX10 MAX 10 10M08 FPGA SoC, U1
  2. 8 Mbyte SDRAM 166MHz, U2
  3. 8 Mbyte QSPI Flash memory, U5
  4. ST Microelectronics LIS3DH 3-axis accelerometer, U4
  5. FTDI USB2 to JTAG/UART adapter, U3
  6. Configuration EEPROM for FTDI chip, U9
  7. 12.0000 MHz oscillator, U7
  8. 8x red user LEDs, D2 ... D9
  9. Red LED (Conf. DONE), D10
  10. Green LED (indicating supply voltage), D1
  11. Push button (user), S2
  12. Push button (reset), S1
  13. Micro USB2 B socket (receptacle), J9
  14. 1x14 pin header (2.54mm pitch), J2
  15. 1x6 pin header (2.54mm pitch), J4
  16. 2x6 Pmod connector, J6
  17. 3-pin header (2.54mm pitch), J3
  18. 1x14 pin header (2.54mm pitch), J1

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Table 1: Initial delivery state of programmable devices on the module

Boot Process

By default the configuration mode pins of the FPGA are set to load the FPGA design from the serial configuration memory, hence the FPGA is configured from serial configuration memory at system start-up. The JTAG interface of the module is provided for storing the initial FPGA configuration data to the serial configuration memoryThe FPGA configuration for Intel MAX 10 FPGAs can be stored through JTAG interface either in external configuration device (QSPI flash memory U5) or on the FPGA itself since the Intel MAX 10 FPGA offers non-volatile memory on chip. The FPGA configuration is loaded from the non-volatile memory when the board is powered up.

To configure the FPGA directly, the JTAG interface can be used to configure the FPGA volatile, means the configuration is lost after power off.

Signals, Interfaces and Pins

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2 46 4 I/O
BankConnector DesignatorI/O Signal CountBank VoltageNotes
2J2J19 4 I/O's3.3V-
J68 I/O's of bank 2 can be pulled-up to 3.3V (4K7 resistors) with 2 I/O's of same bank or pins can be sharedPmod connector
5J18 2 I/O's3.3V-
J3J22 9 I/O's3.3V-5J12 I/O's 3.3V-6J68 I/O'sof bank 5 can be pulled-up to 3.3V Pmod Connector1J4(4K7 resistors)
1AJ17 analog inputs or GPIO's3.3VJTAG interfaceJ21 Input3.3Vlow active Reset inputAnalog reference voltage (AREF) on pin J1-1
J31 analog inputs or GPIO, 1 dedicated analog input1 pin of bank 1A is dedicated analog input (AIN), other are also GPIO's as alternative function
1BJ4JTAG interface (4 I/O's)3.3VJTAG enable signal (JTAGEN) on pin J4-2, leave floating when using JTAG interface

Table 2: General overview of single ended I/O signals connected to pin headers and connectors

FPGA I/O banks

63.3V
BankVCCIOI/O's CountConnected toNotes
13.3V24LIS3DH digital motion sensor, U4SPI interface, 2 interrupt lines
481x6 pin header, J4JTAG interface
42 MByte serial configuration memory, U5FPGA configuration memory with active serial (AS) x1 interface
1J2-10, push button S1 low active reset input2input
591x14 pin header, J2GPIOs (2 I/O's of bank 2 can be pulled-up to 3.3V (4K7 resistors) with 2 I/O's of same Bank or pins can be shared)
1A8LEDs D2 ... D98 x red user LEDs
8FTDI FT2232H JTAG/UART Adapter, U3configurable as GPIO/UART or other serial interfaces
1push button S2user button
1B10pin headers J1, J3GPIOs
56pin headers J1GPIOs
68Pmod connector J6GPIOs
1Red LED, D10Configuration DONE Led (ON when configuration in progress, OFF when configuration is done)
7198 Mbyte SDRAM 166MHz, U216bit SD-RAM memory interface
8218 Mbyte SDRAM 166MHz, U216bit SD-RAM memory interface

Table 3: General overview of FPGA I/O banks




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BankI/O's CountConnected toNotes
241x14 pin header, J1-
8Pmod connector, J6-
1clock oscillator, U712.0000 MHz reference clock input
1optional clock oscillator, U6footprints available for Microchip MEMS oscillator
591x14 pin header, J2
GPIOs (
2 I/O's (D11, D12) of bank
2
5 can be pulled-up to 3.3V (4K7 resistors) with
2
1 I/O
's of same Bank or pins can be shared)33.3V8LEDs D2 ... D98 x red user LEDs8FTDI FT2232H JTAG/UART Adapter, U3configurable as GPIO/UART or other serial interfaces1push button S2user button43.3V10
(D12_R) of same Bank and 1 I/O (D11_R) of bank 6
6188 Mbyte SDRAM 166MHz, U216bit SD-RAM memory interface
322pin headers J1, J3GPIOs
5
3.3V
6pin headers J1GPIOs
6
3.3V
8Pmod connector J6GPIOs
1Red LED, D10Configuration DONE Led (ON when configuration in progress, OFF when configuration is done)
7
3.3V
198 Mbyte SDRAM 166MHz, U216bit SD-RAM memory interface
8
3.3V
8218 Mbyte SDRAM 166MHz, U216bit SD-RAM memory interface

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JTAG Interface

Primary JTAG access to the FPGA SoC device U1 is provided through Micro USB2 B connector J9. The JTAG interface is created by the FTDI FT2232H USB2 to JTAG/UART adapter IC U3. 

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JTAG SignalPin on Header J4Note
TCK3-
TDI5-
TDO4-
TMS6-
JTAGEN5-

Table 4: optional JTAG pin header

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On-board serial configuration memory (U5) is provided by Intel EPCQ16ASI8N Winbond W74M64FVSSIQ with 16 64 MBit (2 8 MByte) storage capacity. This non volatile memory is used to store initial FPGA configuration via JTAG interface. The memory is connected to FPGA bank 1 via active serial (AS) x1 SPI interface.

Serial Memory U5 PinSignal Schematic NameConnected toNotes
Pin 2, DATA1AS_DATA0FPGA bank 1, pin H2
Data out
Pin 5, DATA0AS_ASDOFPGA bank 1, pin C1Data in
Pin 1, nCSAS_NCSFPGA bank 1, pin D2chip select
Pin 6, DCLKAS_DCLK

FPGA bank 1, pin H1

clock

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titleFigure 3: Power Distribution Diagram
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FPGADesignTypical Power, 25C ambient
Intel Cyclone 10LP 10CL025 MAX 10 10M08 FPGA SoCNot configuredTBD*

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Parameter

MinMax

Units

Reference document

VIN supply voltage (5.0V nominal)

-0.3

6.0

V

EP53A7HQI / EP53A7LQI datasheet
I/O Input voltage for FPGA I/O bank-0.54.2VIntel Cyclone MAX 10 LP datasheet

Storage Temperature

-40

+90

°C

LED R6C-AL1M2VY/3T datasheet

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ParameterMinMaxUnitsReference document
VIN supply voltage (5.0V nominal)4.755.25Vsame as USB-VBUS specification
I/O Input voltage for FPGA I/O bank–0.53.6VIntel Cyclone MAX 10 LP datasheet
Operating temperature range0+70

°C

Winbond datasheet W9864G6GT

Table 16: Recommended operating conditions

Note
Please check Intel MAX10 MAX 10 datasheet  for complete list of absolute maximum and recommended operating ratings for the FPGA device.

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