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Online version of this manual and other related documents can be found at https://wiki.trenz-electronic.de/display/PD/Trenz+Electronic+Documentation

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Overview

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Example show, how to reconfigure SI5338 with MCS and monitor CLK. Additional MicroBlaze is add for Hello TE0741 example.

Key Features

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Excerpt
MGT SI5338 initialisation with MCS

Revision History

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Date	Vivado	Project Built	Authors	Description
2018-06-05	2017.4	TE0841-IBERT_noprebuilt-vivado_2017.4-build_10_20180605143852.zip TE0841-IBERT-vivado_2017.4-build_10_20180605143837.zip	John Hartfiel	initial release

Release Notes and Know Issues

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Issues	Description	Workaround	To be fixed version
---	---	---	---

Requirements

Software

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Software	Version	Note
Vivado	2017.4	needed
SDK	2017.4	needed

Hardware

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Basic description of TE Board Part Files is available on TE Board Part Files.

Complete List is available on <design name>/board_files/*_board_files.csv

Design supports following modules:

Module Model	Board Part Short Name	PCB Revision Support	DDR	QSPI Flash	Others
TE0841-01-035-1C	01_35_1c	REV01	2x 512MB DDR4	32MB	---
TE0841-01-035-1I	01_35_1i	REV01	2x 512MB DDR4	32MB	---
TE0841-01-035-2I	01_35_2i	REV01	2x 512MB DDR4	32MB	---
TE0841-01-040-1C	01_40_1c	REV01	2x 512MB DDR4	32MB	---
TE0841-01-040-1I	01_40_1i	REV01	2x 512MB DDR4	32MB	---
TE0841-01-040-2I	01_40_2i	REV01	2x 512MB DDR4	32MB	---

Design supports following carriers:

Carrier Model	Notes
TEBA0841	used as reference carrier

Additional HW Requirements:

Additional Hardware	Notes
USB Cable for JTAG/UART	Check Carrier Board and Programmer for correct type
XMOD Programmer	Carrier Board dependent, only if carrier has no own FTDI
Heat sink	It's recommended to use heat sink for this design

Content

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For general structure and of the reference design, see Project Delivery

Design Sources

Type	Location	Notes
Vivado	<design name>/block_design <design name>/constraints <design name>/ip_lib <design name>/firmware	Vivado Project will be generated by TE Scripts
SDK/HSI	<design name>/sw_lib	Additional Software Template for SDK/HSI and apps_list.csv with settings for HSI

Additional Sources

Type	Location	Notes
SI5338 Project	\misc\SI5338

Prebuilt

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<table width="100%">
<tr> <th>File                                 </th> <th>File-Extension</th>  <th>Description                                                                              </th> </tr>
<tr> <td>BIF-File                             </td> <td>*.bif         </td>  <td>File with description to generate Bin-File                                               </td> </tr>
<tr> <td>BIN-File                             </td> <td>*.bin         </td>  <td>Flash Configuration File with Boot-Image (Zynq-FPGAs)                                    </td> </tr>
<tr> <td>BIT-File                             </td> <td>*.bit         </td>  <td>FPGA Configuration File                                                                  </td> </tr>
<tr> <td>DebugProbes-File                     </td> <td>*.ltx         </td>  <td>Definition File for Vivado/Vivado Labtools Debugging Interface                           </td> </tr>
<tr> <td>Debian SD-Image                      </td> <td>*.img         </td>  <td>Debian Image for SD-Card                                                                </td> </tr>
<tr> <td>Diverse Reports                      </td> <td>  ---         </td>  <td>Report files in different formats                                                        </td> </tr>
<tr> <td>Hardware-Platform-Specification-Files</td> <td>*.hdf         </td>  <td>Exported Vivado Hardware Specification for SDK/HSI                                       </td> </tr>
<tr> <td>LabTools Project-File                </td> <td>*.lpr         </td>  <td>Vivado Labtools Project File                                                             </td> </tr>
<tr> <td>MCS-File                             </td> <td>*.mcs         </td>  <td>Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)                  </td> </tr>
<tr> <td>MMI-File                             </td> <td>*.mmi         </td>  <td>File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only) </td> </tr>
<tr> <td>OS-Image                             </td> <td>*.ub          </td>  <td>Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)             </td> </tr>
<tr> <td>Software-Application-File            </td> <td>*.elf         </td>  <td>Software Application for Zynq or MicroBlaze Processor Systems                            </td> </tr>
<tr> <td>SREC-File                            </td> <td>*.srec        </td>  <td>Converted Software Application for MicroBlaze Processor Systems                          </td> </tr>    
</table>
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File	File-Extension	Description
BIT-File	*.bit	FPGA (PL Part) Configuration File
DebugProbes-File	*.ltx	Definition File for Vivado/Vivado Labtools Debugging Interface
Diverse Reports	---	Report files in different formats
Hardware-Platform-Specification-Files	*.hdf	Exported Vivado Hardware Specification for SDK/HSI and PetaLinux
LabTools Project-File	*.lpr	Vivado Labtools Project File
MCS-File	*.mcs	Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)
MMI-File	*.mmi	File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)
Software-Application-File	*.elf	Software Application for Zynq or MicroBlaze Processor Systems

Download

Reference Design is only usable with the specified Vivado/SDK/PetaLinux/SDx version. Do never use different Versions of Xilinx Software for the same Project.

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Reference Design is available on:

TE0841 "IBERT" Reference Design

Design Flow

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Note
Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first lunch.

Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.

Launch

Programming

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Note
Check Module and Carrier TRMs for proper HW configuration before you try any design.

Xilinx documentation for programming and debugging: Vivado/SDK/SDSoC-Xilinx Software Programming and Debugging

QSPI

Connect JTAG and power on PCB
(if not done) Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd" or open with "vivado_open_project_guimode.cmd", if generated.
Type on Vivado Console: TE::pr_program_flash_mcsfile -swapp
Note: Alternative use SDK or setup Flash on Vivado manually
Reboot (if not done automatically)

SD

Not used on this Example.

JTAG

Connect JTAG and power on PCB
Open Vivado HW Manager
Program FPGA with Bitfile from "prebuilt\hardware\<short dir>"

Usage

Prepare HW like described on section Programming
Connect UART USB (most cases same as JTAG)
Power on PCB
Note: FPGA Loads Bitfile from Flash,MCS Firmware configure SI5338 and starts IBERT.
Do not reboot, if Bitfile programming over JTAG is used as programming method.
1. On TE0841 SI5338 has default configuration and reprogramming of SI5338 is optional
LED:
1. D1 (green) OFF→ MCS SI configuration finished (System Reset is off)

Vivado HW Manager:

Open Vivado HW-Manager
"Refresh device" is needed after Bitfile programming, because MCS reconfigure SI5338 and enables IBERT a little bit later.
1. loopback depends on TEB0841 Revision an connection

IBERT	Component Name	Net Name	TEB0841
X0Y0	224-0	MGT4	loop back RX/TX
X0Y1	224-1	MGT5	loop back RX/TX
X0Y2	224-2	MGT6	loopback over SD Pin header possible with lower Linerate otherwise use internal loopback
X0Y3	224-3	MGT7	loop back RX/TX. Note: N.C. on TEB0841-01, use internal loopback
X0Y4	225-0	MGT0	loop back RX/TX
X0Y5	225-1	MGT1	loop back RX/TX
X0Y6	225-2	MGT2	loop back RX/TX
X0Y7	225-3	MGT3	loopback over sfp possible

System Design - Vivado

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Block Design

HDL

IBERT_top.v
ibert xci IPs

Constrains

Basic module constrains

Code Block

language	ruby
title	_i_bitgen_common.xdc

set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property BITSTREAM.CONFIG.CONFIGRATE 69 [current_design]
set_property CFGBVS GND [current_design]
set_property CONFIG_VOLTAGE 1.8 [current_design]
set_property CONFIG_MODE SPIx4 [current_design]
set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design]
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
set_property BITSTREAM.CONFIG.M1PIN PULLNONE [current_design]
set_property BITSTREAM.CONFIG.M2PIN PULLNONE [current_design]
set_property BITSTREAM.CONFIG.M0PIN PULLNONE [current_design]

set_property BITSTREAM.CONFIG.USR_ACCESS TIMESTAMP [current_design]

Design specific constrain

Code Block

language	ruby
title	ibert_ultrascale_gth_0.xdc
linenumbers	true

# file: ibert_ultrascale_gth_0.xdc
####################################################################################
##   ____  ____ 
##  /   /\/   /
## /___/  \  /    Vendor: Xilinx
## \   \   \/     Version : 2012.3
##  \   \         Application : IBERT Ultrascale
##  /   /         Filename : example_ibert_ultrascale_gth_0.xdc
## /___/   /\     
## \   \  /  \ 
##  \___\/\___\
##
##
## 
## Generated by Xilinx IBERT 7Series 
##**************************************************************************
##
## Icon Constraints
##
create_clock -name D_CLK -period 10.0 [get_ports gth_sysclkp_i]
set_clock_groups -group [get_clocks D_CLK -include_generated_clocks] -asynchronous
set_property C_CLK_INPUT_FREQ_HZ 100000000 [get_debug_cores dbg_hub]
set_property C_ENABLE_CLK_DIVIDER true [get_debug_cores dbg_hub]

##gth_refclk lock constraints
##
set_property PACKAGE_PIN AD6 [get_ports gth_refclk0p_i[0]]
set_property PACKAGE_PIN AD5 [get_ports gth_refclk0n_i[0]]
set_property PACKAGE_PIN AB6 [get_ports gth_refclk1p_i[0]]
set_property PACKAGE_PIN AB5 [get_ports gth_refclk1n_i[0]]
##
## Refclk constraints
##
create_clock -name gth_refclk0_0 -period 8.0 [get_ports gth_refclk0p_i[0]]
create_clock -name gth_refclk1_0 -period 8.0 [get_ports gth_refclk1p_i[0]]
set_clock_groups -group [get_clocks gth_refclk0_0 -include_generated_clocks] -asynchronous
set_clock_groups -group [get_clocks gth_refclk1_0 -include_generated_clocks] -asynchronous
##
## System clock pin locs and timing constraints
##
set_property PACKAGE_PIN R25 [get_ports gth_sysclkp_i]
set_property IOSTANDARD LVDS [get_ports gth_sysclkp_i]

Software Design - SDK/HSI

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For SDK project creation, follow instructions from:

SDK Projects

Application

SCU

MCS Firmware to configure SI5338 and Reset System.

Template location: \sw_lib\sw_apps\scu

Additional Software

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SI5338

Download ClockBuilder Desktop for SI5338

Install and start ClockBuilder
Select SI5338
Options → Open register map file
Note: File location <design name>/misc/Si5338/RegisterMap.txt
Modify settings
Options → save C code header files
Replace Header files from SCU template with generated file

Appx. A: Change History and Legal Notices

Document Change History

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Document Revision

Authors

Description

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dateFormat	yyyy-MM-dd

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prefix	v.

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Release 2017.4

2018-04-16

v.1

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Initial release

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Legal Notices

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Trenz Electronic Documentation

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Key

Table of contents

Overview

Key Features

Revision History

Release Notes and Know Issues

Requirements

Software

Hardware

Content

Design Sources

Additional Sources

Prebuilt

Download

Design Flow

Launch

Programming

QSPI

SD

JTAG

Usage

Vivado HW Manager:

System Design - Vivado

Block Design

HDL

Constrains

Basic module constrains

Design specific constrain

Software Design - SDK/HSI

Application

SCU

Additional Software

SI5338

Appx. A: Change History and Legal Notices

Document Change History

Legal Notices