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Table 3: General overview of FPGA I/O banks
| Bank | I/O's Count | Connected to | Notes |
|---|---|---|---|
| 2 | 4 | 1x14 pin header, J1 | - |
| 8 | Pmod connector, J6 | - | |
| 1 | clock oscillator, U7 | 12.0000 MHz reference clock input | |
| 1 | optional clock oscillator, U6 | footprints available for Microchip MEMS oscillator | |
| 5 | 9 | 1x14 pin header, J2 | 2 I/O's (D11, D12) of bank 5 can be pulled-up to 3.3V (4K7 resistors) with 1 I/O (D12_R) of same Bank and 1 I/O (D11_R) of bank 6 |
| 6 | 18 | 8 Mbyte SDRAM 166MHz, U2 | 16bit SD-RAM memory interface |
| 3 | 22 | 8 Mbyte SDRAM 166MHz, U2 | 16bit SD-RAM memory interface |
| 6 | LIS3DH 3-axis accelerometer, U4 | 4 I/O's for SPI interface, 2 interrupt lines | |
| 1A | 7 | 1x14 pin headers J1 |
| 7 analog inputs or GPIO's, 1 pin analog reference voltage input | |
| 2 |
| pin headers J1 |
| 6 | 8 | Pmod connector J6 | GPIOs |
| 1 | Red LED, D10 | Configuration DONE Led (ON when configuration in progress, OFF when configuration is done) | |
| 7 | 19 | 8 Mbyte SDRAM 166MHz, U2 | 16bit SD-RAM memory interface |
| 8 | 21 | 8 Mbyte SDRAM 166MHz, U2 | 16bit SD-RAM memory interface |
JTAG Interface
Primary JTAG access to the FPGA SoC device U1 is provided through Micro USB2 B connector J9. The JTAG interface is created by the FTDI FT2232H USB2 to JTAG/UART adapter IC U3.
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